This document describes the fabrication and characterization of vertically stacked silicon nanowire field effect transistors for biosensing applications. A process using BOSCH etching and sacrificial oxidation is developed to create arrays of vertically stacked silicon nanowires with diameters less than 40 nm, lengths over 1 micron, and densities up to 10 nanowires per micron. The nanowires are electrically characterized in dry and liquid conditions, showing good electrostatic control in liquid with subthreshold swings of 100 mV/decade and on-currents over 2 mA/micron. The vertically stacked nanowire design and fabrication process aim to increase the sensitivity of field effect transistor biosensors.

1. IC Device 1(Technology 1)
MetallisationSystem 1
IC Device 2(Technology 2) with TSV
MetallisationSystem 2
IC Device 2(Technology 2) with TSV
MetallisationSystem 2Metallisation
MEMS/NEMS Device
possibly withTSV
Cap -Chip (Wafer)
MEMS/NEMS Device
possibly withTSV
Cap -Chip (Wafer)
MEMS/NEMS Device
possibly with TSV
Cap -Chip (Wafer)
e-BRAINS
High Performance Vertically Stacked
SiNW/Fin Based 3D FET for Biosensing
Applications
Elizabeth Buitrago

2. E. Buitrago
o Introduction
o Fabrication
o Vertically stacked fabrication approaches
o Short-loop and process flow
o Electrical characterization
o Dry characterization after SiNW release
o Liquid gated experiments
o Sensor testing
o Surface modification, fluid delivery, experimental set-up
o pH and streptavidin sensing
o Vertically stacked FET sensor in Bulk Si
o Conclusions
Outline
2

3. E. Buitrago
𝑉𝑡ℎ = 𝑉𝑅𝑒𝑓 − 𝜑0 + 𝜒 𝑠𝑜𝑙
−
𝜙 𝑆𝑖
𝑞
−
𝑄 𝑜𝑥 + 𝑄𝑠𝑠 + 𝑄 𝐵
𝐶 𝑜𝑥
+ 2𝜙 𝑓
Introduction
Principle of Operation
The planar ISFET (ion sensitive field effect transistor)
ISFET
Only φ0 (solution-insulator potential) changes
as function of pH.
Bergveld, IEEE Trans. Biomed. Eng. 1970, BME-17, 70-71.
𝑉𝑡ℎ =
𝜙 𝑀 − 𝜙 𝑆𝑖
𝑞
−
𝑄 𝑜𝑥 + 𝑄𝑠𝑠 + 𝑄 𝐵
𝐶 𝑜𝑥
+ 2𝜙 𝑓
𝐼 𝑑 = 𝜇𝐶 𝑜𝑥
𝑊
𝐿
𝑉𝐺 − 𝑉𝑡ℎ 𝑉𝑑 −
1
2
𝑉𝑑
2
MOSFET
Threshold voltage shift ΔVth  pH concentration changes
observed in Id (Bergveld model).
𝛿𝜑0
𝛿𝑝𝐻
= −2.3
𝑘𝑇
𝑞
𝛼 (SB − model)
Id(draincurrent)
ΔVth
VG (gate voltage)
3

4. E. Buitrago
Introduction
4
Why FET Based and Si-Nanostructures for Sensing?
o High sensitivity  from planar
ISFET to 3D SiNWs:
o Nanoscale  high S/V
o Cross section modulation vs.
surface only
o High selectivity:
o Selectivity/specificity through
surface functionalization
(proteins, DNA, viruses, etc.)
o Direct monitoring:
o Label free
o Real time detection
o Fast, POC, low cost
Specific detection of disease biomarkers
with high sensitivity at ultra-low
concentrations in a direct, non-invasive,
real time manner is sometimes necessary.
Diagnosis of asymptomatic and
aggressive diseases at early stage.
Application Example: Colon cancer
diagnosis
From: BIOS/Lab on a Chip Group, University of Twente
http://www.utwente.nl/onderzoek/themas/health/e
n/lab-on-a-chip/lab-on-a-chip/nanopil/
colonoscopy
nanopill ingestion

5. E. Buitrago
Introduction
5
Why Si-Nanostructure 2D Arrays?
o Increased chances for biomolecule
interaction.
o Increased number of sensing channels.
o Increased output currents Ion.
o Increased number of conduction
channels.
o Reduced device-to-device variation:[1]
o Less variation of Vth, SS and gm,max vs.
single SiNWs device.
o Reduction of variation caused by random
dopant fluctuation  low doped
channels (for high sensitivities).
 Can we go one step further?
[1] Regonda et al. Biosens. Bioelectron. 2013, 45, 245-251.

6. E. Buitrago
o Higher chances for biomolecule
interactions for sensing:
o High number of sensing channels in
two directions.
o Suspended structures  entire
SiNW surface area available for
sensing.
o Higher output currents Id:
o High number of conduction
channels.
o Higher utilization of Si substrate:
o High number of SiNW without
increasing Si-footprint.
Introduction
6
Why 3D Vertically Stacked SiNW/Fin FET Sensor?
y
z
x

7. E. Buitrago
o SiNWs stacked in between
S/D anchors
o Device operated by SGs,
VRef, VBG through liquid
Introduction
7
Objective
Develop vertically stacked SiNW/Fin FET
biosensor to be integrated into a 3D
heterogeneous system (e-BRAINS + SiNAPS).

8. E. Buitrago
o Structure:
o Ultra-thin (high S/V) NWs < 40 nm
o Medium NW array density > 5 SiNWs/μm
o Long channels > 1 μm
o Uniformly distributed array
o Uniform NW diameters
o Fabrication process flow:
o Top-Down, CMOS compatible
o Cost effective
o Heterogeneous integration TSV
compatibility
o Suspended and thin, possibly fragile
o Fluid delivery, isolation, topography
o Availability (CMi)
Fabrication
8
Structure and Fabrication Requirements
y
z
x

9. E. Buitrago
o Fabrication:
o Si (110) wafer etched (1) by KOH
anisotropically.
o Metal evaporation at an angle (2).
o Metal (Ti, Au) catalyzed growth of SiNWs on
(111) sidewall (3) to bridge opposite wall (4).
o Advantages and limitations
(‒) Bottom-up, not CMOS compatible
(+) Cheap, no high resolution lithography needed
(+) Medium vertical density ~ 5 NWs/μm
(‒) Non-uniform NW thickness
(‒) Random growth
(‒) NW length limited by trench opening
(‒) Not ultra-thin NW diameters possible > 90 nm
Fabrication
9
VLS-CVD Growth
Fabrication aproach: Vapor liquid solid (VLS) chemical vapor deposition (CVD) growth
Islam et al. Nanotechnology. 2004, 15, L5. (Hewlett Packard, USA)
(1) (2)
(3) (4)

10. E. Buitrago
Fabrication
10
Stacked SiGe NW Array
Fabrication aproach: epitaxial growth Si/SiGe and patterning
[1]
[2]
(1)
(2)
(3)
[1] Bera et al. IEDM, 2006, 298. (A-Star, Singapore), [2] Ernst et al. IEDM, 2006, 740. (CEA-LETI, France)
o Fabrication:
o Si and SiGe(buffer)/Ge multi-layer (1) epitaxial growth.
o Fin patterning by RIE (2).
o NW formation (3) by the selective isotropic etch of
sacrificial SiGe/Ge.
o Advantages and limitations:
(+) Top-down, CMOS compatible
(‒) Epitaxial growth is expensive and complicated
(~) Ultra-high vertical NW density, not necessary
(+) Uniform NW thickness
(~) Ultra-thin NWs, limited thickness, only Si-nanoribbons
or NWs possible due to lattice mismatch
(+) NWs uniformly stacked

11. E. Buitrago
o Fabrication:
o BOSCH (1).
o Thermal oxidation (2).
o BHF oxide removal (3).
o Advantages and limitations
(+) Top-down, CMOS compatible
(+) Cheap, no high resolution lithography
needed  NW diameter further scaled
by oxidation
(+) Medium to high vertical density
(‒) Optimization can be time consuming
(+) NWs uniformly distributed
(+) Ultra-thin NWs possible < 40 nm
Fabrication
11
BOSCH and Sacrificial Oxidation
Fabrication aproach: BOSCH + thermal oxidation + BHF release
Doherty et al. ISCAS, 2003, 934. (Berkeley, USA)
Ng et al. EDSSC, 2007, 133.
(1)
(2)
(3)

12. E. Buitrago
Approach Top-
down
CMOS
compatible
Heterogeneo
us integration
NW
diameters
< 40 nm
when
suspended
NW
length
> 1 μm
Array
uniformity
NW
density
Availability
at EPFL-CMi
VLS-CVD No No, dirty
process
No No No
> 2 μm
limited
by initial
trench
opening
No
Random
growth
Yes
Medium
No
Si/Ge
epitaxy
Yes Yes Yes Yes
Maximum
thickness
limited by
Si/Ge
lattice
mismatch
Not clear
< 500 nm,
depends
on NW
thickness
Yes
Well
controlled
No
Ultra-
high
No
BOSH +
thermal
oxidation
Yes Yes Yes Yes
Can be
controlled
by careful
design
Yes
< 10 μm,
depends
on NW
thickness
Yes
Well
controlled
Yes
Medium
to ultra-
high
Yes
12
Fabrication Approaches Compared
Fabrication

13. E. Buitrago
o BOSCH Process  Scallop formation
o C4F8 passivation step (side wall protection), 1s
o O2 polymer removal (bottom trench/scallop), 1s
o SF6 isotropic etch (scallop formation), 2s
(process temperature 0 °C)
o Thermal oxidation NW formation
o BHF oxide removal NW release
o H2O, air dried.
Fabrication
13
Optimization of Short-Loop SiNW
Fabrication Process

14. E. Buitrago
After BHFAfter oxidationAfter BOSCH
Fabrication
14
Optimization of Short-Loop SiNW Fabrication Process
Any process non-uniformity is furthermore highlighted after each step:
Mask patterning  mask etching  BOSCH thermal oxidation  BHF
Trench opening (T) and silicon spacer (S) width combination optimization
After BOSCH After oxidation

15. E. Buitrago
Fabrication
15
Optimization of Short-Loop SiNW Fabrication Process
o Up to 16 NWs vertically stacked
o Vertical NW density: up to 10 NW/μm
o dNW down to 15 – 30 nm
o L = 2 – 5 μm (up to 10 μm dNW > 50 nm )
o BOSCH recipe  NW
diameter variation from
top to bottom of trench
o T  vertical density
o S + T  horizontal NW
density
o S + T + oxidation + BHF
 final NW diameter

16. E. Buitrago
Masking level 0: alignment marks
o Patterning optical and e-beam marks
Masking level 1: SiNW formation
o LTO/ZEP deposition
o e-beam patterning
o Hard mask dry etch patterning
o Scallop formation by BOSCH
o SiNW formation by thermal oxidation
o 1 μm LTO implantation mask deposition
Fabrication
16
Process Flow
6 masking levels, 4 e-beam lithography steps, SOI, p-type, 1-10 Ohm·cm, device layer: 1 μm

17. E. Buitrago
Masking level 2: Implantation
S/D junctions > 1018 cm-3 N+ phosphorous
o Monte-Carlo 2D Simulations
o LTO mask thickness: 1 μm
o Energy: 1e16 cm-2
o Dose: 320 keV
o RTA: 30 secs
o 1 μm Si device layer 7 ‒ 8 NWs stacked
Fabrication
17
Process Flow
6 masking levels, 4 e-beam lithography steps, SOI, p-type, 1-10 Ohm·cm, device layer: 1 μm
Number of NWs that can be stacked in vertical direction limited by
implantation  deeper S/D junctions prohibitively expensive high implant
energies and doses needed.
NW length limited by dopant lateral spread

18. E. Buitrago
Masking level 2: Implantation
o ZEP deposition, e-beam patterning
o Implant mask patterning by dry etch
o Implantation (IBS) + RTA (LAAS)
Masking level 3 + 4: Metallization
o Side gate patterning (e-beam)
o PMMA/MMA dep., e-beam patterning
o Ti+Pt evaporation, lift-off
o S/D metallization (optical-litho)
o LOR/AZ resist dep. and optical litho
o Ti+Al+Pt evaporation, lift-off
o anneal (425 °C, forming gas, 30 mins)
Fabrication
18
Process Flow
6 masking levels, 4 e-beam lithography steps, SOI, p-type, 1-10 Ohm·cm, device layer: 1 μm

19. E. Buitrago
Masking level 5: SU-8 isolation
o SU-8 deposition, optical lithography
30 x 30 μm2 window, expose NWs and SG
Masking level 6: NW release
o ZEP deposition, e-beam patterning
o BHF oxide removal + O2 plasma
o Metal evaporation, ALD dielectric
deposition
3D Integration possible:
o TSV-last, TSV from back of wafer
o SiNWs protected until end of process by
SiO2
Fabrication
19
Process Flow
6 masking levels, 4 e-beam lithography steps, SOI, p-type, 1-10 Ohm·cm, device layer: 1 μm

20. E. Buitrago
Electrical Characterization
20
Dry Characterization After SiNW Release: BG, DG
Ambient, dry conditions (air εr = 1) room temperature, native oxide as gate dielectric (SiO2 εr = 3.9)
o Normal operation of n-type device transitioning from linear to saturation.
o Poor electrostatic control, SG distance ~ 1 μm, BG BOX distance ~ 70 nm.
o Ioff = 1.2 × 10-6 mA/μm, Ion = 0.5 μA/μm, Ion/Ioff > 102.
o SS = dVBG/d(log10Id) ~ 7.5 V/dec and Vth ~ 13.5 V for VDG = 0 V.
o Slight SS improvement in the Id – VBG as the VDG increases.
SS ~ 6.7 V/dec
SS ~ 19 V/dec
Double SG
(VDG)
potential
increases

21. E. Buitrago
Electrical Characterization
21
Wet Characterization After SiNW Release: SG
Ambient, in isopropanol (IPA εr = 18), room temperature, native oxide as gate dielectric (SiO2 εr = 3.9)
o Use of Pt SG with IPA produces repeatable measurements.
o Id ‒ VSG for different devices within same die are comparable.
o SS (130 ± 21 mV/dec), Vth (2.43 ± 0.98 V) variation  non-dedicated FAB.
o Curve shifts to left  positive charge trapping.
o Little hysteresis (< 15 mV) found  small surface and interface (Si/SiO2) defect
induced charge trapping.[1] Hysteresis affects sensor response drift.
1 mm
Bubbles appear at VSG ~ 10 V, IPA and @ ~5 V PBS pH = 7
[1] Ong et al. J. Phys. D: Appl. Phys. 2011, 44, 28530.

22. E. Buitrago
Electrical Characterization
22
Wet Characterization After SiNW Release: SG
o Excellent electrostatic control through liquid:
o SS ~ 100 mV/dec (87 mV/dec in PBS), Ion > 2 mA/μm.
o Vth ~ 2.24 V (1.93 V in PBS), gm = (dId/dVSG) > 10 µS
o Ioff < 2.1 × 106 mA/μm, Ion/Ioff > 106 for Vd < 500 mV
o Ion and gm,max ↑ with # of NWs and ↓ L
Ambient, in isopropanol (IPA εr = 18), room temperature, native oxide as gate dielectric (SiO2 εr = 3.9)

23. E. Buitrago
Electrical Characterization
23
Wet Characterization: Asymmetric Gating VBG ,VSG
Ambient, in isopropanol (IPA εr = 18), room temperature, native oxide as gate dielectric (SiO2 εr = 3.9)
o SS improvement (~ 30%) and Vth shift towards lower values  electrostatic
control enhancement by asymmetric gating through the liquid.
o α’ = (60 mV/dec)/SSmeasured for same tuning gate potential VSG = VBG = 0.5 V.
o Back-gate can more efficiently control NWs:
o Higher back-gate coupling efficiency: αBG’ = 0.8 vs. αSG’ = 0.6
o Lower Vth when back-gated (Vth = 1.6 V vs. 2.24 V when side/back-gating alone)
Vth =1.6 V
 1.1 V
Vth = 2.24 V
 0.113 V

24. E. Buitrago
Electrical Characterization
24
Wet Characterization: Symmetric Gating
Ambient, in Isopropanol (IPA εr = 18), room temperature, native oxide as gate dielectric (SiO2 εr = 3.9)
o The Vth is reduced but vs. asymmetric front-back gating SS does not change
(~ 5%) significantly.
o Higher back-gate efficiency  Extra BOX layer capacitance when back-gated
in comparison to front-gate configuration:
o solution gate capacitance + native oxide capacitance + BOX layer capacitance
o Low leakage current through SG < 50 nA, VSG < 3 V
SS = 147 mV/dec
 138 mV/dec
SS = 147 mV/dec
 142 mV/dec
Vth = 2.08 V
Vth = 1.82 V
Vth = 2.08 V
Vth = 1.8 V

25. E. Buitrago
Electrical Characterization
25
Wet Characterization After High-κ ALD Dielectric
Ambient, in isopropanol (IPA εr = 18) native ox + t = 10 nm HfO2 (εr = 25) or Al2O3 εr = 15
o Degraded transistor performance for both HfO2 and Al2O3  SS and Vth ↑, Ion ↓.
o Direct deposition of dielectric on native oxide increased amount of dangling
bonds and charge trapping density at interphase.[1]
o Can be improved by thermal anneal in N2 atmosphere or higher quality oxide by
thermal oxidation,[1] not possible here (SU-8, Td ~ 380 °C).
HfO2 Al2O3
SiO2
SiO2
[1] Zhu et al. IEEE Electr. Device Lett. 2002, 23, 59.

26. E. Buitrago
Description Dimensions
Transistor
performance
Remarks Ref.
SiNW array
W = 50 nm
L = 10 μm
in PBS
Ion/Ioff = 105
SS = 100 mV/dec
Pseudo Ag/AgCl
electrode,
Kim et al. Analyst.
2011, 136, 5012.
FinFET array
W = 15 nm
H= 85 nm
L = 10 μm
in PBS
Ion/Ioff = 107
SS = 80 mV/dec
Pseudo Pt+Ag/AgCl local
electrode used
Rim et al. RSC
Advances. 2003, 3,
7963.
SiNW array
W = 100 nm – 1
μm
H = 55 nm
L = 3 μm
in PBS
SS = 85mV/dec
No or little hysteresis
observed,
RE used
Vu et al. Physica Status
Solidi (a). 2009, 426.
SiNW array
nano-gratings
W = 50 nm
H = 30 nm
L = 20 μm
in PBS
Ion/Ioff = 106
SS = 80 mV/dec
down to 65 mV/dec
Low device-to-device
variation due to high NW
density,
RE used
Regonda
et al. Biosens.
Bioelectron. 2013, 245.
SiNW 3D Array
dNW = 15-30 nm
L = 2 – 4 μm
Ion/Ioff > 106
SS ~ 100 mV/dec in IPA
 down to 75 mV/dec
(when asymmetrically
gated)
SS ~ 87 mV/dec in PBS
Pt gate used
little hysteresis
< 15 mV
This work Buitrago
et al.
26
Sensing Experiments
State-of-Art Liquid Gated Transistor Performaces:

27. E. Buitrago
Aminosilanization:
o Surface treated in piranha to leave
hydroxyl-terminated (-OH) surfaces.
o Surface with silanol (Si–OH) and
amino groups can be protonated and
deprotonated for pH sensing,
APTES linker.
Biotinylation:
o Aminosilanized surfaces immersed in
biotin solution.
o Rinsed with PBS (phosphate buffered
saline) and DI-H2O and dried under N2.
 Biotin-streptavidin one of strongest
binding interactions known in nature
Sensing Experiments
27
Surface Modification for Sensing
Aminosilanization with APTES for pH sensing, biotinylation for streptavidin sensing
APTES linker

28. E. Buitrago
Sensing Experiments
28
Fluid Delivery and Reference Electrode
Small channel dimensions minimize exposure, small analyte volumes needed for testing
PDMS stamp:
o 150 μm wide microfluidic channels.
o Contact access on sides of chip.
o Access holes (d ~ 400 μm) link to
external tubing & pump.
o Easy fabrication with SU-8 master mold.
o PDMS stamp-chip bond by “stamp and
stick” for strong, non-permanent bond,
no pretreatment.
Reference electrode (RE):
o Ag/AgCl RE integrated into PDMS flow
cell.
o Flow cell: 1 μL chamber at base
electrode.
o z

29. E. Buitrago
Sensing Experiments
29
Sensor Testing Set-up
o Microtech cascade probe station
and semiconductor device
parameter analyzer.
o Solutions delivered using screw
actuated syringe pump.
o Solution delivery rate: 100 μL/min.
o Different streptavidin solutions
(100 μL) injected separately into
main channel solution by use of a
T-junction within continuous PBS
flow.
o Liquid potential set by integrated
Ag/AgCl RE in flow cell.
Device being measured
PDMS
stamp
in
out
RE and
Flow
Cell
T-junction
streptavidin injection
RE and
Flow Cell

30. E. Buitrago
Sensing Experiments
30
pH Sensing, Id ‒ VRef with pH
APTES modified surfaces
o Excellent transistor characteristics:
o Low SS down to 85 mV/dec
 dNW = 15 - 30 nm
o  PBS pH = 7, εr = 80
o High Ion > 1 mA/μm
 Dense array of NWs.
o High Ion/Ioff > 106
 Low doped SOI substrate.
o ΔVth/pH ~ 50 mV/pH:
o Linear Vth/pH shift, no SS degradation
o Typical for APTES due to presence of both
amino and silanol groups with different
acid dissociation constants.[1]
Increasing pH values
[1] Cui et al. Science. 2001, 293, 1289.

31. E. Buitrago
Sensing Experiments
31
APTES modified surfaces
Subthreshold
strong
inversion
pH Sensing, Various Operation Regimes
ΔId/pH
dependent on
operation
regime
o Clear signal steps observed with pH.
o Avg. response time (time to achieve
90% of full response) t 𝑅 < 60 s.
o High quasi-exponential Id response
w/pH in subthreshold (VRef = 1.25 V)
 ΔId/pH ~ 0.70 dec/pH.
o High linear Id response with pH at
higher current levels strong inversion
(VRef = 3 V)  ΔId/pH ~ 12 μA/pH.
o Sensor response repeatable for full
range of operation.
subthreshold
Subthreshold
Moderateinversion
Stronginversion

32. E. Buitrago
Sensing Experiments
32
pH Sensing, increasing # of NWs (within same die)
APTES modified surfaces
o Drain current changes consistently vary with pH, Id levels increase as the
number of NWs increase.
o Sensor response among different devices within the same die is repeatable
for the full range of operation.
Subthreshold
strong
inversion

33. E. Buitrago
Sensing Experiments
33
pH Sensing, Repeatability
o Sensor still functional after 10 days.
o Reproducible measurements.
o High quasi-exponential Id response in subthreshold
(VRef = 1.25 V, Vd = 1 V)  ΔId/pH ~ 0.8 dec/pH
o High linear Id response with pH above threshold
(VRef = 2 V, Vd = 50 mV)  ΔId/pH ~ 5 μA/pH.
Subthreshold
Above
threshold
APTES modified surfaces, 10 days after first measurement, stored in ambient conditions
Subthreshold
Above
threshold

34. E. Buitrago
Sensing Experiments
34
pH Sensing, Robustness
o Sensor remains functional
after drop.
o Repeatable sensor responses
after 1 m drop.
o Non-ideal handling possible:
1. EPFL Fabrication
2. Tyndall surface modification
3. Imperial stamp bonding
4. Tyndall/EPFL sensor testing
Structures dropped 1 m away
from ground.
APTES modified surfaces

35. E. Buitrago
Description Dimensions
pH response
Transistor
performance
Remarks Ref.
SiNWs array
NA (pH = 2 – 9)
ΔId/pH = 100 nA/pH
APTES modified:
ΔVth/pH linear
Cui et al. Science. 2001,
293, 1289-1292.
SiNW array
nano-gratings
W = 50 nm
H = 30 nm
L = 20 μm
(pH = 2 – 9)
ΔId/pH = nA/pH
ΔVth/pH = 50 mV/pH
Ion/Ioff = 106
SS = 80 mV/dec
down to 65 mV/dec
APTES modified:
ΔVth/pH linear
Regonda
et al. Biosensors and
Bioelectronics. 2013, 245.
Single
trapezoidal
SiNWs
W = 50 nm
H = 25 nm
(pH = 6 – 8)
ΔId/pH ~ 0.82 – 1 dec/pH
Surface not
modified: High
operation voltages
used
Stern et al. Nature. 2007,
445, 519.
SiNW 3D
Array
dNW = 15-30 nm
L = 2 – 4 μm
(pH = 4 – 10)
ΔId/pH > μA/pH
ΔId/pH up to 0.8 dec/pH
ΔVth/pH = 50 mV/pH
Ion/Ioff > 106
SS ~ down to 85 mV/dec
APTES modified:
ΔVth/pH linear
Wide range of
operation pH =4-10.
This work Buitrago et al.
35
Sensing Experiments
SiNWs, State-of-Art pH Sensing

36. E. Buitrago
Sensing Experiments
36
Streptavidin Sensing
Biotinylated surfaces, 100 μL/min, 100 μL streptavidin solution injected within continuous PBS
stream, VRef = 1.5 V
~500 nA
streptavidin
injection
PBS
o Attomolar (~ 17 aM) streptavidin concentration measured.
o Id drops and threshold voltage increases consistently with
the streptavidin binding to the device (streptavidin protein
negatively charged at pH = 7.4).[1]
o As the streptavidin concentration increases consecutively
by a factor of 30 the drain current Id consistently decreases.
[1] Duan et al. Nat. Nano. 2012, 7, 401-407

37. E. Buitrago
Sensing Experiments
37
Protein Sensing, State-of-the-Art
Description
Substrate
fabrication
Dimensions
Concentration
Limits
Ref.
Single
trapezoidal SiNWs
SOI
Top down
W = 50 nm
H = 25 nm
Down to 10 fM
streptavidin
Stern et al. Nature. 2007, 445,
519-522
SiNWs
Array
Bulk Si
Bottom up
NA 10 pM
streptavidin
Cui et al. Science. 2001, 293,
1289-1292.
Si
nano-ribbon
SOI
Top down
W = 45-100 nm
H = 50 nm
L = 1.2 μm
10 fM
streptavidin
Elfstrom et al. Nano Lett. 2008, 8,
945-949.
Random SiNWs
Bulk Si
Bottom up
NA 15 fM biotin
Li et al., Biosens. Bioelectron.
2013, 45, 252-259.
Single SiNW
SOI
Top down
W = 1 μm
H = 45 nm
L = 10 μm
200 fM
streptavidin
Duan et al. Nat. Nano. 2012, 7,
401-407.
SiNW + electrodes for
electro-kinetic pre-
concentration
NA NA
aM cancer
protein PSA
Gong. Small. 2010, 6, 967-973.
SiNW 3D Array
SOI
Top down
dNW = 15-30 nm
L = 2 - 4 μm
Down to 17
aM
streptavidin
This work Buitrago et al.

38. E. Buitrago
Sensing Experiments
38
Vertially Stacked SiNWs on Bulk Si
Low cost alternative to SOI-based sensor with potential
o Low subthreshold slopes SS ~ 160 mV/dec.
o High Ion/Ioff > 3x104
o Parasitic FET (equivalent structure with
destroyed NWs) does not dominate
transistor characteristics.
o Ioff still dominated by leakage current
passing through the parasitic MOSFET.
o Stack more NWs than implantation can
reach. NWs themselves would act as
resistive paths for electron conduction.

39. E. Buitrago
Sensing Experiments
39
SiNWs on Bulk Si, State-of-Art Liquid Gated,
Top-Down Fabrication Approach
Description Dimensions
Transistor
performance
Remarks Ref.
Fin Array
H = 65 – 120
nm
W = 18 – 40 nm
L = 8 – 12 μm
SS ~ 300 mV/dec
Ion/Ioff ~ 104
Ioff ~ 0.1 nA
-Local SOI by “Spacers
Technology”
Rigante et al. ULIS,
Coventry, 2013, 73-76
Single SiNW NA
SS ~ 400 mV/dec
Ion/Ioff ~ 104
Ioff ~ pA
-Channel-stop implantation
to suppress leakage current
-Shallow trench isolation
oxide
Ahn et al. IEEE Trans.
Electron. Devices. 2012,
59, 2243-2249
Polysilicon
NW
W = 40 nm
L = 10 μm
SS = 450 mV/dec
Ion/Ioff > 105
Ioff ~ pA
-thin film process, SiN and
SiO2 isolation layers
Chen et al. Jpn. J. Appl.
Phys. 2011, 50.
Vertically
stacked
SiNWs
dNW = 15 – 30
nm
L = 10 μm
SS = 160 mV/dec
Ion/Ioff > 3 × 104
Ioff ~ 20 nA
-No particular isolation
strategy
This work, Buitrago et al.
No active isolation strategy to suppress leakage current or
isolate of SiNWs/Fins from the bulk

40. E. Buitrago
o Successfully fabricated 3D vertically stacked SiNW FET for
biosensing applications.
o High density array (up to 8 x 20) with ultra-small SiNW
diameters (down to dNW ~ 15 ‒ 30 nm), long (up to L = 5 μm)
robust structures with TSV compatible process.
o Devices have excellent transistor characteristics when liquid
gated.
o High pH sensing responses up to 0.8 dec/pH subthreshold and
> μA/pH in strong inversion.
o Attomolar streptavidin concentrations measured.
o Bulk vertically stacked FET efficiently demonstrated.
Conclusions and Perspectives
40
Conclusions

41. E. Buitrago
o EPFL: A. M. Ionescu, M. Fernandez-Bolaños,
N. Berthaut, X. Van Kooten.
TNI: O. Lotty, R. Yu, J. D. Holmes, Y. Georgiev,
G. Fagas
Imperial College: A. M. Nightingale
o Semiconducting Nanowire Platform for
Autonomous Sensors SiNAPS FP7 European
Project.
o FP7 Integrated project e-BRAINS European
Project.
o Fabrication Center of Micro and
Nanotechnology (CMi) at EPFL.
Acknowledgments
41
IC Device 1 (Technology 1)
MetallisationSystem 1
IC Device 2 (Technology 2) with TSV
MetallisationSystem 2
IC Device 2 (Technology 2) with TSV
MetallisationSystem 2Metallisation
MEMS/NEMS Device
possibly with TSV
Cap -Chip (Wafer)
MEMS/NEMS Device
possibly with TSV
Cap -Chip (Wafer)
MEMS/NEMS Device
possibly with TSV
Cap -Chip (Wafer)
e-BRAINS
People, Funding and Fabrication Facilities

42. E. Buitrago
Thank you for your
attention
Questions?

43. E. Buitrago
o Anisotropic etch Vertical wall
definition
o C4F8 passivation step (side wall protection)
o Anisotropic vertical etch (SF6/C4F8 mixed flow)
o O2 polymer removal (bottom trench/scallop)
o SF6 isotropic etch (scallop formation)
o Thermal oxidation  Fin formation
o BHF oxide removal  Fin release
o H2O, IPA rinse, N2 dry
Fabrication
43
Optimization of Short-Loop Fin
Fabrication Process

44. E. Buitrago 44
Fin Structuration
Back-up Slides: Fin Structuration
First Generation:
Vertical walls: BOSCH
Fin Separation: Passivation C4F8
+ isotropic SF6
Second Generation
Vertical walls: anisotropic
C4F8/ SF6 mixed flow
Fin Separation: Passivation C4F8
+ isotropic SF6
Third Generation
Vertical walls: anisotropic
C4F8/ SF6 mixed flow
Fin Separation: Passivation C4F8+ O2 plasma +
isotropic SF6
o High process variability: e-beam, dry etch
o Thin fins possible 20 x 200 nm
o Scallop shape limits height length to 200 nm
o Achieving fin to fin vertical uniformity is a challenge
Need sharp round
scallop to
reduce droplet
shape

45. E. Buitrago
Back-up Slides: Vertically Stacked
45
Vertically Stacked SiNWs
Fabrication approach: BOSCH + thermal oxidation
Doherty et al., ISCAS, 2003, 934. (Berkeley, USA)
As sacrificial molds for nanofluidic channels
For biospecimen sorting and
filtering by varying vertical wire
separation along a channel

46. E. Buitrago 46
Ferain et al., Nature. 2011, 479.
Types of Multigate MOSFETs
Back-up Slides: Multigate
SOI-FinFET
Gate control
From lateral sides
SOI-tri-gated SiNW
gate control from 3
sides
SOI Π-gate
gate control improved
electric field from sides
exerts control on bottom too
SOI Ω-gate
gate control improved
electric field from sides
exerts control on bottom
too
SOI-GAA
Gate control from 4
sides ultimate
arquitecture
Bulk tri-gate