In wireless communications and data acquisition systems, there is more to consider when designing and implementing a complete solution beyond simply physically connecting a high speed analog module to an FPGA platform. Available hardware description language (HDL) components and software are critical to establish an interface, which is necessary for practical system integration. This session starts with a top-level overview of various physical interfaces that are typically used and provides an in-depth focus on high speed serial JESD204B. Prototype HDL used for these types of boards is covered, along with the specific board components and how they are used to interface to high speed ADCs and DACs. Linux device drivers for the HDL components as well as for the ADI components are presented. This includes a short introduction into the Industrial I/O (IIO) framework, the benefits it offers, and how it can be used in end designs.
MIPI DevCon 2016: Troubleshooting MIPI M-PHY Link and Protocol IssuesMIPI Alliance
The M-PHY specification is designed to allow mobile devices to have a low power, high performance interface. Several higher level protocols use the M-PHY physical layer for storage, I/O and memory in mobile devices. In this presentation, Gordon Getty of Teledyne LeCroy discusses how higher layer protocols, including UniPro and UFS, use the M-PHY physical layer to provide an efficient, low power storage protocol to be enabled on mobile platforms. It also covers debug and analysis techniques for UFS and UniPro technologies to allow root-cause analysis to be performed in an efficient and effective manner.
Demystifying the JESD204B High-speed Data Converter-to-FPGA interfaceAnalog Devices, Inc.
Learn all about the JESD204 standard. This presentation provides an overview of the JESD204 serial interface standard from its origin up to the current "B" revision. Common "high-performance metrics" that are associated with high speed serial interfaces are also discussed. by Analog Devices, Inc.
MIPI DevCon 2016: Troubleshooting MIPI M-PHY Link and Protocol IssuesMIPI Alliance
The M-PHY specification is designed to allow mobile devices to have a low power, high performance interface. Several higher level protocols use the M-PHY physical layer for storage, I/O and memory in mobile devices. In this presentation, Gordon Getty of Teledyne LeCroy discusses how higher layer protocols, including UniPro and UFS, use the M-PHY physical layer to provide an efficient, low power storage protocol to be enabled on mobile platforms. It also covers debug and analysis techniques for UFS and UniPro technologies to allow root-cause analysis to be performed in an efficient and effective manner.
Demystifying the JESD204B High-speed Data Converter-to-FPGA interfaceAnalog Devices, Inc.
Learn all about the JESD204 standard. This presentation provides an overview of the JESD204 serial interface standard from its origin up to the current "B" revision. Common "high-performance metrics" that are associated with high speed serial interfaces are also discussed. by Analog Devices, Inc.
Final Presentation of TEEP (Taiwan Experience Education Program)@AsiaPlus 2019 at Broadband Multimedia and Wireless Research Laboratory, National Taiwan University of Science and Technology.
This presentation contains explanation about 5G FAPI specification in concept.
Presented by James Goel, MIPI Technical Steering Group chair, and Rick Wietfeldt, Security Working Group co-chair
This session brings you up to speed on all the latest developments within MIPI Automotive SerDes Solutions (MASS) – a framework that provides a full-stack, end-to-end sensor/display-to-ECU solution for autonomous driving and ADAS systems that leverage existing MIPI CSI-2®, DSI-2℠ and VESA eDP/DP protocols running over MIPI A-PHY℠. The presentation also explains how recent developments make it easier for you to integrate MIPI A-PHY into your next automotive E/E architecture and how, through A-PHY's adoption as an IEEE standard, it can be accessed for evaluation without MIPI membership.
In addition, the presenters discuss how recently released MIPI Camera and Display Service Extensions (CSE and DSE) and their associated protocol adaptation layers (PALs) work together to embed functional safety and security enablers natively at the "edge" – ultimately within the sensor, display and ECU components themselves.
In wireless communications and data acquisition systems, there is more to consider when designing and implementing a complete solution beyond simply physically connecting a high speed analog module to an FPGA platform. Available hardware description language (HDL) components and software are critical to establishing an interface, which is necessary for practical system integration. This session starts with a top-level overview of various physical interfaces that are typically used and provides an in-depth focus on high speed serial JESD204B. Prototype HDL used for these types of boards is covered, along with the specific board components and how they are used to interface to high speed ADCs and DACs. Linux device drivers for the HDL components, as well as for the ADI components, are presented. This includes a short introduction into the Industrial I/O (IIO) framework, the benefits it offers, and how it can be used in end designs.
This is an overview of the Analog Devices’ JESD204 Interface Framework, a system-level software package targeted at simplifying development by providing a performance optimized IP framework.
Final Presentation of TEEP (Taiwan Experience Education Program)@AsiaPlus 2019 at Broadband Multimedia and Wireless Research Laboratory, National Taiwan University of Science and Technology.
This presentation contains explanation about 5G FAPI specification in concept.
Presented by James Goel, MIPI Technical Steering Group chair, and Rick Wietfeldt, Security Working Group co-chair
This session brings you up to speed on all the latest developments within MIPI Automotive SerDes Solutions (MASS) – a framework that provides a full-stack, end-to-end sensor/display-to-ECU solution for autonomous driving and ADAS systems that leverage existing MIPI CSI-2®, DSI-2℠ and VESA eDP/DP protocols running over MIPI A-PHY℠. The presentation also explains how recent developments make it easier for you to integrate MIPI A-PHY into your next automotive E/E architecture and how, through A-PHY's adoption as an IEEE standard, it can be accessed for evaluation without MIPI membership.
In addition, the presenters discuss how recently released MIPI Camera and Display Service Extensions (CSE and DSE) and their associated protocol adaptation layers (PALs) work together to embed functional safety and security enablers natively at the "edge" – ultimately within the sensor, display and ECU components themselves.
In wireless communications and data acquisition systems, there is more to consider when designing and implementing a complete solution beyond simply physically connecting a high speed analog module to an FPGA platform. Available hardware description language (HDL) components and software are critical to establishing an interface, which is necessary for practical system integration. This session starts with a top-level overview of various physical interfaces that are typically used and provides an in-depth focus on high speed serial JESD204B. Prototype HDL used for these types of boards is covered, along with the specific board components and how they are used to interface to high speed ADCs and DACs. Linux device drivers for the HDL components, as well as for the ADI components, are presented. This includes a short introduction into the Industrial I/O (IIO) framework, the benefits it offers, and how it can be used in end designs.
This is an overview of the Analog Devices’ JESD204 Interface Framework, a system-level software package targeted at simplifying development by providing a performance optimized IP framework.
The industrial control market involves the monitoring and control aspects of both complex and simple processes. Common trends within the industry, notably the drive for increased efficiencies, better robustness, higher channel densities, and faster monitoring and control speeds, subsequently drive new technology advancements for semiconductor manufacturers. This session aims to give a broad overview into the system requirements for both field instruments (sensors/actuators) and control room (analog input/output) modules, and demonstrates a typical I/O module configuration with HART (highway addressable remote transducer) connectivity.
This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, direct conversion radio architecture, the high speed data converter interface, and FPGA-based digital signal processing for software-defined radio. Demonstrations use the latest generation Analog Devices’ high speed data converters, RF, and clocking devices, along with the Xilinx Zynq-7000 SoC. Other topics of discussion include the imperfections introduced by the modulator/ demodulator with particular focus on the effect of temperature and frequency changes. In-factory and in-field algorithms that reduce the effect of these imperfections, with particular emphasis on the efficacy of in-factory set-and-forget algorithms, are examined.
This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, direct conversion radio architecture, the high speed data converter interface, and FPGA-based digital signal processing for software-defined radio. The demo board uses the latest generation of Analog Devices’ high speed data converters, RF, and clocking devices, along with the Xilinx Zynq-7000 SoC. Other topics of discussion include the imperfections introduced by the modulator/demodulator with particular focus on the effect of temperature and frequency changes. In-factory and in-field algorithms that reduce the effect of these imperfections, with particular emphasis on the efficacy of in-factory set-and-forget algorithms, are examined.
Acquired analog signals can be manipulated and processed by either the analog or digital portions of a system, for example, through filtering, multiplexing, and gain control. The analog portions of a system can typically provide reasonably simple processing at fairly low cost, power, and overhead. Digital processing can provide far greater analysis power and can alter the nature of the analysis without changing hardware. Sampling theory, however, must be taken into account. This session covers the signal chain basics from signal to sensor to amplifier to converter to digital processor and back out again.
Partitioning Data Acquisition Systems (Design Conference 2013)Analog Devices, Inc.
Acquired analog signals can be manipulated and processed by either the analog or digital portions of a system, for example, through filtering, multiplexing, and gain control. The analog portions of a system can typically provide reasonably simple processing at fairly low cost, power, and overhead. Digital processing can provide far greater analysis power and can alter the nature of the analysis without changing hardware. Sampling theory, however, must be taken into account. This session covers the signal chain basics from signal to sensor to amplifier to converter to digital processor and back out again.
Introducing Application Engineered Routing Powered by Segment RoutingCisco Service Provider
Application-Engineered Routing
Application programs the Segment Routing network to deliver end-to-end per-flow policy from DC through WAN to end-user
Adding value at your own pace
– Leveraging the existing MPLS dataplane without any change. SW upgrade only.
– Simplification, Automated 50msec FRR, per-domain and then end-to-end policies
Economic gains
– Improved service richness and velocity
– Optimized CAPEX and OPEX thanks to the simplicity of the SR architecture
Segment Routing deployments in CY15 in all the markets – WEB, SP, Entreprise
Strong partnership with lead operator group Commitment to standardization and multi-vendor support

The industrial control market involves the monitoring and control aspects of both complex and simple processes. Common trends within the industry, notably the drive for increased efficiencies, better robustness, higher channel densities, and faster monitoring and control speeds, subsequently drive new technology advancements for semiconductor manufacturers. This session aims to give a broad overview of the system requirements for both field instruments (sensors/actuators) and control room (analog input/output) modules, and demonstrates a typical I/O module configuration with HART® (highway addressable remote transducer) connectivity.
Data conversion for data acquisition is a two-part process that involves sampling and then converting signals into digital venues. These processes inherently remove part of the complete analog signal in exchange for the power and robustness of digital signal handling. This becomes especially difficult when trying to capture signals at the limits of the resolution and speed of our systems. In this session, learn how to design a data conversion system that minimizes the signal loss to match the signal handling requirements … even on the hard ones.
Spectra IP Core ORB - high-performance, low-latency solution for FPGA-GPP com...ADLINK Technology IoT
Various approaches have been developed for integrating FPGA and GPP application components in a Software Communications Architecture (SCA) radio. Most of these have been less than successful, primarily due to overhead, latency and/or maintainability issues. Spectra IP Core is a second-generation solution to FPGA-GPP component integration that provides a low-latency, standards-based CORBA protocol with excellent performance metrics and the robustness of a proven, deployed solution. Building on PrismTech’s ICO v1, Spectra IP Core is a second-generation COTS product. This webcast will introduce the Spectra IP Core architecture, its main functions and its performance benchmarks. Although FPGA ‘middleware’ is a new concept for many FPGA developers, the capabilities provided by Spectra IP Core not only provide valuable integration ‘hooks’, but also help support a highly-efficient, proven radio component that simplifies the integration of high-level software development with digital design and accelerates the development of SCA-compliant FPGA components for SCA radios. These slides will be of great interest and value to project managers, systems engineers and architects as well as software and digital engineers involved in designing, building and testing SCA-compliant SDRs.
An Introduction to ADI’s Power components used in RF signal chains, with special treatment of high performance data converters, transceivers and PLL/VCOs.
An Introduction to ADI’s RF Switches and RF Attenuators including their key characteristics and how and where they should be used in the RF signal chain.
Digital isolation plays a key role in designing industrial motor control systems. This presentation takes you through why, where and how for isolation designs that optimize system performance while meeting the ever stringent safety and efficient standards. Analog Devices, Nicola O'Byrne at PCIM 2015
Isolation in gate drive is one critical area for designing efficient, safe and highly productive motor control systems. Learn how the latest ADI isolated gate drives can help you solve the design challenges. Analog Devices, Dara O'Sullivan PCIM 2015
When it comes to high performance signal chains, you need high performance power solutions. Noise sensitive
circuits such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and phase
lock loops (PLLs)—as well as FPGAs—demand low noise power supplies that require specialized design
techniques. Engineers spend hours trying to figure out how to power these circuits without adding noise.
This presentation will focus on understanding various methods for not only approaching but meeting system
requirements. The session will introduce tested solutions and layout considerations that must be taken into
account when designing with switching regulators and low drop out (LDO) regulators.
This session provides insight into the operation of electric motor drive systems. Topics include electric motor operation and construction, motor control strategies, feedback sensors and circuits, power and isolation, and challenges of designing highly efficient motor control systems. A new high performance servo control FMC board will be introduced in the presentation, which provides an efficient motor control solution for different types of electric motors, addresses power and isolation challenges, and provides accurate measurement of motor feedback signals and increased control flexibility due to FPGA interfacing capabilities. The motor control hardware platform will be used to demonstrate rapid prototyping of motor control algorithms using Xilinx base platforms and the MathWorks development and simulation tools.
Finding the right combination of parts to create a signal chain can be a complex and daunting task, due to time demands, unfamiliarity with various technology areas, and the enormous amount of unproven solutions scattered across the Web. Signal Chain Designer is an intelligent selection and design tool that accesses verified product combinations and applications circuits, which can be customized or newly created according to user specifications. The Signal Chain Designer experience is supported by direct access to online EE design tools, evaluation hardware, software, documentation, and ADI Circuits from the Lab® reference circuits.
Sensors are the eyes, ears, and hands of electronic systems and allow them to capture the state of the environment. The capture and processing of sensor inputs is a delicate process that requires understanding of the signal details. Integration of sensor functions onto silicon has brought about improved performance, better signal handling, and lower total system cost. MEMS (microelectromechanical systems) sensors have opened up entire new areas and applications. In this session, the fundamental MEMS sensor concept of moving fingers that form a variable capacitor is covered, along with how it is turned into a usable motion signal. Adaptations for multiaccess sensing, rotational sensing, and even sound sensing, along with concepts of how these devices are tested and calibrated, are covered.
Instrumentation: Test and Measurement Methods and Solutions - VE2013Analog Devices, Inc.
Tilt Measurement: Tilt measurement is fast becoming a fundamental analysis tool in many fields including automotive, industrial, and healthcare. Navigation, vehicle dynamic control, building sway indication, and motion detection systems all rely on this simple, cheap, and precise way of angle monitoring. MEMS accelerometers are better suited to inclination measurement than other methodologies. This session will address the challenges encountered when designing a dual-axis tilt sensor using a MEMS accelerometer including measurement resolution, signal conditioning, single- vs. dual-axis, angle computation, and calibration.
Impedance Measurement: The measurement of complex impedance is widely used across industrial, commercial, automotive, healthcare, and consumer markets, and can include applications such as proximity sensing, inductive transducers, metallurgy and corrosion detection, loudspeaker impedance, biomedical, virus detection, blood coagulation factor, and network impedance analysis. This session will cover the concepts, approaches, and challenges of performing complex impedance measurements and will present a system-level solution for impedance conversion.
Weigh Scale Measurement: Most common industrial weigh scale applications use a bridge-type load-cell sensor, with a voltage output that is directly proportional to the load weight placed on it. This session examines the basic parameters of a bridge-type load-cell sensor, such as the number of varying elements, impedance, excitation, sensitivity (mV/V), errors, and drift. It will also discuss the various components of the signal conditioning chain and present solutions with high dynamic range.
Liquid Sensing: Visible light absorption spectroscopy and colorimetry are two fundamental tools used in chemical analysis. Most of these light-based systems use photodiodes as the light sensor, and require similar high input impedance signal chains. This session examines the different components of a photodiode amplifier signal chain, including a programmable gain transimpedance amplifier, a hardware lock-in amplifier, and a Σ-Δ ADC that can measure a sample and reference channel to greatly reduce any measurement error due to variations in intensity of the light source.
Gas Sensing: Many industrial processes involve toxic compounds, and it is important to know when dangerous concentrations exist. Electrochemical sensors offer several advantages for instruments that detect or measure the concentration of toxic gases. This session will describe a portable toxic gas detector using an electrochemical sensor. The system presented here includes a potentiostat circuit to drive the sensor, as well as a transimpedance amplifier to take the very small output current from the sensor and translate it to a voltage that can take advantage of the full-scale input of an ADC.
At very high frequencies, every trace and pin is an RF emitter and receiver. If careful design practices are not followed, the unwanted signals can easily mask those a designer is trying to handle. The design choices begin at the architecture level and extend down to submillimeter placement of traces. There are tried and proven techniques for managing this process. The practical issues of real system design are covered in this session, along with ways to minimize signal degradation in the RF environment.
Frequency Synthesis and Clock Generation for High Speed Systems - VE2013Analog Devices, Inc.
Frequency synthesis and clock generation are now key elements in all aspects of high speed data acquisition and RF design. In this session, the primary types of frequency synthesizers—phase-locked loops (PLL) and direct digital synthesizers (DDS)—are discussed, along with the applications for when each is appropriate. Also covered are detailed aspects of synthesizer design. Other applications, such as clock distribution and translation are addressed, and problems associated with poor clocking are identified. Examples of poor clocking are shown, along with the results of doing it properly.
Amplifiers are the workhorses of data acquisition and transmission systems. They capture and amplify the low level signals from sensors and transmitters, and can pull these signals from high noise and high common-mode voltage levels. Amplifiers can also change the signal range and switch from single-ended to differential (or the reverse) to match exactly the input range of an ADC. This session covers the versatility and power of amplifiers in precision systems.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Let's dive deeper into the world of ODC! Ricardo Alves (OutSystems) will join us to tell all about the new Data Fabric. After that, Sezen de Bruijn (OutSystems) will get into the details on how to best design a sturdy architecture within ODC.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Slack (or Teams) Automation for Bonterra Impact Management (fka Social Soluti...Jeffrey Haguewood
Sidekick Solutions uses Bonterra Impact Management (fka Social Solutions Apricot) and automation solutions to integrate data for business workflows.
We believe integration and automation are essential to user experience and the promise of efficient work through technology. Automation is the critical ingredient to realizing that full vision. We develop integration products and services for Bonterra Case Management software to support the deployment of automations for a variety of use cases.
This video focuses on the notifications, alerts, and approval requests using Slack for Bonterra Impact Management. The solutions covered in this webinar can also be deployed for Microsoft Teams.
Interested in deploying notification automations for Bonterra Impact Management? Contact us at sales@sidekicksolutionsllc.com to discuss next steps.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
"Impact of front-end architecture on development cost", Viktor TurskyiFwdays
I have heard many times that architecture is not important for the front-end. Also, many times I have seen how developers implement features on the front-end just following the standard rules for a framework and think that this is enough to successfully launch the project, and then the project fails. How to prevent this and what approach to choose? I have launched dozens of complex projects and during the talk we will analyze which approaches have worked for me and which have not.
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
3. Today’s Agenda
High speed converter interface styles and standards
A closer look at the JESD204B converter-to-FPGA serial interface
FPGA converter systems design support offerings
Evaluation and reference design boards
Software and device drivers
HDL interface blocks
Online technical support and documentation
3
4. Microcontrollers to FPGAs to ASICs: Trade-Offs
Microcontroller DSP FPGA ASIC
4
Development Cost
Potential I/O Performance
Ease of Development
BOM Cost
Potential Signal Processing and Converter Performance
5. ADC Output Configurations
Parallel CMOS
Fdata max = 150 MSPS
DDR LVDS
Fdata max = 420 MSPS
Interface available in lower
cost FPGAs
Pins = ADC resolution plus
DCO
High pin count
5
ADC ADC ADC
N
PLL PLL
Fdata
Fdata
Fdata
Fs Fs Fs
FCLK
DCO
DCO
Fdata max = 1 + Gbps
Serial LVDS
Fs max = Fdata × # of data
lanes/ADC resolution
On-chip PLL required
Medium to low-end FPGA
typically required
Pins = # of data lanes plus
Frame CLK and Data CLK
Fdata = 6.25+ Gbps
Encoded serial CML
Fs max = data packet
length + overhead
On-chip PLL required
GT(x) ports on FPGA
required
Aria, Kintex platforms, in
addition to high end Virtex
and Stratix
Two pins/lane, number of
lanes depends on channels,
speed, resolution
PARALLEL SERIAL LVDS SerDes/JESD204
6. Interface Styles and Standards:
Control vs. Data
High speed converters almost always have a separate control
interface from the data interface
Often SPI
Occasionally I2C or pin-programmable
Used to access register map of converter
Runs much slower than data interface
SPI often runs at <40 MHz (5 Mbps)
Lower speed/precision converters may combine data and control
Over SPI or I2C
Or, they may not have a control interface at all
Pin-programmable
No options
6
Often requires dedicated software device drivers to set up and control the converter
7. 7
Why the Need for a High Speed
Converter-to-FPGA Serial Interface?
Today’s solution Solution with
JESD204A/JESD204B
serial interface
FPGA
34 WIRES
18 WIRES
Tight timing
requirements
Large number of I/Os
TO
ANTENNA 1
34 WIRES
18 WIRES
TO
ANTENNA 2
FPGA
TO
ANTENNA 1
TO
ANTENNA 2
Relaxed
timing requirements
with sync control
Minimum number of I/Os
8
SERIAL PAIRS
1 to 2
SERIAL PAIRS
1 to 2
SERIAL PAIRS
14B ADC
250 MSPS
DUAL 16B DACDUAL
16B DAC
1.2 GSPS
14B ADC
250 MSPS
DUAL 16B DACDUAL
16B DAC
1.2 GSPS
14B ADC
250 MSPS
14B ADC
250 MSPS
QUAD
16B DAC
2 GSPS
8. Why the Need for a High Speed
Converter-to-FPGA Serial Interface?
Simplification of overall system design
Smaller/lower number of trace routes, easier to
route board designs
Easier synchronization
Reduction in pin count – both the Tx and Rx side
Move from high pin count low speed parallel interfaces
to low pin count high speed serial interfaces
Embedded clock incorporated to even further reduce pin count
Reduction in system costs
Smaller IC packages and board designs lead to lower cost
Easily scalable to meet future bandwidth requirements
As geometries shrink and speed increases, the standard adapts
8
9. What is JESD204?
JESD204, a JEDEC defined standard for
high speed, point to point, serial interface,
used to interconnect two (or more) devices.
ADC to digital receiver.
Digital source to DAC.
Digital source to digital receiver.
How is it different than previous data converter interfaces?
A single primary serial interface can be used to pass all data, clocking, and
framing information.
The clock and frame information are embedded in the data stream.
No need to worry about set up and hold time between data and clock.
One PCB trace (differential) can route all bits.
9
FPGA
DAC
DAC
ADC
ADC
Clock
10. What is the JEDEC Standard 204 (JESD204)?
JESD204 is a standard defining a multigigabit serial data link
between converters and a receiver (commonly FPGA or ASIC)
JESD204 (April 2006) – original standard defining one lane, one link
Defined transmission of samples across a single serial lane for multiple
converters at speeds up to 3.125 Gbps
10
11. What is the JEDEC Standard 204 (JESD204A)?
JESD204A (April 2008) – first revision expanding standard
to multiple links and multiple lanes
Revision adds capability for multiple aligned serial lanes for
multiple converters at speeds up to 3.125 Gbps
11
12. What is the JEDEC Standard 204 (JESD204B)?
JESD204B (August 2011) – third version utilizes a device clock
and adds measures to ensure deterministic latency
Supports multiple aligned serial lanes for multiple converters at speeds
up to 12.5 Gbps
12
Multiple
Converters
Up to
12.5 Gbps
Multiple
Lanes
13. Key Aspects of JESD204x Standards
8b/10b Embedded Clock
DC balanced encoding which
guarantees significant transition
frequency for use with clock and
data recovery (CDR) designs
Encoding allows both data and
control characters – control characters
can be used to specify link alignment, maintenance, monitoring, etc.
Detection of single bit error events on the link
Serial Lane Alignment
Using special training patterns with control characters, lanes can be aligned across
a “link”
Trace-to-trace tolerance may be relaxed, relative to synchronous sampling parallel
LVDS designs
Serial Lane Maintenance/Monitoring
Alignment maintained through super-frame structure and use of specific
“characters” to guarantee alignment
Link quality monitored at receiver on lane by lane basis
Link established and dropped by receiver based on error thresholds
13
14. Key Signals in JESD204A Systems
Frame Clock
A clock signal in the system equal to
the frame rate of the data on the link.
This is the master timing reference.
SYNC~
A system synchronous, active low signal
from the receiver to the transmitter which denotes the state of synchronization.
Synchronous to the frame clock in JESD204A.
When SYNC~ is low, the receiver and transmitter are synchronizing.
SYNC~ and frame clock should have similar compliance in order to ensure
proper capture/transmission timing (i.e., LVDS, CMOS, CML).
SYNC~ signals may be combined if multiple DACs/ADCs are involved.
Lane 0, … , L-1
Differential lanes on the link (typically high speed CML).
8B/10B code groups are transmitted MSB first/LSB last.
14
15. Key Signals in JESD204B Systems
Device Clock
A clock signal in the system which is a
harmonic of the frame rate of the data
on the link. In JESD204B systems, the
frame clock is no longer the master
system reference.
SYNC~
Same as JESD204A except synchronous to local multiframe clocks (LMFC) instead
of the frame clock.
Lane 0, … , L-1
Same as JESD204A.
SYSREF (Optional)
An optional source-synchronous, high slew rate timing resolution signal responsible
for resetting device clock dividers (including LMFC) to ensure deterministic latency.
One shot, “gapped periodic” or periodic.
Distributed to both ADCs/DACs and ASIC/FPGA logic devices in the system.
When available, SYSREF is the master timing reference in JESD204B systems
since it is responsible for resetting the LMFC references.
15
16. Deterministic Latency in JESD204x
Latency can be defined as deterministic when the time from the
input of the JESD204x transmitter to the output of the JESD204x
receiver is consistently the same number of clock cycles
In parallel implementations, deterministic latency is rather simple –
clocks are carried with the data
In serial implementations, multiple clock domains exist, which can
cause nondeterminism
JESD204 and JESD204A do not contain provisions for guaranteeing
deterministic latency
JESD204B looks to address this issue by specifying three device
subclasses:
Device Subclass 0 – no support for deterministic latency
Device Subclass 1 – deterministic latency using SYSREF (above 500 MSPS)
Device Subclass 2 – deterministic latency using SYNC~ (up to 500 MSPS)
16
17. LVDS vs. CML
17
The increased speed of the CML driver leads to a reduction in the
number of drivers by enabling more channels per lane.
With JESD204 providing up to an 80% lane reduction, the power
increase of JESD204 CML is comparable to an LVDS implementation.
LVDS
Max data rate < 3.125 Gbps
Low power consumption
CML
Max data rate ≤ 12.5 Gbps
Higher power consumption
compared to LVDS
18. High Speed Data Connectivity: Summary
High speed converters may only attach to FPGAs/ASICs
High speed converter interfaces
Converters typically feature a control and data path
Data path:
Require interface logic (HDL)
Serial interfaces tend to be more sophisticated and, therefore, require more
know-how and interface logic.
Dedicated control interfaces typically 3-wire, 4-wire SPI
SPI interface → uses standard IP cores
However, often more than 100 registers, with lots of control bits
Complexity is with the software and initialization values
18
DOCS
HW
HELP
HDL
SW
Rapid Development
Integration
19. FPGA Converter Systems
Design Support Offerings
19
Evaluation and
Reference Design
Boards
Software and
Device Drivers
HDL Interface
Blocks
Online Technical
Support and
Documentation
FPGA Design
Support
21. Native FMC Interface Cards
FPGA Mezzanine Card, or
FMC, as defined in VITA 57,
provides a specification
describing an I/O mezzanine
module with connection to
an FPGA or other device with
reconfigurable I/O capability.
Analog Devices converter
products can be found on
many boards, which use
industry standard FMC
connectors.
21
http://wiki.analog.com/resources/alliances/xilinx
22. AD-FMCJESDADC1-EBZ
AD-FMCJESDADC1-EBZ
2× dual, 14-bit, 250 MSPS ADC
(AD9250)
Clock tree (AD9517)
4 channels total
Synchronized sampling across
ADCs
Requires HPC-FMC (4 lanes of
GTX) for full performance
Can work on LPC (1 lane) with
reduced sample rate, and 1×
AD9250
Works with Xilinx® 204B HDL
ADI/Xilinx reference design
ADI drivers available (Linux and
No-OS)
22
AD-FMCJESDADC1-EBZ
23. Using FPGA Evaluation Boards with ADI
Converters
Adapter boards exist to allow customers to use some of our
standard evaluation boards with various FPGA evaluation boards
Customers are encouraged to use our evaluation platforms first, to become
familiar with the parts and their expected performance
Adapter boards provide electrical connections only
Reference designs exist (check wiki.analog.com)
High speed ADCs
Adapter boards for Xilinx (FMC-HPC) evaluation boards are available
SPI is routed through FPGA evaluation board connector
FPGA (firmware) controls SPI
ADI part numbers:
CVT-ADC-FMC-INTPZ
23
25. AD-DAC-FMC-ADP
25
The AD-DAC-FMC-ADP adapter
board allows any of Analog
Devices' DPG2-compatiable high
speed DAC evaluation boards to
be used on a Xilinx evaluation
board with an FMC connector.
The adapter board uses the low
pin count (LPC) version of the
FMC connector, so it can be
used on either LPC or HPC
hosts.
http://wiki.analog.com/resources/alliances/xilinx
26. System Demonstration Platform (SDP)
Interposers
FMC-SDP Interposer
The FMC-SDP interposer
allows any Analog Devices
SDP evaluation board or
Circuits from the Lab®
reference boards to be used
on a Xilinx evaluation board
with an FMC connector.
The interposer uses the low
pin count (LPC) version of the
FMC connector, so it can be
used on either LPC or HPC
hosts. The interposer can only
be used with FPGA boards
that support 3.3VIO for the
FMC connection.
26
27. Precision ADC Pmod Examples
27
PmodAD1—Two 12-bit ADC inputs
Analog Devices AD7476
PmodAD2 —4 channel,
12-bit ADC
Analog Devices AD7991
Sampling rate: 1 MSPS
Resolution: 12-bit
No. of channels: 2
Interface: SPI
ADC type: SAR
Sampling rate: 1 MSPS
Resolution: 12-bit
No. of channels: 4
Interface: I2C
ADC type: SAR
PmodAD4 —1 channel,
16-bit ADC
Analog Devices AD7980
PmodAD5 —4 channel,
24-bit ADC
Analog Devices AD7193
Sampling rate: 1 MSPS
Resolution: 16-bit
No. of channels: 1
Interface: SPI
ADC type: PulSAR®
Sampling rate: 4.8 kSPS
Resolution: 24-bit
No. of channels: 4
Interface: SPI
ADC type: Σ-Δ
29. FPGA Projects
Analog Devices provided HDL reference designs
Native FMC converter cards
FMC interposers—converter evaluation board combinations
Pmods
SDP or Circuits from the Lab® type cards
Each reference design consists of
Complete FPGA design project
Including HDL and Verilog IP cores for the various components
Documentation on the Wiki
No-OS device drivers, setup, and test code
Linux device drivers where applicable
Source of all information is the Analog Devices Wiki
29
30. HDL IP Interface Core
What function does it typically
provide:
Drives converter control signals
Samples data
Abstracts and mediates data up in the
hierarchy
Pre and postprocessing
Conversions
Format, scale, offset, etc.
Sign extention
Extracting, selecting data
Interface timing validation
PN number checker
Status, error tracking
Overrange, DMA status
Allows engineers to insert custom
IP, while maintaining the interfaces
on both ends
30
ADC
N
Fdata
Fs
DCO
AXI
AXILite
AXIDMA
ConverterIPCore
CustomIP
31. Example HDL Blocks: HDMI Tx/Rx and SPDIF
31
This reference design
provides the video
and audio interface
between the FPGA
and ADV7511/ADV7611
HDMI Tx/Rx.
HDMI transmitter also
found on various Xilinx
evaluation boards:
ZC702
ZC706
ZedBoard
KC705, etc.
Linux DRM, V4L2, ASoC
device drivers available.
ADI IP CoreXilinx IP Core
32. HDL Blocks: AD-FMCJESDADC1-EBZ
JESD204B serial interface
Reference design for:
Virtex-7, Kintex-7, Virtex-6
KC705
ZC706
VC707
ML605
32
ADI IP CoreXilinx IP Core
33. Effect of FR4 Channel Loss at 3.25 Gbps
33
At higher line rates, pre-emphasis
and equalization techniques are
used to compensate channel loss,
due to the limited bandwidth of the
media.
Equalization works at the receiver
end while pre-emphasis on the
transmitter side.
Selectively boost the high frequency
components in order to compensate the
channels high frequency roll off.
Quality of the line cannot be
determined by measuring the far-
end eye opening at the receiver
pins.
Real-time oscilloscopes for
multigigabit SerDes measurements
cost $$$.
3.25 Gbps – Ideal Source
3.25 Gbps – After 40” FR4How to verify link reliability?
34. The Statistical Eye (2D Post Equalization)
The Rx Eye Scan in Xilinx GTH, GTX, and
GTP transceivers of 7 series FPGAs
provides a mechanism to measure and
visualize the receiver eye margin after the
equalizer.
Statistical eye scan functionality on per-lane
basis is based on comparison between the
data sample in the nominal center of the
eye and the offset sample captured by an
independent and identical circuitry at a
programmable horizontal and vertical offset.
Bit error (BER) is defined as a mismatch
between these two samples.
Taking BER measurements at all horizontal
and vertical offsets allows drawing a 2D
eye diagram while enabling BER to be
measured with high confidence down to
10
-15
.
34
Nominal Sample
Offset Sample
35. JESD204B High-Speed ADC Demo
35
Analog Devices’
AD-
FMCJESDADC1-
EBZ 14-bit / 250
MSPS
4-ch ADC
AD9250 High
Speed
JESD204B
Serdes Outputs
Data Eye @
5Gbps
Analog Input
(Single-Tone FFT with
fIN = 90.1 MHz)
Ethernet data
connection to PC for
Verification of
Analog Signal on
VisualAnalog™
Xilinx Kintex-7 FPGA KC705 Eval Kit
Recovered Eye
(after EQ/CDR)
37. Linux Kernel Basics
Advantages of Linux
Broad use as an open source desktop, server, and embedded OS
Feature-rich
Symmetric multiprocessing
Preemptive multitasking
Good RT performance
Shared libraries
Countless device drivers
Memory management
Support for almost any networking and protocol stack
Support for multiple file systems
Linux kernel is a free and open-source software
Licensed under the GNU Public License
Therefore, easy to extend and modify
37
Memory Devices
Applications
CPU
Kernel
38. Linux Support for Xilinx FPGA Hard and Soft
Cores
FPGA Hard Core:
Zynq
Dual core ARM Cortex™-A9
PowerPC (PPC)
Pros
Avoids extra co-processor
Fast data exchange between FPGA and CPU
Less power, board space, and system cost
Cons:
May require external memory
FPGA Soft Core:
Microblaze
Pros
Avoids extra co-processor
Fast data exchange between FPGA and CPU
A soft core can be customized to meet system
demands
Cons:
Requires some extra gates and external
memory
May not be as fast as a hard core
Power consumption
38
Linux is an ideal OS and a significant part of the
ecosystem for FPGA hard and soft cores
39. Linux Driver Model Basics
The Linux driver model
breaks all things down into:
Buses
Devices
Classes
A bus can be described as
something with devices
connected to it.
A device class describes
common types of devices,
like sound, network, or input
devices, sometimes referred
as subsystems.
Examples of buses
in Linux are:
ACPI
I2C
IDE
MDIO bus
PCI/Express
Platform (MEM mapped)
PNP
SCSI
SERIO
SPI
USB
39
Hardware
I2C
HWMON
SPI
IIO
40. Linux Driver Model Basics
Each device class defines a set of
semantics and a programming
interface that devices of that class
adhere to.
Device drivers are typically the
implementation of that programming
interface for a particular device on a
particular bus.
Device classes are agnostic with
respect to what bus a device resides
on.
The unified bus model includes a set of
common attributes which all buses
carry, and a set of common callbacks,
such as ideal device discovery during
mandatory bus probing, bus shutdown,
bus power management, etc.
Summarize:
The Linux driver model provides a
common, uniform data model for
describing a bus and the devices
that can appear under the bus.
Device drivers are agnostic with
respect to what processor platform
they run on, in case they are
registered with a common bus that
the target platform supports.
40
41. IIO—a New Kernel Subsystem for Converters
The Linux industrial I/O subsystem is
intended to provide support for devices that,
in some sense, are analog-to-digital or digital-
to-analog converters
Devices that fall into this category are:
ADCs
DACs
Accelerometers, gyros, IMUs
Capacitance-to-Digital converters (CDCs)
Pressure, temperature, and light sensors, etc.
Can be used on ADCs ranging from a SoC ADC to
>100 MSPS industrial ADCs
Mostly focused on user-space abstraction, but also
in-kernel API for other drivers exists
IIO to Linux input or HWMON subsystem bridges
41
42. IIO Subsystem Overview
42
SYSTEM CALL INTERFACE
VIRTUAL FILE SYSTEM (VFS)
APPLICATION
CHARACTER DEVICE
DRIVER
HARDWARE
Kernel Area
Application
Area
Hardware
SYSFS
DEVICE DRIVER
IIO BUFFER IIO CORE IIO TRIGGERIIO Subsystem
BUS DRIVERS
IIO Device Drivers
43. AXI ADC Linux Driver
Each and every IIO device,
typically a hardware chip, has a
device folder under:
/sys/bus/iio/devices/iio:deviceX.
Where X is the IIO index of the
device. Under every of these
directory folders resides a set of
files, depending on the
characteristics and features of the
hardware device in question.
These files are consistently
generalized and documented in
the IIO ABI documentation. In
order to determine which IIO
deviceX corresponds to which
hardware device, the user can
read the name file:
/sys/bus/iio/devices/iio:deviceX/
name.
43
44. IIO Devices
Linux—everything is a file
IIO control via sysfs
IIO data via device nodes
/dev/iio:deviceX
Attributes/files:
Control converter modes
Enable/disable channels
Query data format, byte-
order, alignment, index
Query and set
Sampling frequency
Test modes
Reference levels
etc…
44
User Application
int main(…){
fd = open(/dev/iio:…);
read(fd, buf, RCNT);
…
}
45. Example Device Driver: VGA/PGA Gain Control
45
out_voltage1_hardwaregain
/sys/
bus/
iio/
iio:device0/
dev name out_voltage0_hardwaregain
/sys/bus/iio/iio:device0 # cat name
ad8366-lpc
/sys/bus/iio/iio:device0 # echo 6 > out_voltage1_hardwaregain
/sys/bus/iio/iio:device0 # cat out_voltage1_hardwaregain
5.765000 dB
Device attributes
Very convenient for configuring and
controlling devices using shell scripts
Shell Commands:
AD8366
0.25dB Step Size
600MHz Bandwidth
SPI
46. AD9517-1 Multi-Output Clock Generator/
Distribution Control
46
Outputs individually
controllable
Enable/disable
Set/get frequency
IIO device driver, but also
registers with the Linux
clock consumer/producer
framework
47. JESD204B Receiver Interface Linux Device
Driver
47
Ease of use Rx Eye Scan
Nondestructive
Implemented all in gates
No runtime overhead
Direct read access to
JESD204 link parameters
(ILA)
Interface configuration via
device tree
axi_jesd204b_rx4_0: axi-jesd204b-rx4@77a00000 {
compatible = "xlnx,axi-jesd204b-rx4-1.00.a";
reg = < 0x77a00000 0x10000 >;
jesd,lanesync_en;
jesd,scramble_en;
jesd,frames-per-multiframe = <32>;
jesd,bytes-per-frame = <2>;
clocks = <&clk_ad9517 0>;
clock-names = "out0";
} ;
Xilinx LogiCORE™ IP JESD204 core
48. Analog Devices 2D Statistical Eye Scan
Application Runs Natively on ZYNQ ZC706
48
Graphical front end (GUI) JESD204B receiver interface Linux device driver
49. Data to VisualAnalog
VisualAnalog™ is a
software package that
combines a powerful set of
simulation, product
evaluation, and data
analysis tools with a user-
friendly graphical interface
Measure and visualize
SNR, SFDR, THD, power,
etc.
IIO command client
Control Linux IIO device
drivers and capture data via a
TCP network connection
49
51. Analog Devices Wiki
This Wiki provides developers
using Analog Devices products
with:
Software and documentation
HDL interface code
Software device drivers
Reference project examples for
FPGA connectivity
It also contains user guides for
some Analog Devices
evaluation boards to help
developers get up and running
fast
http://wiki.analog.com/
51
52. At Analog Devices, we
recognize that our products are
just one part of the design
solution.
We are supporting seamless
integration of ecosystems and
tools by offering HDL interface
code, device drivers, and
reference project examples for
FPGA connectivity.
This community is for the
discussion of these reference
designs.
http://ez.analog.com/community/fpga
52
FPGA Reference Designs Support Community
53. Analog Devices creates and
maintains Linux device drivers
for various ADI products.
Some software drivers are also
available for ADI products that
connect to microcontroller
platforms without an OS.
The purpose of this community
is to provide support for these
drivers.
To see the list of available
drivers supported, visit
the Analog Devices Wiki
http://wiki.analog.com
http://ez.analog.com/community/
linux-device-drivers
53
LINUX and Microcontroller Device Drivers
Support Community
54. Design Resources Covered in this Session
Design Tools and Resources:
Ask technical questions and exchange ideas online in our
EngineerZone™ Support Community
Choose a technology area from the homepage:
ez.analog.com
Access the Design Conference community here:
www.analog.com/DC13community
57
Name Description URL
VisualAnalog http://www.analog.co
m/visualanalog
Analog Devices
Wiki
Software and documentation
HDL interface code
Software device drivers
Reference project examples for FPGA connectivity
http://wiki.analog.com/
[other]
55. Tweet it out! @ADI_News #ADIDC13
Selection Table of Products Covered Today
58
Part number Description
AD-FMCJESDADC1-
EBZ
FMC-based AD9250 evaluation board
CVT-ADC-FMC-INTPZ FMC to high speed ADC evaluation board adaptor
AD-DAC-FMC-ADP FMC to high speed DAC evaluation board adaptor
SDP-FMC-IB1Z SDP-to-FMC interposer board
56. Tweet it out! @ADI_News #ADIDC13
Visit the AD9250-FMC JESD204B Demo in the
Exhibition Room
AD9250-FMC250-EBZ card, connected to Xilinx development system
(ZC706), streaming data to VisualAnalog (over Ethernet), to measure
converter performance (SNR, SFDR).
Alternatively data can be visualized on a Linux desktop environment. HDMI
monitor, mouse, keyboard connected to the ZC706.
Concurrently measure and visualize the receiver eye margin on all
JESD204B lanes.
GO to Xilinx to find out more on LogiCORE™ IP JESD204 core.
59
This demo board is available for purchase:
http://www.analog.com/DC13-hardware
57. What We Covered
Overview high speed converter interface styles and standards
Detailed look at the JESD204B interface standard
Analog Devices FPGA design support offerings
60