Roy aeroVerifying Power Domains in AeroFONE


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Roy aeroVerifying Power Domains in AeroFONE

  1. 1. Verifying Power Domains in AeroFONE®Subrata RoySenior Design Engr, Wireless10/23/
  2. 2. 2Silicon Labs PortfolioProducts8-bit, 8051,Mixed-Signal MCUsFixed-FunctionsolutionsProductsFM TunersSiRX™ STB ReceiverXM Satellite ReceiverProductsModemVoicePowerTimingProductsAero® TransceiversAeroFONE®Power AmplifierRF SynthesizersCore CapabilitySystem on a ChipCore CapabilityTuner and DemodIntegrationCore CapabilityPLL and HighVoltage ExpertiseCore CapabilityRF design inCMOSMCUBroadcastWirelineWireless
  3. 3. 3AeroFONE® based DesignSi4700 FMTunerSi4300T PowerAmplifierSi4905 AeroFONE:TX, ABB, DBB, PMU,Battery ChargingCircuitryCP2102 USB toUART Bridge
  4. 4. 4AeroFONE® Power domains♦ Motivations for Multiple Power DomainsPower Saving : power what you needPower Saving : power as much as you need;Voltage scaling for different operating modesBackbias RAM, powerdown ROMDifferent voltages needed by the functionNoise isolation♦ Voltage RegulatorsVpermanentVgpioVext_memoryVcore (Linear regulator, DCDC regulator)VanalogVRFVcustom_digital1Vcustom_digital2
  5. 5. 5Power Control Feedback loopVoltageRegulatorsPowerdomainsBattery♦ The chip controls its power♦ Make sure it is not stuck in a bad state; e.g., waiting for input through anun-powered path while powering-upcontrol statusP_ctlVdd
  6. 6. 6Power Verification-1♦ SpecifyMap blocks to Power domainReset & clocksVoltage modes, dynamic operating modes (load current)input power domains, output power domainspre-power domains : domains powered up before this blockpost-power domains: domains powered after this block is poweredup♦ Design :RTL: signal connectivityInterface Cells between power domains (level shifters, logic & noiseisolators) have explicit supply pins; these cells are custom designedAnalog components have explicit supply pins
  7. 7. 7Power Verification-2♦ Static Verification: Checks conditions independent ofstimulus; assuming specified constraintsall inputs of the domain are definedEvery domain can be reset at power upCorrect level shiftingAll outputs to post-power domains are at 0 during ramp-upLot of painful scripting & reviews♦ Dynamic Verification : functional operation of the deviceexercising different power domains & power modesAll possible power up sequencesAll possible sequences of power modesUse AMS methodology
  8. 8. 8Assertions♦ Check that the system is always in valid system powerstates♦ Check that a transition from 1 valid system power state toanother valid system power state satisfies all necessaryconditions♦ ExamplesIf Vext_memory is in low power mode then no access to memoryIf Vgpio is in low power mode then no access to gpio pins except forsome keypad pins
  9. 9. 9Power Verification-3♦ Power Goals♦ Design Level: Characterize Power usage of different blocksin different modes♦ System Level: Use information from Power Characterizationto build system level power modelsExample: DRX2 : 8 slots of p1-mode, 2 slots of p2-mode out of 816slots
  10. 10. 10Modeling♦ The quality of dynamic verification depends on modeling♦ Interface Cells: level shift, logic & noise isolatorsVoltage levels of power supply pins are modeled in Verilog-AMSAny error in voltage levels is indicated by driving X to logic signals aswell as global error flagsLump any effect of the digital load to the Voltage signals of theinterface cell♦ All registers/outputs in a un-powered domain are forced to X♦ The impact of power(vdd) on signals connected to aninterface cell are modeled within the Verilog-AMS model ofthe interface cell♦ Voltage RegulatorsModel impact of controls signals on voltage outputsFocus is on modeling the loop between Digital & analog domainfeedback loops within the analog are ignored
  11. 11. 11Interface Cells- AMS model♦ New disciplines are defined for hv/lv logic in AMS♦ AMS connectrules define the electrical equivalent oflogic_hv/lv♦ AMS automatically inserts connectors based on typeLogic_hv Logic_lvLS_12.CellAMS-modelvdd2vdd1logic_hv_to_electrical connectorelectrical_to_logic_lv connector
  12. 12. 12Summary♦ Static Verification is well defined but requires lot of adhocscripting – standardization will have big impact here♦ Dynamic verificationBetter modeling of effects of system power states using AMSFor unmodeled effects we use constraints to restrict digital behaviorExample: Vgpio low power mode only allows access through somekepad pinsLarge number of combinations of power states and their sequencing7 Regulators3 power on events (power on key, RTC alarm, Charger insertion)Some regulators completely hardware controlled (configured by inputpins); some are software controlledBased on ordering of input events and subsequent software control thereare many possible sequences
  13. 13. 13Wish List♦ Efficient way to model effects of power modes/states♦ Extension of our current modeling language (Verilog) butmore efficient than AMS♦ Some Objectionsdifferent instances have different power contexts,keep power information seperate from designlanguage constructs can address these issues (e.g., parameters,vunit binding in systemverllog)