Asic design

Introduction to
Application Specific Integrated Circuit

Outline
Introduction
ASIC cell library
ASIC design styles
ASIC design flow
ASIC design issues
ASIC Vs. FPGA
ASIC design tools
 Reference
12/16/2019 ASIC Design 2

Introduction
A
S
I
C
Application
Specific
Integrated
Circuit
 It is a custom integrated circuit designed and
optimized to fit a specific purpose and product.

Introduction…
 Examples of ICs that are an ASICs:
 a chip for a toy bear that talks;
 a chip for a satellite;
 a chip designed to handle the interface between
memory and a microprocessor for a workstation
CPU;
 a chip containing a microprocessor as a cell
together with other logic.

ASIC cell library
 The logic cells such as AND, OR, XoR, NOR,
NAND, multiplexers, and flip-flops are
predesigned by designers using different
configurations, standardized and stored in the
form of a library.
 Cell libraries are fixed set of well-
characterized logic blocks.

ASIC cell library…
 Each cell in an ASIC cell library must contain:
 A physical layout
 A behavioral model
 A Verilog/VHDL model
 A detailed timing model
 A test strategy
 A circuit schematic
 A cell icon
 A wire-load model
 A routing model

ASIC design styles

ASIC design styles…
1. Full-Custom ASIC:
 Include some (possibly all) customized logic cells
 Have all their mask layers customized
 Manufacturing lead time is typically 8 weeks
(time taken to make the IC does not include design
time)

1) Full-Custom ASIC…
Full-custom ASIC design makes sense only:
When no suitable existing libraries exist or
Existing library cells are not fast enough or
The available pre-designed/pre-tested cells consume too
much power that a design can allow or
The available logic cells are not compact enough to fit
or
ASIC technology is new or/and so special that no cell
library exits.

 Advantage:
 Offer highest performance
 lowest cost (smallest die size)
 Disadvantages:
 Increased design time
Increased Complexity
Higher design cost
Higher risk.

 Future:
 Maximum performance
 Minimized area
 Highest degree of flexibility
 Examples:
 Microprocessor
 High-Voltage Automobile Control Chips

2. Semi-Custom ASIC:
 Also known as cell-based ASIC, which uses a
pre-designed some (possibly all) logic cells namely
AND gates, OR gates, Multiplexers, Flip-flops,…
(i.e. called standard libraries).
 Only the placement of the standard cells and
interconnection is done.
 All mask layers are customized
 Custom blocks embedded

2) Semi-Custom ASIC…

 Types:
i. Standard cell-based (CBIC- “sea-bick”)
 uses pre-designed library
ii. Gate array (GA) based
 uses pre-defined transistor in the silicon wafer.

i. Standard cell-based (CBIC- “sea-bick”)
 Use predesigned logic cells (Called standard cells)
from:
 standard cell libraries
 other mega-cells (Microcontroller or Microprocessors)
 full-custom blocks
 System-Level Macros(SLMs)
 Functional Standard Blocks (FSBs)
 cores etc

i. Standard cell-based (CBIC- “sea-bick”)…
Get all mask layers customized- transistors and
interconnect
 Manufacturing lead time is about 8 weeks
Custom blocks can be embedded
 Advantages:
 Save time, money, reduce risk
 Standard cell optimized individually for speed or area

i. Standard cell-based (CBIC- “sea-bick”)…
 Disadvantage:
Time to design standard cell library
 Expenses of designing std cell library
 Time needed to fabricate all layers of the ASIC for
new design

ii. Gate array based
 Transistors are predefined on the silicon wafer
 Predefined pattern of transistors on a gate array is base
array.
 Smallest element repeated to form base array is base
cell.
 Only the top few layers of metal, which define the
interconnect between transistors, are defined by the
designer using custom masks. It is often called a
masked gate array ( MGA ).

ii. Gate array based…
 Types:
A) Channeled GA
B) Channelless GA
C) Structured GA

A) Channeled GA
 Only the interconnect is customized
 Space between rows are predefined
 Manufacturing lead time is between
two days and two weeks

A) Channeled GA…
 Advantage:
 Specific space for interconnection
 Disadvantage:
 compared to CBIC space is not adjustable

B) Channelless GA (Channel free gate array, Sea-of-
Gate/SOG/)
 Only some (the top few) mask layers
are customized
 Manufacturing lead time is between
two days and two weeks

B) Channelless GA…
 Advantage:
 Logic density is higher for channelless gate array
 Contact layers are customized
 Disadvantage:
 No specific area for routing
 Rows of transistors used for routing are not used for other
purpose.

C) Structured GA (Masterslice or Masterimage)
 Only the interconnect is
customized
 Custom blocks (the same for
each design) can be embedded
 Manufacturing lead time is
between two days and two
weeks

C) Structured GA…
 Advantage:
 Embedded gate array set in some of IC area and dedicate to
specific function-customized.
 Increase area efficiency, performance of CBIC
 low cost and fast turn around of MGA
 Disadvantage:
 Embedded function is fixed

3. Programmable ASIC:
all of the logic cells are predesigned and none of
the mask layers are customized.
 Types:
a) Programmable Logic Design (PLD)
b) Field Programmable Gate Array (FPGA)

3) Programmable ASIC…
a) Programmable Logic Design (PLD):
No customized mask layers or logic cells
Fast design turnaround
A single large block of programmable interconnect
A matrix of logic macro cells that usually consist of
programmable array logic followed by a flip-flop or
latch

a) Programmable Logic Design (PLD)…
A programmable logic device (PLD) die

a) Programmable Logic Design (PLD)…
 Types:
Programmable Logic Array (PLA):
 has a programmable AND logic array, or AND plane , followed
by a programmable OR logic array, or OR plane
Programmable Array Logic (PAL):
 has a programmable AND plane and, in contrast to a
PLA, a fixed OR plane.

b) Field Programmable Gate Array (FPGA):
None of the mask layers are customized.
A method for programming the basic logic cells and the
interconnect.
The core is a regular array of programmable basic logic
cells that can implement combinational as well as
sequential logic (flip-flops).
A matrix of programmable interconnect surrounds the
basic logic cells.
Programmable I/O cells surround the core.
Design turnaround is a few hours.

b) Field Programmable Gate Array (FPGA)…
Field-programmable
gate array (FPGA) die

ASIC design flow

ASIC design flow…
1. Design entry: Enter the design into an ASIC design system, either
using a hardware description language(HDL) or schematic entry.
2. Logic synthesis: Use an HDL (VHDL or Verilog) and a logic
synthesis tool to produce a netlist description of the logic cells and their
connections.
3. System partitioning: Divide a large system into ASIC- sized pieces.
4. Pre-layout simulation: Check to see if the design functions
correctly.
5. Floor planning: Arrange the blocks of the netlist on the chip.
6. Placement: Decide the locations of cells in a block.
7. Routing: Make the connections between cells and blocks.
8. Extraction: Determine the resistance and capacitance of the
interconnect.
9. Post-layout simulation: Check to see the design still works with the
added loads of the interconnect.

ASIC design issues
 Factors to consider before design:
 Performance
 Functionality
 Design Techniques
 Physical dimensions
 Fabrication technology
 Specification
 Area
 Speed
 Power

ASIC Vs. FPGA
No. FPGA ASIC
1 Reconfigurable circuit. FPGAs can
be reconfigured with a different
design. They even have capability
to reconfigure a part of chip while
remaining areas of chip are still
working! This feature is widely
used in accelerated computing in
data centres.
Permanent circuitry. Once the
application specific circuit is taped-
out into silicon, it cannot be
changed. The circuit will work same
for its complete operating life.
2 Design is specified generally using
hardware description languages
(HDL) such as VHDL or Verilog.
Same as for FPGA. Design is
specified using HDL such as
Verilog, VHDL etc.
Note: For more information click here

ASIC design tools

Reference
1. Rajeev Jayaraman, Xilinx Inc,
2001 https://www.doc.ic.ac.uk/~wl/teachlocal/arch/killasic.pdf
2. Fasang, P.P., Mullins, D. and Wong, T., 1988, May. Design for
testability for mixed analog/digital ASICs. In Custom Integrated
Circuits Conference, 1988., Proceedings of the IEEE 1988 (pp. 16-
5). IEEE.
3. Bhatnagar, H., 2007. Advanced ASIC Chip Synthesis: Using
Synopsys® Design CompilerTM Physical CompilerTM and
PrimeTime®. Springer Science & Business Media.
4. Bansal, J.P., BAE Systems Information and Electronic Systems
Integration Inc, 2004. Gate array core cell for VLSI ASIC devices.
U.S. Patent 6,765,245.
5. Wu, K.C. and Tsai, Y.W., 2004, April. Structured ASIC, evolution
or revolution?. In Proceedings of the 2004 international
symposium on Physical design (pp. 103-106). ACM.

Reference…
6. Crosetto, D.B., D Computing Inc, 1999. High-speed, parallel, processor
architecture for front-end electronics, based on a single type of ASIC, and
method use thereof. U.S. Patent 5,937,202.
7. Trimberger, S.M., Xilinx Inc, 2003. Method for making large-scale ASIC
using pre-engineered long distance routing structure. U.S. Patent 6,601,227.
8. Rajsuman, R., 2000. System-on-a-chip: Design and Test. Artech House, Inc..
9. Hamida, N.B. and Kaminska, B., 1993, October. Analog circuit testing
based on sensitivity computation and new circuit modeling. In Proceedings of
IEEE International Test Conference-(ITC) (pp. 652-661). IEEE.
10. Rose, J., Francis, R.J., Lewis, D. and Chow, P., 1990. Architecture of field-
programmable gate arrays: The effect of logic block functionality on area
efficiency. IEEE Journal of Solid-State Circuits, 25(5), pp.1217-1225.
11. Brown, S.D., Francis, R.J., Rose, J. and Vranesic, Z.G., 2012. Field-
programmable gate arrays (Vol. 180). Springer Science & Business Media.
12. Barnett, P.C., Advanced Technology Materials Inc, 2001. Field
programmable gate array (FPGA) emulator for debugging software. U.S.
Patent 6,173,419.

Reference…
13. Rose, J., El Gamal, A. and Sangiovanni-Vincentelli, A., 1993. Architecture
of field-programmable gate arrays. Proceedings of the IEEE, 81(7), pp.1013-
1029.
14. Trimberger, S.M. ed., 2012. Field-programmable gate array technology.
Springer Science & Business Media.
15. Ebeling, W.H. and Borriello, G., Washington Research Foundation,
1993. Field programmable gate array. U.S. Patent 5,208,491.
16. Wu, J., Shi, Z. and Wang, I.Y., 2003, October. Firmware-only
implementation of time-to-digital converter (TDC) in field-programmable gate
array (FPGA). In Nuclear Science Symposium Conference Record, 2003
IEEE (Vol. 1, pp. 177-181). IEEE.
17. Khatakhotan, M., S MOS Systems Inc, 1992. Gate array architecture with
basic cell interleaved gate electrodes. U.S. Patent 5,079,614.
18. Gheewala, T.R., Breid, D.G., Sherlekar, D.D. and Colwell, M.J., Virage
Logic Corp, 2003. Gate array architecture using elevated metal levels for
customization. U.S. Patent 6,617,621.

Asic design

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