The document describes a technical challenge to design an FPGA system to acquire baseband signals from two external ADCs, filter and downsample the data, and stream it to an application running on an APU. The proposed solution includes a block diagram with dual-port FIFOs to interface the ADCs, a decimation filter to downsample the data, and DMA to transfer the data to software over an AXI stream interface. The feasibility discusses the expected resource utilization and data rates. Concerns about future work to optimize the decimation filter are also discussed.

1. Interview: Technical challenge
Candidate: Maikon Nascimento
28-Sept-2021

2. 2
Agenda
Introduction:
Problem Definition
High-level design aspects
Solution:
Block diagram
Interfaces Design
Feasibility
Conclusion:
Concerns
Future Work

3. 3
Introduction: Problem Definition
●
Technical Task: Provide an FPGA design for a
Xilinx MPSoC to acquire a complex baseband
signal using two external ADCs accessed over
SPI, filter/downsample the data and stream it to
an application SW running on the APU. Assume
12-bit component samples, 1 MSPS ADC sample
rate, 50 kSPS output sample rate, Linux running
on the APU.

4. 4
Introduction: Problem Definition
●
1 MSPS and 12b and 1b per clock, the ADC will have 12 MHz as working clock;
●

5. 5
Solution: Block Diagram
●
Assuming 2 ADCs where: 1 for I and the other for Q;
●
Dual Port FIFO assuming the output of the ADCs could have a skew clock issue and we want the 12b words together;
●
The decimation will convert the 24b 1 MSPS to 24b 50 kSPS;
●
DMA transfer the data to the SW APP running in Linux controlling the DMA and pulling data.

6. 6
Solution: Block Diagram
●
Dual port FIFO to deal with the cross clocking domain and grouping the words
●
Decimation algorithm for 20 down of scale factor, which becomes 20 taps in a FIR moving sum filter.
●
Output buffer to buffer the data before transmitting to help the burst of data transfer

7. 7
Solution: Block Diagram –
Decimation Filter
●
Output depends on the current and previous M=20 input samples;
●
Aiming to use the DSPs available in the FPGA for multipliers; The MPSoC may have a
multiplier and accumulator integrated together which should be the aim.
●
Also aiming to infer the minimal adders in the logic; Which can happen with the use of
the specific DSPs from the family.
●
After any operation register the result to improve performance;
●
Re- quantize after the multiplication to keep smaller buses;

8. 8
Solution:Interfaces
●
2 ADCs with 12 bit of LVDS
interface will cost 24 FPGA
LVDS CMOS port in;
●
Plus clock and control signals
from the ADC like a valid or
ready signal.
●
SPI interface: MISO, MOSI,
CLK, GND, and CS. The SPI
could be also the case to
send data from the ADCs to
the FPGA which would
require an SPI in the FPGA.
●
Custom logic receiving 24 bit
of data at MSP;
●
Master and Slave AXI Stream
to interface the DMA.
●
Slave port in the APU to
transfer data from the DMA to
the Linux APU.
●
Controlling the DMA from an
user application in the Linux
to access the registers via
/dev/mem. This is not a
custom DMA but Xilinx DMA
with SR registers available.
●
Vivado tells you at Address
Editor where it is the offset of
the DMA.
●
Maybe a custom signal
connect from the FPGA to
the APU to inter an INT to tell
where new data is available.

9. 9
Solution: Feasibility
● Roughly FPGA resources utilization: number of Logic Element, Registers, Adders, DSP/Multipliers,
Memory, Desired Performance in terms of frequency, and Power consumption.
● Data rate requiments for data transfer from the FPGA to the APU.
● Real-time requirements in the embedded Linux application.
● ADCs for RF AD9361

10. 10
Solution: Feasibility
● Report of Design
implementation to estimate
device utilization.
● Xc7z020clg400
● “could go further here and
explain why this is not a
constrainted design, what
would have changed”.

11. 11
Conclusion
●
This presentation demonstrates a solution and how to approach a DSP problem using a FPGA/APU SoC;
●
Block diagrams were used to describe the solution for data transfer, filtering, interfaces, algorithm
implementation;
●
It was given 4h to complete the task so a high level solution was presented to discuss high level ideas;
●
For the advent of more time I would like to investigate the decimation solution of open APIs like ffmpeg and
openCV for possible use of other strategies that would consume less memory (taps ?) which is a future work.

12. 12
Appendix I – Fixed Point Mult.
●
Just a sample showing the Fixed point multiplication and re-
quantization after the multiplication, this case is a 100 gl pixel
multiplied by a 0.5 decimal point number converted to fixed
point 128, the output is 16 but after the re-quantization is
comes back to 8bit.

13. 13
Appendix II – Debugging Strategy
●
For SW the use of GBD with breaking points and messages.
●
For FPGA:
– ILA for debugging the code inside the FPGA;
– Simulation tools like Modelsim for code functionality verification;
– For extra verification with high level languages like Python as a wrapper in tools like Vunit;
– Math can be checked with Matlab/octave;