Cockatrice is a hardware design environment that allows designing hardware circuits from Elixir code. It synthesizes Elixir code following the "Zen style" of using enumerations and pipelines to describe dataflow into a hardware description language representation of a dataflow circuit. The synthesis flow analyzes the Elixir code, generates hardware modules from functions, connects them as a dataflow circuit, and outputs the final circuit description along with an interface driver for communication between the generated hardware and a Elixir software application. This allows accelerating parts of Elixir code by offloading processing to customized hardware circuits designed from the Elixir code.

1. Cockatrice
Hardware Design Environment
with Elixir
Hideki Takase
(Kyoto University / JST PRESTO)
takase@i.kyoto-u.ac.jp

2. Who am I?
@takasehideki
− Assistant Professor at Kyoto University
− Researcher at PRESTO program,
Japan Science of Technology Agency
My Research Topics/Interests
− System level design for
embedded real-time systems
− IoT computing architecture
SW/HW codesign for
processors and FPGA!
− and,,, Elixir for IoT!!!
2

3. Thank to,,, with Wabi-Sabi
• My students in lab.
− Kentaro Matsui
− Yasuhiro Nitta
• My research partners at fukuoka.ex
− @zacky1972
− @hisawayex
− @piacere_ex
− @enpedasi
• My friends at hls-friends
− Tech comm. for self-made high-level synthesis tools
3

4. Introduction of
HW Design on FPGA
• What is FPGA?
• Advantages, applications, and design flow
• High level synthesis and high level design

5. “do what needed immediately”
• application specific architecture
• dedicated data width and
customized units as needed
Computational Resources
”do whatever is instructed"
• universal data path to
cover all application cases
• fixed data width and
arithmetic units
processor
with
software
ASIC
as
hardware
5

6. Computational Resources
6
design flexibility
development cost
power efficiency
performance
FPGA
processor
with
software
ASIC
as
hardware

7. What is FPGA?
• Field Programmable Gate Array
− LSIs whose contents can
be changed any time
− We can design a unique
digital circuit (HW) on it
− Two major vendors
Xilinx・Altera (powered by Intel)
7
IOB
SB
CB LB
IOB
IOB
SB
IOB LB
SB
CB CB
SB
CB
SB SB
CB CBLB IOBIOB LB
SB SB SB
IOB IOB
CB
CB
CB
CB
CB
CB
I/O block
connection blockLB logic block
IOBSB switching block
CB
LUT
IN OUT
0000 1
0001 0
0010 0
… …
1110 1
1111 0
D-FF
D Q

8. Common Design Flow
8
RTL description
RTL simulation
logic synthesis
technology mapping
placement and routing
bitstream generation
• Design by Hardware
Description Language (HDL)
always@(posedge clk) begin
if (!rst) out <= 0;
else begin
case (in)
4'b0001 : tmp <= 1;
4'b0010 : tmp <= 5;
4'b1100 : tmp <= 7;
default : tmp <= 0;
endcase
end
end
assign out = ~{reg[7:4], tmp[3:0]};
post-layout simulation

9. Common Design Flow
9
RTL description
RTL simulation
logic synthesis
technology mapping
placement and routing
bitstream generation
post-layout simulation
LUT
LUT
EDA tools support
almost everything!

10. How to Use of FPGA
10
processor
通信バス
FPGA
Offloading
heavy processing
HW
HW
interface IF
circuit
performance improvement
and low power consumption
can be achieved
SW
SW
communication
between SW/HW
SW
SW
IF
driver

11. Applications of FPGA
• Used as LSIs for rapid design of ASICs
− Functionality of ASICs can be verified before production
− Development of SW can be started before
HW manufacturing is completed
• Used as LSIs for final products
− There are already so many practical consumer products
− It is possible to have a rewriting function after shipping
− Recent practical applications
 Financial market transaction, robotics and automotive
 Data center / cloud server
 Machine Learning!!
11

12. Machine Learning on FPGA
• Accelerator of CNN/DNN
− Neuron synapse values flow through the pipeline
12
Ref: K. Ovtcharov, et al. Toward Accelerating Deep Learning at Scale Using Specialized Hardware in the Datacenter,
HotChips27, 2015.
C. Zhang, et al. Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks, FPGA 2014.

13. Advantage of FPGA
13
FPGA
Memory
Func Func
Func FuncFunc
Func FuncFunc
FuncFunc
• Various systems can be designed onto one LSI
• High performance / low power consumption
• Parallel processing can be realized at task/data level
• Data streaming processing can be realized

14. Current Technology Trends
• Increase in circuit scale and amount of LB
− High performance systems can be realized
− Further increase will continue by new technology
 multi-die, 3D stacking,,,
• Tightly coupling with processors
− General-purpose: Connection via PCIe to processors
− Embedded: Integration with embedded processors
14
high-quality system design
in a short time
has become difficult,,,

15. High Level Synthesis (HLS)
• Solution to improve design productivity!
− Technology for synthesizing HDL from behavioral
descriptions with a programming language
C/C++ or its extension is commonly used
− Abstraction level of design becomes higher
15
int func (int x) {
int a[N];
int i;
for(i=0;i<N;i++){
a[i] = ･･･;
:
:
}
:
}
x
func
i
a

16. Commercial HLS Tools
• Xilinx Vivado HLS
− Synthesize from C/C++
− #pragma is offered to
indicate the optimization
16
• Intel SDK for OpenCL
− Synthesize from
OpenCL parallelized code
− Can be executed with same
description as the host PC
Ref: Xilinx Inc. White paper UG902
D. Neto, Optimizing OpenCL for Altera FPGAs, Int’l Workshop on Open CL, 2014.
It is essential to understand
#pragma and libraries deeply
for deriving optimized hardware

17. not only C/C++!!
• Chisel: Scala based
− Object Oriented / Functional styled DSL
• CλaSH: Haskell based
− Synthesize HDL from description of functional language
• Karuta: original scripting language
• Synthesijer: Java based
− HLS from the subset of Java specification
• PyCoRAM, Polyphony: Python based
 Veriloggen: Python library for HDL design
• Mulvery: Ruby based
− Synthesis from Reactive Programming
• Octopus🐙：OCaml based
17
developed by
Japanese
hls-friends!!

18. OK, What We Want is,,,
18
We want to design
HW by Elixir!!
We want to operate HW
from our Elixir code!!

19. Concept of Cockatrice
• Elixir Zen Style
• Why Elixir would be suitable for HW design?
• HW synthesis flow from Elixir code
• SW/HW communication interface

20. What is Cockatrice?
• Summoned beast that appears in FF4 (^^;
− The effect is to make all enemies to stones
• Hardware design environment with Elixir!
• Features
− It synthesizes Elixir Zen Styled code
to the description of HW circuits
− It provides communication interface
between Elixir code and HW circuits
20
Your Elixir code can be accelerated,
and low-powered!!
NOTE: Current logo of cockatrice is from Wikipedia

21. Elixir Zen Style
• Enum:
transform data directly
• Flow:
realize parallel processing
intuitively (by MapReduce)
• |>: pipeline operator
express data flow intuitively
• Zen(禅) means the essential beauty
− The essential of programming is data transformation
− Enum Flow |> describe only data transformation
21
input_list
|> Flow.from_enumerable()
|> Flow.map(& foo(&1))
|> Flow.map(fn a->-a end)
|> Enum.to_list
|> Enum.sort

22. Zen’s process model
22
input_list
|> Flow.from_enumerable(stages: 4)
|> Flow.map(& foo(&1))
|> Flow.map(fn a->-a end)
|> Enum.to_list
|> Enum.sort
from_
enumerable
input_list
foo
foo
foo
foo
sortto_list
arbitrator
-a
-a
-a
-a
It’s similar to
efficient HW
architecture!!

23. Zen is suitable for HW design!
23
Cockatrice
input_list
|> Flow.from_enumerable(stages: 4)
|> Flow.map(& foo(&1))
|> Flow.map(fn a->-a end)
|> Enum.to_list
|> Enum.sort
from_
enumerable
input_list
foo
foo
foo
foo
sortto_list
arbitrator
-a
-a
-a
-a
We summon Cockatrice to lithify
Elixir Zen Styled Code
as parallel HW stones!!

24. Effect of Cockatrice
24
Input
List from_
enume
rable
to_list
sort
foo -a
foo -a
foo -a
foo -a
arbitrator
foo -a
foo
-a
foo -a
foo
-a
foo
-a
foo
foo -a
foo
-a
foo -a -a
foo -a
foo -afoo -a
foo -a

25. HW Description by Elixir
• defcockatrice part will be
treat as HW description
− It is completely equivalent
to native Elixir code
You do not need to
consider HW design
It can be verified at
functional level
• HW module can be called
as same as SW function
− We assume SW/HW
cooperative systems
25

26. Synthesis Flow
26
Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)

27. Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)
Synthesis Flow
27
Metaprogramming method is employed
to derive AST of Zen styled design
description by Quote function

28. Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)
Synthesis Flow
28
we provide templates of HDL
code that are equivalent to
Enum functions as DSL files
HDL code is synthesized by
applying pattern matching
with AST and DSL

29. Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)
Synthesis Flow
29
each modules is connected as data flow
from AST representation of |> and Flow
data flow and parallel processing
HW circuit is finally synthesized!!

30. Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)
Synthesis Flow
30
communication interface
and its driver are
generated as NIF function

31. Code analysis &
AST optimization
design desc.
Elixir
templates for IP
DSL
info. of desc.
AST
Synthesis of
HW modules from
Elixir function
HW IP modules
HDL
data flow HW
circuit HDL
HW circuits
bitstream
logic synthesis
SW app
Elixir+C(NIF)
Compilation
of SW
Generation of
device driver
of I/F circuit
Synthesis of
data flow
I/F driver
C(NIF)
SW binary and HW bit files are
compiled by respective tools
Synthesis Flow
31
SW binary and HW bit files are
compiled by respective tools

32. SW/HW Comm. Interface
• Activation/Operation to
HW from Elixir code
• Data communication
between SW and HW
− AXI4 bus on Zynq is used
• We implement device
driver as C/NIF module
− ikwzm/udmabuf is used
for DMA transfer
− Elixir/Erlang list should be
converted to C array
32
FPGA
processor
DMA buffer
HW circuits
Elixir app
Erlang VM
device driver
(NIF module)
interface
circuit

33. Our Targets
33
Zynq-7000 Zynq UltraScale+

34. Demonstration Time??
• Board: Avnet Ultra96-V2
− Zynq UltraScale+ ZU3EG
− 1.5GHz quad-core Arm Cortex-A53
− 16nm FinFET+ programmable logic
$249.00
• EDA tool: Xilinx Vivado 2019.1
• Software platform
− Linux Kernel v4.19.0 with debian10-rootfs-vanilla
from ikwzm/ZynqMP-FPGA-Linux build-v2019.1
with udmabuf v1.4.2 as kernel module
− Elixir 1.9.1-otp-22 / Erlang 22.0.7
34

35. Discussion
&
Future Direction

36. Discussion
• Currently, we just implement prototypes
− We will publish them as Hex pkgs very soon,,,
− Currently supported features are limited
IOW, we only synthesize Zen styled code
Are another Elixir/Erlang process models
suitable for efficient HW architecture?
− Quantitative evaluation of our proposal will be also
important (to verify academic contribution^^;
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37. Discussion
• Applicable range of Cockatrice?
− Not only embedded, but also HPC domain!?
Bigger data for Cockatrice would be suitable
since there is some overhead on SW/HW comm.
− AI/ML would be a killer application
Big data stream processing for IoT
Cloud processing that allows users
to change functions flexibly
− We are planning to support large-scale FPGA
boards with comm. interface for PCIe bus
37

38. BTW, I love Nerves!!
• Experiences at Lonestar2019 was great for me!
• I made a presentation to promote the innovation of
Nerves to Japan at Erlang & Elixir Fest 2019!!
38
Nervesが開拓する
『ElixirでIoT』
の新世界
⾼瀬 英希
(京都⼤学／JSTさきがけ)
takase@i.kyoto-u.ac.jp
18
ライブデモのお品書き
1. Nervesプロジェクトの準備とビルド
2. microSDに書き込んでブート・IEx実⾏
3. ソース編集してlocal ssh書き込み
4. NervesHubから書き込み
5. Scenic連携＆GPIOデバイスの制御
Raspberry Pi Zero WH Adafruit 128x64 OLED Bonnet
https://github.com/takasehideki/eefest19demo
NervesKey
『ElixirでIoT』の新世界︕
25
デバイス
エッジサーバ クラウド
あらゆるモノ・コト・ヒトを
ネットワーク化︕
情報科学の総合格闘技︕
新たな社会的価値を創出!!
みんなで⼀緒に
IoTを創ろう︕
14
NervesHub
•サーバ経由のOTA (Over The Air) で
Nervesアプリをリモートデプロイ︕
- X.509署名証明書とNervesKey回路で
セキュアな接続経路を実現
- 更新先とファームを任意指定可

39. Nerves Training in Japan!!
Thank you so much, Justin & Frank!!
39

40. Future Direction
40
What will happen
when Nerves meets Cockatrice?
Please help us, to evolve the new era of
"IoT development with Elixir"

41. Thank you for your attention!!
41