The detailed results are described at GitHub (in English):
https://github.com/jkatsuta/exp-18-1q
(maddpg/experiments/my_notes/のexp1 ~ exp6)
立教大学のセミナー資料(前篇)です。
資料後篇:
https://www.slideshare.net/JunichiroKatsuta/ss-108099542
ブログ(動画あり):
https://recruit.gmo.jp/engineer/jisedai/blog/multi-agent-reinforcement-learning/
ZynqMPのブートとパワーマネージメント : (ZynqMP Boot and Power Management)Mr. Vengineer
2016年2月20日(金)のZynq Ultrasclae+ MPSoC 勉強会で使った資料です。
追記) 2016.05.08
公式ARM Trusted Firmwareのサイトに、Zynq UltraScale+ MPSoCの実装が追加されていていることを明記した
This is the material I used at Zynq Ultrasclae + MPSoC SIG on 20th February (Friday).
Addendum) 2016.05.08
We stated that the implementation of Zynq UltraScale + MPSoC was added to the official ARM Trusted Firmware site.
A Random Forest using a Multi-valued Decision Diagram on an FPGaHiroki Nakahara
The ISMVL (Int'l Symp. on Multiple-Valued Logic) presentation slide on May, 22nd, 2017 at Novi Sad, Serbia. It is a kind of machine learning to realize a high-performance and low power.
The detailed results are described at GitHub (in English):
https://github.com/jkatsuta/exp-18-1q
(maddpg/experiments/my_notes/のexp1 ~ exp6)
立教大学のセミナー資料(前篇)です。
資料後篇:
https://www.slideshare.net/JunichiroKatsuta/ss-108099542
ブログ(動画あり):
https://recruit.gmo.jp/engineer/jisedai/blog/multi-agent-reinforcement-learning/
ZynqMPのブートとパワーマネージメント : (ZynqMP Boot and Power Management)Mr. Vengineer
2016年2月20日(金)のZynq Ultrasclae+ MPSoC 勉強会で使った資料です。
追記) 2016.05.08
公式ARM Trusted Firmwareのサイトに、Zynq UltraScale+ MPSoCの実装が追加されていていることを明記した
This is the material I used at Zynq Ultrasclae + MPSoC SIG on 20th February (Friday).
Addendum) 2016.05.08
We stated that the implementation of Zynq UltraScale + MPSoC was added to the official ARM Trusted Firmware site.
A Random Forest using a Multi-valued Decision Diagram on an FPGaHiroki Nakahara
The ISMVL (Int'l Symp. on Multiple-Valued Logic) presentation slide on May, 22nd, 2017 at Novi Sad, Serbia. It is a kind of machine learning to realize a high-performance and low power.
論文紹介:Dueling network architectures for deep reinforcement learningKazuki Adachi
Wang, Ziyu, et al. "Dueling network architectures for deep reinforcement learning." Proceedings of The 33rd International Conference on Machine Learning, PMLR 48:1995-2003, 2016.
8. 分類⽊ (Decision Tree)
• 特徴マップを分類する, 弱学習器といわれる
1.00
0.53
0.29
0.00
0.09
0.63
0.71
1.00
C1
C2 C1
C
1
C2 C1
X1
X2
X2<0.53?
X2<0.29? X1<0.09?
X1<0.63? X1<0.71?
Y N
N
NN
NY
Y
Y
Y
C1
C1C2 C1C2
C1
8
12. Random Forest (RF)
• アンサンブル学習の⼀種
• 複数の分類⽊(弱学習器)で構成
• クラス分類と回帰が可能
12
Tree 1 Tree 2 Tree n
C1
C2
C1
Voter
C1 (Class)
InputX1<0.53?
X3<0.71? X2<0.63?
X2<0.63? X3<0.72?
Y N
N
NN
NY
Y
Y
Y
C1
C1C2 C1C3
C1
Tree 1
Binary Decision Tree (BDT) Random Forest
...
13. RFのアプリケーション
• Key point matching [Lepetit et al., 2006]
• Object detector [Shotton et al., 2008][Gall et al., 2011]
• Hand written character recognition [Amit&Geman, 1997]
• Visual word clustering
[Moosmann et al.,2006]
• Pose recognition
[Yamashita et al., 2010]
• Human detector
[Mitsui et al., 2011]
[Dahang et al., 2012]
• Human pose estimation
[Shotton 2011]
13
15. FPGA (Field Programmable
Gate Array)
• Reconfigurable architecture
• Look-up Table (LUT)
• Configurable channel
• Advantages
• Faster than CPU
• Dissipate lower power
than GPU
• Short time design
than ASIC
15
22. システムデザインツールの利⽤
22
①
②
④
③
1. Behavior design
+ pragmas
2. Profile analysis
3. IP core generation by HLS
4. Bitstream generation by
FPGA CAD tool
5. Middle ware generation
↓
Automatically done
30. 他のプラットフォームとの⽐較
• Implemented RF following devices
• CPU: Intel Core i7 650
• GPU: NVIDIA GeForce GTX Titan
• FPGA: Terasic DE5-NET
• Measure dynamic power including
the host PC
• Test bench: 10,000 random vectors
• Execution time including
communication time between
the host PC and devices
30
GPU
FPGA
36. Deep Forestへ拡張
• Sliding Window + Cascaded Forestの組合せ
36
Z.H.Zhou, J.Feng, “Deep Forest: Towards An Alternative to Deep Neural
Networks,”arXiv:1702.08835, [v2] Wed, 31 May 2017.