This document proposes a new efficient distributed arithmetic (NEDA) technique for implementing high-speed memory-efficient 1-D 9/7 wavelet filters. NEDA is an area-efficient architecture that does not require ROM, multiplication, or subtraction. It can expose redundancy in adder arrays consisting of entries of 0 and 1. The document describes how NEDA can be used to compute the high pass filter output of a 1-D discrete wavelet transform using 9/7 filters through an example. It also shows the proposed NEDA architecture and processing steps to obtain the low pass and high pass filter outputs with just additions and shifts.
A landing gear assembly consists of various components viz. Lower side stay, Upperside stay, Locking actuators, Extension actuators, Tyres, and Locking pins to name a few. Each unit having a specific operation to deal with, in this project the main unit being studied is the lower brace. The primary objective is to analyse stresses in the element of the lower brace unit using strength of materials or RDM method and Finite Element Method (FEM) and compare both. Using the obtained data a suitable material is proposed for the component. The approach used here is to study the overall behaviour of the element by taking up each aspect, finally summing up the total effect of all the aspects in the functioning of the element.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A landing gear assembly consists of various components viz. Lower side stay, Upperside stay, Locking actuators, Extension actuators, Tyres, and Locking pins to name a few. Each unit having a specific operation to deal with, in this project the main unit being studied is the lower brace. The primary objective is to analyse stresses in the element of the lower brace unit using strength of materials or RDM method and Finite Element Method (FEM) and compare both. Using the obtained data a suitable material is proposed for the component. The approach used here is to study the overall behaviour of the element by taking up each aspect, finally summing up the total effect of all the aspects in the functioning of the element.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Robust Watermarking through Dual Band IWT and Chinese Remainder TheoremjournalBEEI
CRT was a widely used algorithm in the development of watermarking methods. The algorithm produced good image quality but it had low robustness against compression and filtering. This paper proposed a new watermarking scheme through dual band IWT to improve the robustness and preserving the image quality. The high frequency sub band was used to index the embedding location on the low frequency sub band. In robustness test, the CRT method resulted average NC value of 0.7129, 0.4846, and 0.6768 while the proposed method had higher NC value of 0.7902, 0.7473, and 0.8163 in corresponding Gaussian filter, JPEG, and JPEG2000 compression test. Meanwhile the both CRT and proposed method had similar average SSIM value of 0.9979 and 0.9960 respectively in term of image quality. The result showed that the proposed method was able to improve the robustness and maintaining the image quality.
Glocalized Weisfeiler-Lehman Graph Kernels: Global-Local Feature Maps of Graphs Christopher Morris
Most state-of-the-art graph kernels only take local graph properties into account, i.e., the kernel is computed with regard to properties of the neighborhood of vertices or other small substructures. On the other hand, kernels that do take global graph properties into account may not scale well to large graph databases. Here we propose to start exploring the space between local and global graph kernels, striking the balance between both worlds. Specifically, we introduce a novel graph kernel based on the k-dimensional Weisfeiler-Lehman algorithm. Unfortunately, the k-dimensional Weisfeiler-Lehman algorithm scales exponentially in k. Consequently, we devise a stochastic version of the kernel with provable approximation guarantees using conditional Rademacher averages. On bounded-degree graphs, it can even be computed in constant time. We support our theoretical results with experiments on several graph classification benchmarks, showing that our kernels often outperform the state-of-the-art in terms of classification accuracies.
A Cryptographic Hardware Revolution in Communication Systems using Verilog HDLidescitation
Advanced Encryption Standard (AES), is an
advancement of Federal Information Processing Standard
(FIPS) which is an initiated Process Standard of NIST. The
AES specifies the Rijndael algorithm, in which a symmetric
block cipher that processes fixed 128 bit data blocks using
cipher keys with different lengths of 128, 192 and 256 bits.
The earliest Rijndael algorithm had the advantage of
combining both data block sizes of 128, 192 and 256 bits with
any key lengths. AES can be programmed in pure hardware
Verilog HDL, Which includes Multiplexer to enhance more
secure to Cipher text. The results indicate that the hardware
implementation proposed in this project is Decrementing
Utilization of resource and power consumption of 113 mW
than other implementation. Using FPGA lead to reliability on
source modulations. This project presents the AES algorithm
with regard to FPGA and Verilog HDL. The software used for
Simulation is ModelSim-Altera 6.3g_p1 (Quartus II 8.1).
Synthesis and implementation of the code is carried out on
Xilinx ISE 13.4 (XC6VCX240T) device is used for hardware
evaluation.
Real Time System Identification of Speech Signal Using Tms320c6713IOSRJVSP
In this paper real time system identification is implemented on TMS320C6713 for speech signal using standard IEEE sentence (SP23) of NOIZEUS database with different types of real world noises at different level SNR taken from AURORA data base. The performance is measured in terms of signal to noise ratio (SNR) improvement. The implementation is done with “C’ program for least mean square (LMS) and recursive least square (RLS) algorithms and processed using DSP processor with Code composer studio.
vFORTRAN is used as a numerical and scientific computing language. The main objective of the lab work is to understand FORTRAN language using which we solve simple numerical problems and compare different methodologies. Through this project we make use of various functions of FORTRAN and solve a simple projectile problem and also LAPACK library to solve a tridiagonal matrix problem. We use DGESV and DGTSV functions to make it possible. The given problems are built and compiled using a free integrated development environment called CODE::BLOCKS [1] which is an open source platform for FORTRAN and C.
We review our recent progress in the development of graph kernels. We discuss the hash graph kernel framework, which makes the computation of kernels for graphs with vertices and edges annotated with real-valued information feasible for large data sets. Moreover, we summarize our general investigation of the benefits of explicit graph feature maps in comparison to using the kernel trick. Our experimental studies on real-world data sets suggest that explicit feature maps often provide sufficient classification accuracy while being computed more efficiently. Finally, we describe how to construct valid kernels from optimal assignments to obtain new expressive graph kernels. These make use of the kernel trick to establish one-to-one correspondences. We conclude by a discussion of our results and their implication for the future development of graph kernels.
This paper proposes modeling and identification of dynamical systems in delta
domain using neural network. The properties of delta operator are used such as greater
numerical robustness in computation and superior coefficients representation in finite word
length in implementation and well ensured numerical conditioning at high sampling
frequency. To formulate the identification scheme delta operator model is recasted into a
realizable neural network structure using the properties of inverse delta operator.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DAOR - Bridging the Gap between Community and Node Representations: Graph Emb...Artem Lutov
Slides of the presentation given at BigData'19, special session on Information Granulation in Data Science and Scalable Computing.
The fully automatic (i.e., without any manual tuning) graph embedding (i.e., network representation learning, unsupervised feature extraction) performed in near-linear time is presented. The resulting embeddings are interpretable, preserve both low- and high-order structural proximity of the graph nodes, computed (i.e., learned) by orders of magnitude faster and perform competitively to the manually tuned best state-of-the-art embedding techniques evaluated on diverse tasks of graph analysis.
In this paper generation of binary sequences derived from chaotic sequences defined over Z4 is proposed.
The six chaotic map equations considered in this paper are Logistic map, Tent Map, Cubic Map, Quadratic
Map and Bernoulli Map. Using these chaotic map equations, sequences over Z4 are generated which are
converted to binary sequences using polynomial mapping. Segments of sequences of different lengths are
tested for cross correlation and linear complexity properties. It is found that some segments of different
length of these sequences have good cross correlation and linear complexity properties. The Bit Error Rate
performance in DS-CDMA communication systems using these binary sequences is found to be better than
Gold sequences and Kasami sequences.
Recently, WaveNet, which predicts the probability distribution of speech sample auto-regressively, provides a new paradigm in speech synthesis tasks.
Since the usage of WaveNet for speech synthesis varies by conditional vectors, it is very important to effectively design a baseline system structure.
In this talk, I would like to first introduce various types of WaveNet vocoders such as conventional speech-domain approach and recently proposed source-filter theory-based approach.
Then, I will explain a linear prediction (LP)-based WaveNet speech synthesis, i.e., LP-WaveNet, which overcomes the limitations of source-filter theory-based WaveNet vocoders caused by the mismatch between speech excitation signal and vocal tract filter.
While presenting experimental setups and results, I also would like to share some know-hows to successfully training the network.
Presentation of my NSERC-USRA funded summer research project given at the Canadian Undergraduate Mathematics Conference (CUMC) 2014.
Please refer to the project site: http://jessebett.com/Radial-Basis-Function-USRA/
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Robust Watermarking through Dual Band IWT and Chinese Remainder TheoremjournalBEEI
CRT was a widely used algorithm in the development of watermarking methods. The algorithm produced good image quality but it had low robustness against compression and filtering. This paper proposed a new watermarking scheme through dual band IWT to improve the robustness and preserving the image quality. The high frequency sub band was used to index the embedding location on the low frequency sub band. In robustness test, the CRT method resulted average NC value of 0.7129, 0.4846, and 0.6768 while the proposed method had higher NC value of 0.7902, 0.7473, and 0.8163 in corresponding Gaussian filter, JPEG, and JPEG2000 compression test. Meanwhile the both CRT and proposed method had similar average SSIM value of 0.9979 and 0.9960 respectively in term of image quality. The result showed that the proposed method was able to improve the robustness and maintaining the image quality.
Glocalized Weisfeiler-Lehman Graph Kernels: Global-Local Feature Maps of Graphs Christopher Morris
Most state-of-the-art graph kernels only take local graph properties into account, i.e., the kernel is computed with regard to properties of the neighborhood of vertices or other small substructures. On the other hand, kernels that do take global graph properties into account may not scale well to large graph databases. Here we propose to start exploring the space between local and global graph kernels, striking the balance between both worlds. Specifically, we introduce a novel graph kernel based on the k-dimensional Weisfeiler-Lehman algorithm. Unfortunately, the k-dimensional Weisfeiler-Lehman algorithm scales exponentially in k. Consequently, we devise a stochastic version of the kernel with provable approximation guarantees using conditional Rademacher averages. On bounded-degree graphs, it can even be computed in constant time. We support our theoretical results with experiments on several graph classification benchmarks, showing that our kernels often outperform the state-of-the-art in terms of classification accuracies.
A Cryptographic Hardware Revolution in Communication Systems using Verilog HDLidescitation
Advanced Encryption Standard (AES), is an
advancement of Federal Information Processing Standard
(FIPS) which is an initiated Process Standard of NIST. The
AES specifies the Rijndael algorithm, in which a symmetric
block cipher that processes fixed 128 bit data blocks using
cipher keys with different lengths of 128, 192 and 256 bits.
The earliest Rijndael algorithm had the advantage of
combining both data block sizes of 128, 192 and 256 bits with
any key lengths. AES can be programmed in pure hardware
Verilog HDL, Which includes Multiplexer to enhance more
secure to Cipher text. The results indicate that the hardware
implementation proposed in this project is Decrementing
Utilization of resource and power consumption of 113 mW
than other implementation. Using FPGA lead to reliability on
source modulations. This project presents the AES algorithm
with regard to FPGA and Verilog HDL. The software used for
Simulation is ModelSim-Altera 6.3g_p1 (Quartus II 8.1).
Synthesis and implementation of the code is carried out on
Xilinx ISE 13.4 (XC6VCX240T) device is used for hardware
evaluation.
Real Time System Identification of Speech Signal Using Tms320c6713IOSRJVSP
In this paper real time system identification is implemented on TMS320C6713 for speech signal using standard IEEE sentence (SP23) of NOIZEUS database with different types of real world noises at different level SNR taken from AURORA data base. The performance is measured in terms of signal to noise ratio (SNR) improvement. The implementation is done with “C’ program for least mean square (LMS) and recursive least square (RLS) algorithms and processed using DSP processor with Code composer studio.
vFORTRAN is used as a numerical and scientific computing language. The main objective of the lab work is to understand FORTRAN language using which we solve simple numerical problems and compare different methodologies. Through this project we make use of various functions of FORTRAN and solve a simple projectile problem and also LAPACK library to solve a tridiagonal matrix problem. We use DGESV and DGTSV functions to make it possible. The given problems are built and compiled using a free integrated development environment called CODE::BLOCKS [1] which is an open source platform for FORTRAN and C.
We review our recent progress in the development of graph kernels. We discuss the hash graph kernel framework, which makes the computation of kernels for graphs with vertices and edges annotated with real-valued information feasible for large data sets. Moreover, we summarize our general investigation of the benefits of explicit graph feature maps in comparison to using the kernel trick. Our experimental studies on real-world data sets suggest that explicit feature maps often provide sufficient classification accuracy while being computed more efficiently. Finally, we describe how to construct valid kernels from optimal assignments to obtain new expressive graph kernels. These make use of the kernel trick to establish one-to-one correspondences. We conclude by a discussion of our results and their implication for the future development of graph kernels.
This paper proposes modeling and identification of dynamical systems in delta
domain using neural network. The properties of delta operator are used such as greater
numerical robustness in computation and superior coefficients representation in finite word
length in implementation and well ensured numerical conditioning at high sampling
frequency. To formulate the identification scheme delta operator model is recasted into a
realizable neural network structure using the properties of inverse delta operator.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DAOR - Bridging the Gap between Community and Node Representations: Graph Emb...Artem Lutov
Slides of the presentation given at BigData'19, special session on Information Granulation in Data Science and Scalable Computing.
The fully automatic (i.e., without any manual tuning) graph embedding (i.e., network representation learning, unsupervised feature extraction) performed in near-linear time is presented. The resulting embeddings are interpretable, preserve both low- and high-order structural proximity of the graph nodes, computed (i.e., learned) by orders of magnitude faster and perform competitively to the manually tuned best state-of-the-art embedding techniques evaluated on diverse tasks of graph analysis.
In this paper generation of binary sequences derived from chaotic sequences defined over Z4 is proposed.
The six chaotic map equations considered in this paper are Logistic map, Tent Map, Cubic Map, Quadratic
Map and Bernoulli Map. Using these chaotic map equations, sequences over Z4 are generated which are
converted to binary sequences using polynomial mapping. Segments of sequences of different lengths are
tested for cross correlation and linear complexity properties. It is found that some segments of different
length of these sequences have good cross correlation and linear complexity properties. The Bit Error Rate
performance in DS-CDMA communication systems using these binary sequences is found to be better than
Gold sequences and Kasami sequences.
Recently, WaveNet, which predicts the probability distribution of speech sample auto-regressively, provides a new paradigm in speech synthesis tasks.
Since the usage of WaveNet for speech synthesis varies by conditional vectors, it is very important to effectively design a baseline system structure.
In this talk, I would like to first introduce various types of WaveNet vocoders such as conventional speech-domain approach and recently proposed source-filter theory-based approach.
Then, I will explain a linear prediction (LP)-based WaveNet speech synthesis, i.e., LP-WaveNet, which overcomes the limitations of source-filter theory-based WaveNet vocoders caused by the mismatch between speech excitation signal and vocal tract filter.
While presenting experimental setups and results, I also would like to share some know-hows to successfully training the network.
Presentation of my NSERC-USRA funded summer research project given at the Canadian Undergraduate Mathematics Conference (CUMC) 2014.
Please refer to the project site: http://jessebett.com/Radial-Basis-Function-USRA/
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Establishing Optimal Dehydration Process Parameters for Papaya By EmployingA ...IJERA Editor
This study employs a Firefly Algorithm (FA) to determine the optimal osmotic dehydration parameters for papaya. The functional form of the osmotic dehydration model is established via a standard response surface technique. The format of the resulting optimization model to be solved is a non-linear goal programming problem. While various alternate solution approaches are possible, an FA-driven procedure is employed. For optimization purposes, it has been demonstrated that the FA is more computationally efficient than other such commonly-used metaheuristics as genetic algorithms, simulated annealing, and enhanced particle swarm optimization. Hence, the FA approach is a very computationally efficient procedure. It can be shown that the resulting solution determined for the osmotic process parameters is superior to those from all previous approaches.
Studies on Strength Evaluation of Fiber Reinforced Plastic CompositesIJERA Editor
Fiber Reinforced Polymer (FRP) composites are extensively used for primary structural components such as wing, empennage and fuselage; and sub-structures such as wing ribs and intermediate spars in new generation aircraft as they give rise to high stiffness and strength to weight ratio. The failure load predictions of such composites are extremely important in order to ascertain the flight safety during its service periods. The stress analysis is a part of failure prediction process, since the failure criterion, in order to predict failure load, requires information about stresses and strains in a structure. In the present investigation, the stress analyses of CFRP composite laminates with and without cut-outs have been carried out by using both analytical and finite element approaches. In analytical approach, a mat lab code has been developed for a flat panel using Classical Laminated Plate Theory (CLPT) and different composite failure theories. MSC.NASTRAN finite element analysis code is used for carrying out finite element analysis. Convergence study has been carried out for the flat composite panel in order to ascertain the best mesh size. Comparison of stress and strain values obtained from both analytical and finite element methods shows that they are in good agreement for flat panel. This further validates the best mesh sizes obtained from the convergence study. This similar mesh sizes are further considered for flat panel with circular and elliptical cut-outs with some mesh refinements around the cut-out regions. Failure load of the flat composite laminate (without cut-out) is determined using four different failure criteria such as maximum stress, maximum strain, Tsai-Hill and Tsai-Wu criteria. The predicted values are compared with experimental results. It is found that the most appropriate theory is Tsai-Wu failure criterion, since the predicted value based on this theory is very closure to experimental failure loads. This theory is used further for predicting the failure loads of composite laminates with cut-outs. The average value of stresses in each lamina has been used for determining the failure indices of the lamina for such cases. The results are compared with experimental failure loads available in the literature. The comparison shows that they are in very good agreement. Tsai-Wu failure criterion best predicts the failure load of a composite laminate with and without cut-outs.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Color Based Authentication Scheme for Publically Disclosable EntitiesIJERA Editor
Traditional password authentication system are not strong enough to cope up with the current age of cyber-crime. It’s high time that new password authentication schemes are explored and studied. This paper aims to provide an authentication system based on color recognition which would provide a way to encrypt both the username and password. The Color based authentication system would provide an efficient way to encrypt account details for sensitive applications like defense and banking.
Modeling the transport of charge carriers in the active devices diode submicr...IJERA Editor
A Monte Carlo simulation program was developed to simulate the movement of electrons in a submicron GaInP diode three dimensional (3D) with 0.1 microns-long active layer. The algorithm couples a standard Monte Carlo particle simulator for the Boltzmann equation with a 3D Poisson solver. Thus a series of hits for a specific MC submicron diode (GaInP), with an active layer (n = 2x1015cm-3) of length 0.1μm surrounded by two regions doped with n = 5x1017cm-3, are presented. The lattice temperature is 300K and the anode voltage Va is 1V. The analysis also showed that the average drift velocity to the electrons in the channel is about 5x106 cm/sec
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Cooling Of Power Converters by Natural ConvectionIJERA Editor
This paper discusses the numerical analysis of the effect of a discontinuous heat flux on heat transfer by natural convection along a vertical flat plate or in a rectangular channel. The objective of this study is to determine the effect of a discrete distribution of the heat flux on the cooling of twelve resistors, which represent electronic components, that are mounted on an aluminium vertical plate. The results of the simulations show that the distribution of the heat flux significantly influences the heat transfer.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
In this paper, a novel architecture of RNS based 1D Lifting Integer Wavelet Transform (IWT) has been introduced. Advantage of Residue Number System (RNS) based Lifting Scheme over RNS based Filter Bank and non-binary IWT has been discussed. The performance of traditional predicts and updates stage of binary Lifting Scheme (LS) for Discrete Wavelet Transform (DWT) generates huge carry propagation
delay, power and complexity. As a result non binary number system is becoming popular in the field of Digital Signal Processing (DSP) due to its efficient performance. In this paper also a new fixed number ROM based RNS division circuit has been proposed. The proposed architecture has been validated on Xilinx Vertex5 FPGA platform and the corresponding result and reports are shown in here.
Concurrent Ternary Galois-based Computation using Nano-apex Multiplexing Nibs...VLSICS Design
Novel realizations of concurrent computations utilizing three-dimensional lattice networks and their corresponding carbon-based field emission controlled switching is introduced in this article. The formalistic ternary nano-based implementation utilizes recent findings in field emission and nano applications which include carbon-based nanotubes and nanotips for three-valued lattice computing via field-emission methods. The presented work implements multi-valued Galois functions by utilizing concurrent nano-based lattice systems, which use two-to-one controlled switching via carbon-based field emission devices by using nano-apex carbon fibers and carbon nanotubes that were presented in the first part of the article. The introduced computational extension utilizing many-to-one carbon field-emission devices will be further utilized in implementing congestion-free architectures within the third part of the article. The emerging nano-based technologies form important directions in low-power compact-size regular lattice realizations, in which carbon-based devices switch less-costly and more-reliably using much less power than silicon-based devices. Applications include low-power design of VLSI circuits for signal processing and control of autonomous robots.
VLSI IMPLEMENTATION OF AREA EFFICIENT 2-PARALLEL FIR DIGITAL FILTERVLSICS Design
This paper aims to implement an area efficient 2-parallel FIR digital filter. Xilinx 14.2 is used for synthesis and simulation. Parallel filters are designed by using VHDL. Comparison among primary 2–parallel FIR digital filter and area efficient 2-parallel FIR digital filter has been done. Since adders are less weight in
term of silicon area, compare to multipliers. Therefore multipliers are replaced with adders for reducing area and speed of the filter. 2-parallel FIR filter is used in digital signal processing (DSP) application.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Low Power Adaptive FIR Filter Based on Distributed ArithmeticIJERA Editor
This paper aims at implementation of a low power adaptive FIR filter based on distributed arithmetic (DA) with
low power, high throughput, and low area. Least Mean Square (LMS) Algorithm is used to update the weight
and decrease the mean square error between the current filter output and the desired response. The pipelined
Distributed Arithmetic table reduces switching activity and hence it reduces power. The power consumption is
reduced by keeping bit-clock used in carry-save accumulation much faster than clock of rest of the operations.
We have implemented it in Quartus II and found that there is a reduction in the total power and the core dynamic
power by 31.31% and 100.24% respectively when compared with the architecture without DA table
Bandpass Filter in S-Band by D.C.Vaghela,LJIET,Ahmedabad,Gujarat.Dipak Vaghela
This paper is to design bandpass filter suitable with center at 2.5 GHz. This application is in the S band range at
2.5 GHz center frequency currently being used for Indian Regional Navigation Satellite System (IRNSS) receiver. The filter
covers the centre frequency 2.5 GHz and the bandwidth is 80 MHz. This project was initiated with theoretical understanding
of various types of filter and their applications. And suitable type was selected. It functions to pass through the desired
frequencies within the range and block unwanted frequencies. In addition, filters are also needed to remove out harmonics
that are present in the communication system. It was design and simulated using ADS (Advanced Design System) software
Design of an Adaptive Hearing Aid Algorithm using Booth-Wallace Tree MultiplierWaqas Tariq
The paper presents FPGA implementation of a spectral sharpening process suitable for speech enhancement and noise reduction algorithms for digital hearing aids. Booth and Booth Wallace multiplier is used for implementing digital signal processing algorithms in hearing aids. VHDL simulation results confirm that Booth Wallace multiplier is hardware efficient and performs faster than Booth’s multiplier. Booth Wallace multiplier consumes 40% less power compared to Booth multiplier. A novel digital hearing aid using spectral sharpening filter employing booth Wallace multiplier is proposed. The results reveal that the hardware requirement for implementing hearing aid using Booth Wallace multiplier is less when compared with that of a booth multiplier. Furthermore it is also demonstrated that digital hearing aid using Booth Wallace multiplier consumes less power and performs better in terms of speed.
Channel Equalization of WCDMA Downlink System Using Finite Length MMSE-DFEIOSR Journals
Abstract: The performance of WCDMA system deteriorates in the presence of multipath fading environment. Fading destroys the orthogonality and is responsible for multiple access interference (MAI). Though conventional rake receiver provides reasonable performance in the WCDMA downlink system due to path diversity, but it does not restores the orthogonality. Linear equalizer restores orthogonality and suppresses MAI, but it is not efficient, since its performance depends on the spectral characteristics of the channel. To overcome this, Minimum Mean Square Error- Decision Feedback Equalizer (MMSE-DFE) with a linear, anticausal feedforward filter, causal feedback filter and simple detector is proposed in this paper. The filter taps of finite length DFE is derived using the cholesky factorization theory, capable of suppressing noise, Intersymbol Interference (ISI) and MAI. This paper describes the WCDMA downlink system using finite length MMSE-DFE and takes into consideration the effects of interference which includes additive white gaussian noise, multipath fading, ISI and MAI. Furthermore, the performance is compared with conventional rake receiver and MMSE and the simulation results are shown. Keywords – MMSE, MMSE-DFE, rake receiver, WCDMA
Channel Equalization of WCDMA Downlink System Using Finite Length MMSE-DFEIOSR Journals
The performance of WCDMA system deteriorates in the presence of multipath fading environment.
Fading destroys the orthogonality and is responsible for multiple access interference (MAI). Though
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Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
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High Speed Memory Efficient Multiplier-less 1-D 9/7 Wavelet Filters Based NEDA Technique
1. Akanksha Yadav Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11(Version - 6), November 2014, pp.37-41
www.ijera.com 37 | P a g e
High Speed Memory Efficient Multiplier-less 1-D 9/7 Wavelet Filters Based NEDA Technique Akanksha Yadav1, Anushree2
Hindustan College Of Science & Technology Farah Mathura (India) ABSTRACT— Conventional distributed arithmetic (DA) is popular in field programmable gate array (FPGA) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, we describe high speed area efficient 1-D discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA) Technique. Being area efficient architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. This architecture supports any size of image pixel value and any level of decomposition. The parallel structure has 100% hardware utilization efficiency.
Keywords: - 1-D Discrete Wavelet Transform (DWT), NEDA, Low Pass Filter, High Pass Filter, Xilinx Simulation.
I. INTRODUCTION
The well-known image coding standards, namely, MPEG-4 and JPEG2000 have adopted 1-D DWT as the transform coder due to its remarkable advantages over the other transforms. For lossy and lossless compression, Daubechies 9/7 orthogonal filter is used as the default wavelet filter in JPEG 2000. Efficient implementation of 1-D DWT using 9/7 filters in resource-constrained hand-held devices with capability for real-time processing of the computation-intensive multimedia applications is, therefore, a necessary challenge. Multiplier-less hardware implementation approach provides a kind of solution to this problem due to its scope for lower hardware-complexity and higher throughput of computation. Several parallel and pipeline systems that meet the computational requirements of the discrete wavelet transform have been proposed. Some of them need multiprocessor to implement it and the system is complex, time consuming, and costly [1]. The Field programmable gate array (FPGA) provides us a new way to digital signal processing [2]. Several designs have been proposed for the multiplier, multiplier-less implementation of 1-D DWT based on the principle of multiplier based design (MBD) distributed arithmetic (DA) canonic signed digit (CSD), [1]–[3]. The structure of distributes the bits of the fixed coefficients instead of the bits of input samples. Consequently, the adder- complexity of the structure of depends on the DA- matrix of the fixed coefficients [2]. Canonic signed digit (CSD) are popular for representing a number with fewest number of non- zero digit. The CSD representation of a number
contains the minimum possible number of nonzero bits, thus the name canonic. The CSD representation of a number is unique and CSD numbers cover the range (-4/3, 4/3), out of which the value in the range {-1, 1} are of greatest interest. Martina et al [5] have approximated the 9/7 filter coefficients and performance of a hardware implementation of the 9/7 filter bank depends on the accuracy of coefficients representation. By that approach, they have significantly reduced the adder- complexity of the 9/7 DWT. Gourav et al [7] have suggested an LUT-less DA-based design for the implementation of 1-D DWT. They have eliminated the ROM cells required by the DA-based structures at the cost of additional adders and multiplexors. Some of them need Rom to implement it and the system is complex, time consuming, and costly [4] The adder-complexity of this structure is significantly higher than the other multiplier-less structures. In this paper, we have proposed an efficient scheme to derive NEDA-based bit-parallel structures, for low- hardware and high-speed computation DWT using 9/7 filters [4]. The remainder of the paper is organized as follows: New efficient distributed arithmetic based computation of 1-D DWT using 9/7 filter is presented in Section II. The proposed structures are presented in Section III. Hardware and time complexity of the proposed structures are discussed and compared with the existing structures in Section IV. Conclusion is presented in Section V.
II. NEW EFFICIENT DISTRIBUTED ARITHMETRIC (NEDA) Let us consider the following sum of products [4]:
RESEARCH ARTICLE OPEN ACCESS
2. Akanksha Yadav Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11(Version - 6), November 2014, pp.37-41
www.ijera.com 38 | P a g e
k
L
k
k Y X R 1
(1)
Where k X are fixed coefficients and they k Y are the
input data words. Equation (1) can be expressed in
the form of a matrix product as:
L
L
Y
Y
Y
R X X X
.
... 2
1
1 2
(2)
Both k X and k Y are in two’s complement format.
The two’s complement representation of k X may be
expressed as
1
2 2
M
i N
i i
k
M M
k k X X X (3)
Where i
k X 0 or 1, and i N, N+1… M
and
M
k X is the sign bit and
N
k X is the least significant
bit (LSB).
Equation (3) can be expressed in matrix form as:
M
k
N
k
N
k
N N M
k
X
X
X
X
.
2 2 ... 2
1
1
(4)
Similarly k Y can be represented in two’s
complemented format as:
1
2 2
X
i W
i i
k
X X
k k Y Y Y (5)
Where i
k Y 0 or 1, and i W, W+1, …,X
and
M
k Y is the sign bit and
N
k Y is the least significant
bit (LSB).
Now on combining equations (1) and (3), we get-
1
( .2 ) ( .2 )
M
i N
M M i i R R R (6)
Where
L
k
k
i
k
i R X Y
1
, i N, N+1… M
III. PROPOSED ARCHITECTURE
In this paper, we have proposed a high speed
area efficient multiplier-less 1-D 9/7 wavelet filters
based NEDA technique. 9/7 wavelet filters
coefficient i.e. 9 low-pass and 7 high-pass wavelet
filters coefficient are given in table1. We multiply the
filter coefficients by 128 for simplification. The
mathematical calculation for 1-D high pass filter
output is explained by an example.
Table 1: Show high-pass and low-pass wavelet filters
coefficient.
Wavelet filters
coefficients
Multiplied
by 128
8 bit binary
representation
with 2’s
complement
of negative no.
0 h 0.60294901823 77 01001101
1 h 0.26686441184 34 00100010
2 h -0.07822326652 -10 11110110
3 h -0.01686411844 -2 11111110
4 h 0.026748757410 3 00000011
0 g 0.55754352622 71 01000111
1 g -0.29563588155 -38 01011010
2 g -0.02877176311 -4 11111100
3 g 0.045635881557 6 00000110
Where 0 h , 1 h , 2 h , 3 h , 4 h are the Low pass filter
coefficients and 0 g , 1 g , 2 g , 3 g are the High pass
filter coefficients.
If we take the high pass coefficients 0 g , 1 g , 2 g and
3 g multiply by 1 r , 2 r , 3 r and 4 r then we get the High
pass output H Y of the 9/7 filter as [6]:
4
3
2
1
0 1 2 3
r
r
r
r
Y g g g g H (7)
Where
( ) ( 6) 1 r Y n Y n
( 1) ( 5) 2 r Y n Y n
( 2) ( 4) 3 r Y n Y n
( 3) 4 r Y n
Let 1 r =1, 2 r =2, 3 r =3, 4 r =4 then
3. Akanksha Yadav Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11(Version - 6), November 2014, pp.37-41
www.ijera.com 39 | P a g e
7
4
3
2
1
71 38 4 6
H Y
(8)
Now if we implement this with NEDA then
4
3
2
1
01000111 11011010 11111100 00000110
r
r
r
r
YH
(9)
Now we can make the DA matrix by the filter
coefficients as
0
0
0
1
1
1
1
1
0
0
1
0
0 1 1 0
0 1 1 0
1 0 1 1
1 1 0 1
1 0 0 0
k B
(10)
2 3
1 2 3
3
2 3
2 3
1 3 4
1 2 4
1
4
3
2
1
0
0
0
1
1
1
1
1
0
0
1
0
0 1 1 0
0 1 1 0
1 0 1 1
1 1 0 1
1 0 0 0
r r
r r r
r
r r
r r
r r r
r r r
r
r
r
r
r
YH
(11)
In Figure 2, apply NEDA techniques step-1 all the
input converts’ binary number, Step-2 all the binary
input applied to sign extension, after than all the sign
extension input applied to a adder array so,
00001 1 P , 00111 2 P
01000 3 P , 00101 4 P
00101 5 P , 00011 6 P
YL
Y(n)
YH
NEDA Technique
NEDA Technique
Y(n-1) Y(n-2) Y(n-3) Y(n-4) Y(n-5) Y(n-6) Y(n-7) Y(n-8)
A
A
A
A
A
A
A
Figure 1: Proposed Multiplier-less 9/7 Wavelet filter using NEDA Technique
4. Akanksha Yadav Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11(Version - 6), November 2014, pp.37-41
www.ijera.com 40 | P a g e
,
00110 7 P , 00101 8 P
The entire adder array input applied to MUX so, the
entire adder array input m(1) right shift 1-bit so
MUX (1) = 0’0111 =Yp (0)
MUX (1) add MUX (2) = YP (1)
= 0’00001
= 0 0111
+ 0 01111
Output of the YP (1) again right shift 1-bit and adds
MUX (3) so
= 0’001111
= 0 1000
+ 0 101111
YP (1) + MUX (3) = YP (2)
Output of the YP (2) again right shift 1-bit and adds
MUX (4) so
= 0’0101111
= 0 0101
+ 0 1010111
YP (2) + MUX (4) = YP (3)
Output of the YP (3) again right shift 1-bit and adds
MUX (5)
so
= 0’01010111
= 0 0101
+ 0 10100111
YP (3) + MUX (5) = YP (4)
Output of the YP (4) again right shift 1-bit and adds
MUX (6)
so
= 0’010100111
= 0 0011
+ 0 100000111
YP (4) + MUX (6) = YP (5)
Output of the YP (5) again right shift 1-bit and adds
MUX (7)
so
= 0’010000111
= 0 0110
+ 0 1010000111
YP (5) + MUX (7) = YP (6)
Output of the YP (6) again right shift 1-bit and adds
MUX (8)
so
= 0’01010000111
RIGHT
SHIFT
1 BIT
MUX
S
I
G
N
E
X
T
E
T
I
O
N
P8
“1”
P1
P2
P3
P4
P5
P6
P7
r1
r2
r3
r4
Figure 2: Mathematical calculation of the NEDA Technique of the Low-pass Wavelet Filter Output