This document summarizes a transition from a traditional DFT and test generation approach to a 1687-based approach for a mixed-signal IC. The traditional flow uses multiple test buses and handcrafted analog tests, requiring months of effort. The 1687 approach aims to streamline testing by accessing analog blocks via scan chains, potentially reducing test time and increasing coverage. While specification coverage would remain the same, defect coverage may increase. Future benefits include reusable test libraries and improved quality for designs using shared IP blocks. A proof of concept simulation showed increased analog defect coverage through improved 1687 access.

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Full Service Foundry
An example transition to
1687-based mixed-signal DFT
Peter Sarson
February 16, 2015

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Block Diagram

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IP Block Data
IP BLOCK Number of Transistors Number of Tests Frequencies Tested
CLK
recovery
500 15 1, 32, 256 Mb/s
CC TX 50 10 1, 32, 256 Mb/s
CC RX 200 10 1, 32, 256 Mb/s
PLL 1 500 10 1, 32 MHz
PLL 2 500 10 256 MHz
RC Oscillator 40 4 100 kHz
XTAL 50 4 24 MHz

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Our Typical DFT and Test Generation
2 Test buses: 1 serial digital, 1 handcrafted analog
Multiple resources needed on CCP, CCN, TESTBUS2 to test majority of
functions
• Requires many relays, which add parasitics
 Reduces test accuracy
 Less reliable
 May increase test time
Design IP reused, but tests not reusable
90% of analog section can be tested via test bus
Entire test handcrafted using SPI commands and ATE resources
• Time to write and debug analog test code: 2-3 months
DAC accessed serially and possibly limited by shift-in time
• Test time limitations

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Our Typical Test Coverage
100% of datasheet parameters tested
• Temperature guardbands
• No automated verification of coverage
Defect-based coverage unknown (likely lower)
• Some defects might not affect datasheet specs – reliability?

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1687 Modifications and Benefits
TESTBUS1 (digital), TESTBUS2 (analog)
• Control analog bus via scan, instead of via digital bus – less area
 May be able to access additional nodes to increase coverage
DAC test
• Stream data serially from scan – may decrease test time 5%
No handcrafted digital SPI patterns
• All test blocks accessed by scan, generated from WGL files
• Possible 2 week saving in writing/debug of setups
One test pin instead of three
• Hardware more reliable; higher performance due to fewer wires
• May decrease test time 5% test time by avoiding relay switching to high
performance resources

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Drawbacks
Specification coverage same as original test plan
• Might increase defect coverage, but not yet proven

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Future Benefits
RC Oscillator, PLL, CLK recovery circuit, proximity detection
designed-for-test differently each time
• 1687 ICL and PDL allow generation of reusable hardware and tests
• Allows creation of plug-and-play (and test) library IP blocks
• Will reduce DFT and test development time of future ICs
Any production test escapes will lead to fix to IP block’s test
• Improves quality of future designs using that block

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Proof of Concept – Simulation Only
Old flow
• Structural test not possible
• Analog Defect Coverage calculation using Test Benches is xyz %
New flow
• Show where test coverage is missing and how it was increased using 1687
access to abc %
• Real silicon wont be modified at the moment

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