The document discusses the design and layout processes of application-specific integrated circuits (ASICs), including various types such as standard cell-based, gate arrays, and programmable logic devices like FPGAs. It covers key concepts like floorplanning, channel routing, and the flow of ASIC design, as well as verification methods like directed testing and their advantages and disadvantages. The content emphasizes measurement of delays in design and the incremental approach to ensure design correctness.

1. An IC with PGA Package

2. TYPES OF ASIC

3. Standard Cell Based ASICS

4. Layout of a Standard Cell

5. Routing The Cell-Base IC

6. Gate Array Based ASICs
1.Channeled Gate-array die

7. Channel less gate array die

8. Structured gate array die

9. Programmable Logic Devices

10. Field Programmable Gate Array

11. Design Flow

12. DATA PATH LOGIC CELLS
INTRODUCTION

13. DATAPATH ADDER (RCA)

14. DATAPATH ELEMENTS
SYMBOLS FOR DATA ADDER

15. ADDERS
CONVENTIONAL RCA IN TERMS OF GENERATE ,PROPAGATE
AND KILL SIGNALS

16. LOGIC DIAGRAM OF CONVENTIONAL RCA WITH REDUCTION IN THE DELAY BY USING THE GO-FASTER BUBBLE PAIRS

18. CARRY SAVE ADDER
CONCEPT OF CARRY SAVE ADDER

19. EQUATIONS AND CONCEPT OF CSA

20. CSA SYMBOL,DATAPATH ,PIPELINED STRUCTURE

21. CARRY-BYPASS & CARRY-SKIP ADDERS: CONCEPT,EQUATIONS

22. LOGIC DIAGRAM

24. LOOK-AHEAD CARRY ADDER

25. CARRY - LOOKAHEAD ADDER

26. BRENT-KUNG CLA

27. Carry Select Adder

29. ASIC DESIGN FLOW

30. FloorPlanning
• The input to floorplanning is a netlist that describes the circuit blocks
and the logic cells within them and their interconnections.
• We should now set aside spaces for interconnections called the
channel.

31. Floor Planning ---- An Example

33. The Floorplanning Problem formulation

36. Goals & Objectives Of floorplanning

37. Floorplanning inputs

40. Measurement Of Delay In Floorplanning

41. Measurement Of Delay In Floorplanning

42. Measurement Of Delay In Floorplanning

43. Measurement Of Delay In Floorplanning

44. Measurement Of Worst Case Interconnect Delay

45. Example Of Wire Load Table

47. Floorplanning Tools

49. Floorplanning Tools

50. Congestion Analysis

51. Channel Definition

52. Channel Routing Order Using a slicing tree

55. Cyclic Constraints

58. I/O and Power Planning

61. Power Planning

62. Placement

86. Force Equation

117. Directed Testing
• Traditionally Direct Tests were used when we had the task of verifying the correctness of
the design.
• We first look at the hardware specifications.
• We then write a verification plan with a list of tests
• Each of these verification tests concentrate on a list of related features
• We then write the stimulus vectors that excersize these features in the DUT
• We then simulate the DUT with these vectors and manually review th eresulting log files
and waveforms to make sure the design does the expected.
• Finally once the test works correctly we verify it wrt the verification plan and move on to
the next test.
• This is incremental approach makes a steady progress.
• It also produces immediate results as little infrastructure is needed to create the
stimulus vector.
• Given ample time and staffing, directed testing is sufficient to verify many designs.

119. Disadvantages of Directed Testing:
This approach cannot be used when we don’t have the necessary time or resources to carry out directed testing.
When the Design complexity doubles,it takes twice as long to complete or requires twice as many people to implement it.
We cannot use it when we want to find the bugs faster with 100% coverage

120. Methodology Basics