3DIC & 2,5D TSV Interconnect trends 2014 Kinsale Presentation Yole Developpement

FROM TECHNOLOGIES TO MARKET
1
YOLE DEVELOPPEMENT
3DIC & 2,5D TSV Interconnect
Trends
COLLABORATION
INNOVATION
NEW PERSPECTIVES
3DIC 2014 – December 1st Kinsale

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 Yole Introduction
 Industry trends & Market Drivers
 TSV Applications
 Patent Status in 3D Technology
 Conclusions
Presentation Outline
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From TECHNOLOGIES to MARKET
Copyright @ Yole Developpement SA.. All rights reserved

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Our Global Presence
Yole Inc.
Yole
Europe
30%
40%
30% Yole Korea
Yole KK Japan
Offices in Lyon (HQ),
Nantes, Nice & Paris

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MEDIA
News feed / Webcasts
Technology Magazines
www.yole.fr
FINANCE
M&A / Valuation / Due Diligence /
Technology brokerage
www.yolefinance.fr
www.i-micronews.com
REPORTS
Market & technology
Patent Investigation
Reverse costing
CONSULTING
Market research
Technology & Strategy
Patent Investigation
Reverse costing
WORKSHOPS
Focused seminars
Yole Group Activities
5%

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The company is involved in the following areas:
 30 full time global analysts with technical, marketing and management
background
 35000 interviews per year
Field of Research
Advanced Packaging Photovoltaics LED & Compound Semi Power Electronics
Microfluidics & Bio Tech MEMS & Sensors Semiconductor Manufacturing: Equipment & Materials
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• Yole’s research is focused on:
 Applicative Packaging: moving to high performance, low cost, application driven
packaging techniques
 Advanced Packaging: moving to high performance, low cost, collective wafer
level packaging techniques
Camera Level Packaging Power Module Packaging MEMS Packaging LED Packaging
Lead-Frame LCC Wirebonding BGA WLCSP 3D WLP SIP 3DIC
QFN PGA Flip Chip POP FOWLP 2.5D Interposer
Semiconductor Packaging

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Advanced Packaging
3D IC Market
YOLE DEVELOPPEMENT

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Silicon / Interconnection trend
500
020406080100
Number
I/O per
cm²
20.000
10.000
1500
CMOS90 CMOS45
CMOS28
CMOS16
CMOS65
FinFET
Technology Node
CMOS [nm]
Scaling of Transistor
Nodes => I/Os Density
Increase

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The Evolution of Semiconductor Packaging
A bridging technology between ICs and PCBs
Feature sizes CMOS
transistors: 28nm
Feature sizes of PCBs
1970
through
hole
technology
1980
Surface mount
devices
DevelopmentinCMOSprocessingcapabilities
DevelopmentinPCBprocessingcapabilities
1990
CSPs/BGAs
SiPs
2000
WLCSP
more SiPs
Flip Chip BGA
PoP
2010
3DIC
TSV
Fan-out WLCSP
Cu pillars
Silicon interposers

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The Evolution of Semiconductor Packaging
A bridging technology between ICs and PCBs
Feature sizes CMOS
transistors: 28nm
Feature sizes of PCBs
1970
through
hole
technology
1980
Surface mount
devices
DevelopmentinCMOSprocessingcapabilities
DevelopmentinPCBprocessingcapabilities
1990
CSPs/BGAs
SiPs
2000
WLCSP
more SiPs
Flip Chip BGA
PoP
2010
3DIC
TSV
Fan-out WLCSP
Cu pillars
Silicon interposers
….across several markets
Mobile:
High-end Multimedia
Smart-phones / PMP
High-density
Solid State
Storage & µ-Cards
Computing: Notebooks / MID
‘connectivity’ devices
Consumer:
Gaming / Graphic
application engines
Industrial: HPC/
Network,
Servers
Consumer: High-performance
Digital Video
Wireless:
Connectivity /
Network Center
Medical Military & AerospaceTransportation:
Automotive,
Trains,
HEV/EV
Renewable Energy:
Photovoltains, Wind
Turbines…
Telecom: Power
Supplies…
Industrial

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Advanced Packaging Platforms
Wafer-Level
Electrical Redistribution
Flip-chip & Wafer-Level
Stacking / Integration
WL CSP
‘Fan-in’
FOWLP
‘Fan-out’
2.5D
Interposer
FC wafer
bumping
on BGA
3D IC &
TSV
Embedded die
in PCB /
laminate
Wafer-Level
Interface / Encapsulation
3D WLP
For MEMS & sensors
(also called 3D SiP)
LED & Sensors
WLOptics
2.5D Interposer & 3DIC activities & trends
Wafer-level-packages have emerged in many different varieties

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3D IC Market Drivers
Unchanged !
“More than Moore”
Heterogeneous
integration
Co-integration of
RF+logic+memory + sensors in
a reduced space
Density
 Achieving the highest
capacity / volume ratio
Form
factor-
driven
Performance-
driven
3D IC
Optimum Market
Access Conditions
Wide IO
memory
CIS
DRAM
RF-SiP
Electrical performance
 Interconnect speed, bandwidth and
reduced power consumption
3D vs. “More Moore”
 Can 3D be cheaper
than going to the next
lithography node?
Flash
Cost-driven
Partitioning
Sensors
CPU
GPU
Power.
Analog.
FPGA

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3D Stacking Packages
Wire bonded
packages
Package on/in Package
(POP/PIP)
iPhone 5 POP Package
John Lau – “The future of Interposers”
in Chip Scale Review, May-June 2014
Continue to being produced
today (still the main
interconnect packaging
technology)
2.5D Interposer / 3D IC
Xillinx Virtex FPGA
Hybrid Memory Cube

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Comparison of 2D vs. 3D Packages
Wire bonded
packages
Package on/in
Package (POP/PIP)
Memory Capacity
2.5D Interposer /
3D IC
Time
2D SOC
Memory Bandwidth
Power Consumption
Form Factor
Cost
- ++ ++ ++
++ + 0 +++
++ + 0 +++
0 ++ + +++
--- - ++ ??
Phil Garrou – Handbook of 3D Integration, vol. 3, June 2014

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YOLE DEVELOPPEMENT
3D TSV Applications

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Photonics
Others
(Power,
LED, RF…)
Memory
TSV in a nutshell
MEMS
Logic
CMOS
Image
Sensors
Through
Silicon
Via
TSV

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2014 2015 2016 2017 2018 2019
WSPY
300 eq
MEMS
Memory
Photonic
CIS
MEMS
HBM
HMC
Photonic
interposer
FPGA
SK
Hynix
Micron
Xilinx
Altera
<2013
CIS
FPGA
Logic on Logic
2014-2019 TSV Wafer Starts Breakdown by Application
HMC
HBM
Wide I/O
DDR4

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Photonics
Others
(Power,
LED, RF…)
Memory
TSV in a nutshell
Through
Silicon
Via
TSV
MEMS
Logic
CMOS
Image
Sensors

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CMOS Image Sensor Evolution
FSI BSI 3D Stacked BSI
20122008
TSV Hole to replace shell
case approach
Wafer Level Packaging
Interconnection
Trench TSV
BEOL Interconnection
TSV BEOL and DSP
Interconnection
« Real 3D »
TSVCross-sectionSEMTSVNeedsIntegrationScheme

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Iphone 5S Teardown - Camera Module
8Mp 1.5µm Stacked BSI CIS
BSI stacked CIS
from SONY
Teardown
Iphone 6 & 6+
now available!

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CIS – Cross Section TSV
TSVs are organized in pair one connecting pixel
array circuit and one connecting logic circuit
Cu

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Comparison with Previous 8Mp Sensors
Significant Improvement brought by Sony
Phone Ref. (Year)
CIS
Manufacturer
Resolution/
Techno
Pixel size
Pixel Array
Area
CIS Area
Dies per wafer
(12-inch)
Motorola Razor (2011) Omnivision 8Mp/BSI 1.4µm 16mm² 43mm² 1,500
Apple iPhone 4S (2011) Sony 8Mp/BSI 1.4µm 16mm² 35.4mm² 1,816
Samsung Galaxy SII (2011) Samsung 8Mp/BSI 1.4µm 16mm² 34.2mm² 1,884
Apple iPhone 5S (2013) Sony 8Mp/BSI 1.5µm 18mm² 28.5mm² 2,268
Courtesy System Plus Consulting
~50% ~60% ~60% ~90%
Increase of pixel area

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Current BSI
Stacked BSI
+ logic – TSV
stacking
Hybrid Bond
Stacking
3 Wafer
stacking?
3D Stacked CIS
Roadmap
Carrier wafer
Sensor + logic
Sensor only
Logic
SOURCE OMNIVISION

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Photonics
Others
(Power,
LED, RF…)
Memory
TSV in a nutshell
MEMS
Logic
CMOS
Image
Sensors
Through
Silicon
Via
TSV
MEMS

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Different TSV architectures (Accelerometer)
2013 20142012
Cu TSV in ASIC
Via Middle 10:100 AR 10
Temporary Bonding)
W TSV-like 3:30 AR 10
connecting MEMS to IC metal
layers (fusion bonding)
Integrationscheme-Crosssection
TSV Trench
To connect with wirebonding
from MEMS to ASIC

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3-Axis Accelerometer
Package size comparison
Surface: SST= 4mm²
Package thickness: TST= 1mm
Surface: SmCube= 4mm²
Package thickness: TmCube= 0.9mm
Surface: SBosch= 1.8mm²
Package thickness: TBosch= 0.8mm
Bosch achieved 55% in package
reduction and has the thinner
package (0.8mm)
SST = SmCube > SBosch
TST > TmCube > TBosch

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Photonics
Others
(Power,
LED, RF…)
Memory
TSV in a nutshell
Through
Silicon
Via
TSV
MEMS
CMOS
Image
Sensors
Logic

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FPGA using 2.5D Integration
Xilinx Interposer cross section (working with UMC and SPIL)
 FPGA on interposer
introduced in 2011
 Since 2013 Xilinx and
TSMC reach volume
production on 28nm
CoWoS™ based
 Next device will use
20nm logic dies.

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Market Evolution
100µm 10µm 1µm 100nm 10nm
PCB Design Rule Wafer Design Rule
Organic Substrate
GAP!
Silicon/Glass Interposer
~8-> 5µm
More functionalities and advanced technologies nodes
OSAT /
Wafer foundries
Substrate
Manufacturers
High Cost
Lower cost than
Si/Glass Interposer
Opportunity!

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Status of Substrate Processing Capabilities
Ibiden FCCSP
140um bump pitch
15/15um L/S
4/4
L/S
8/8 10/10 12/126/62/2 ……….15/25
100µm
50µm
Bump
Pitch
150µm
Current Production
Capabilities
Bump Pitch: 130um & above
L/S
12/12 & above
Shinko (DLL)
130um bump pitch
14/14um (HVM)
In Development:
Aggressive developmental
roadmaps:
Bump pitch shrinking
L/S narrowing
• With core – substrates
• Core-less substrates

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Photonics
Others
(Power,
LED, RF…)
Memory
TSV in a nutshell
Through
Silicon
Via
TSV
MEMS
Logic
CMOS
Image
Sensors
Memory

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Memory Package Roadmap
New Packaging Technologies driven by the need of:
1. Wider bandwidth,
2. Faster speed,
3. Smaller/thinner packages
64GB
High Capacity
High SpeedThinner
128GB
256GB
512GB
40Mbps
200-400Mbps
800Mbps 1Gbps
1,4mm
1,2mm
1mm
0,6mm
PoP
TSV PoP
TSV RDL

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Markets Demand: High Performance, Lower Power Consumption
High Performance Computing (HPC)
•Game Consoles
•Graphics
•Microprocessors
Networking, Wired Applications
•Servers
•Storage
•Digital TV Networking
Consumer, Wireless, Mobile Computing
•Smartphones
•Tablets
•Portable Consumer
High Capacity
Low Power
High Bandwidth
High capacity
High Bandwidth
Low Power

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Memory
A brief Overview of Announced Products

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Market SmartPhone Tablet Networking
Servers
High Performance
computing (HPC)
Graphics
Memory Type
Wide I/Ox
Widecon
Wide I/Ox or
LPDDRx
HMC/HBM –
DDR4 3DS
DiRAM4
HBM
Players
Memory Types by Application

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YOLE DEVELOPPEMENT
Patents Status

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Time Evolution of Patent Publications
All Patents
1 1 1 2 3 3 1 6 4 3
12
3 10 11 16 8
17 22
13
31 33
70
119
191
215
235
405
226
0
50
100
150
200
250
300
350
400
450
1970
1971
1972
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
NUMBEROFPATENTFAMILIES
1RST PUBLICATION YEAR OF EACH PATENT FAMILY
1000+ patent family published between 1971 and 2012
650+ new patent
families published
since 2013
• 1013 patent families were filed from 1969 to 2012
• 82% of patents were filed since 2006
• 260 organizations with patents
• 1700 inventors

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Countries & Applicants of New Patents
TSMC 99
IBM 51
SAMSUNG 51
INTEL 34
SK HYNIX 29
STATS CHIPPAC 25
ITRI 21
TI 18
QUALCOMM 16
ELPIDA 12
AMD 11
AMKOR 11
FREESCALE 11
GLOBALFOUNDRIES 11
MICRON 8
BROADCOM 6
UNIMICRON 4
ELPIDA MEMORY 15
SAMSUNG 9
HITACHI 4
IBM 4
INTEL 4
SUMITOMO 4
TSMC 47
ITRI 14
IBM 11
INTEL 10
R. INST. CHINA AEROSPACE SCI. TECH. 9
SAMSUNG 9
BEIJING UNIV. OF TECH. 7
GLOBALFOUNDRIES 7
TI 6
TSINGHUA UNIV. 6
FREESCALE SEMICONDUCTOR 5
INST. OF MICROELEC. (CHINESE ACA. OF SCI.) 5
NAT. CENTER FOR ADV. PACK. (NCAP) 5
SAMSUNG 51
SK HYNIX 42
TSMC 20
AMKOR 17
KAIST 10
INTEL 9
BROADCOM 4
TSMC 29
ITRI 22
INTEL 19
GLOBALFOUNDRIES 7
AMKOR 5
PTI 5
STATS CHIPPAC 5
BROADCOM 4
MICRON 4
SPIL 4
UNIMICRON 4
INTEL 30
CEA 5
IBM 4
TSMC 4
ELPIDA 3
BROADCOM 2
RAMBUS 2
Number of patent families
having at least a patent filed
in the country.
Europe (95)
USA (504)
WO (97)
Korea (170)
Japan (50)
Taiwan (151)China (204)

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Main Patent Applicant Ranking
All Patents – Status 2014
62
76
76
57
72
52
27
24
22
23
17
18
21
14
15
6
9
12
7
2
1
6
1
6
3
5
3
1
1
99
58
52
42
8
25
36
27
24
15
18
17
5
10
9
11
7
4
8
11
11
6
9
4
6
4
4
5
4
4
0 50 100 150 200
TSMC
SAMSUNG
IBM
SK HYNIX
MICRON
STATS CHIPPAC
INTEL
AMKOR
ITRI
ELPIDA MEMORY
TI
QUALCOMM
CEA
KAIST
POWERTECH TECHNOLOGY (PTI)
AMD
BEIJING UNIV. OF TECH.
HITACHI
TSINGHUA UNIV.
FREESCALE SEMICONDUCTOR
GLOBALFOUNDRIES
INST. OF MICROELECTRONICS (CHINESE ACA. OF SCI.)
RESEARCH INST. CHINA AEROSPACE SCI. TECH.
SPIL
BROADCOM
RAMBUS
XILINX
NAT. CENTER FOR ADV. PACK. (NCAP)
SUMITOMO BAKELITE
UNIMICRON TECHNOLOGY
NUMBER OF PATENT FAMILIES
IP Study 2013 New Patents

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YOLE DEVELOPPEMENT
Conclusions

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3D Stacking with TSVs is a Viable Option
 3DIC will be adopted for high-end applications
• No more doubts about that, since all key players have shown the
technology on their roadmaps and real samples have already
been shipped. 2015 will be the year for TSVs adoption.
 The question about 3D adoption still remaining is: How and when will
this really happen for the consumer market, where cost is so critical?
• Manufacturing costs require further reduction; equipment and
materials suppliers, in collaboration with major players, are
continuing their developments in this area to enable the industry
to bring 3DIC on the consumer market.
 The path is open for the heterogeneous integration of devices:
• MEMS are being integrated onto ASIC dies connected with TSVs
• Since node scaling is becoming more and more challenging and
costly, 3D stacking using TSVs is definitely going to be (and
already is) a viable option.

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Thank you!
Contact: buisson@yole.fr
YOLE DEVELOPPEMENT
COLLABORATION
INNOVATION
NEW PERSPECTIVES
For additional information visit our websites:
www.yole.fr & www.i-micronews.com
Online free registration to YOLE publications
Info extracted from 3DIC & 2.5D TSV Interconnect Report:

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 Technical comparison of new processes at
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 Yole Developpement consultants provide market analysis, technology
evaluation, and business plan along the entire value chain
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3DIC & 2,5D TSV Interconnect trends 2014 Kinsale Presentation Yole Developpement

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3DIC & 2,5D TSV Interconnect trends 2014 Kinsale Presentation Yole Developpement