The document discusses various logic families and memory concepts. It provides details on propagation delay, noise margin, TTL NAND gate, ECL logic family characteristics, MOS transistor advantages, CMOS inverter and NAND gate structure, SRAM and DRAM organization and operation, and comparisons between different types of ROM such as PROM, EPROM, and EEPROM.

1. LOGIC FAMILIES AND MEMORY
K.N.BALUPRITHVIRAJ
ASSISTANT PROFESSOR
DEPARTMENT OF EIE
KONGU ENGINEERING COLLEGE

2. UNIT-V
• Propagation Delay
The threshold voltage is defined as that voltage
at the input of a gate which causes a change in
the state of the output from one logic level to
the other. The average transition delay time tpd
expressed by
tpHL: delay time in going from logical 1 to
logical 0 state (HIGH to LOW)

3. Noise Margin
• When the digital circuits operate in noisy environment
the gates may malfunctions if the noise is beyond
certain limits.
• The noise immunity of a logic circuit refers to the
circuit’s ability to tolerate noise voltages at its inputs.
• A quantitative measure of noise immunity is called
noise margin.
• Unwanted spurious signals - noise margin.
• Voltages greater than VOH(min) are considered as a
logic 1 and voltages lower than VOL (max) are
considered as a logic 0.
• Voltages in the disallowed ranges should not appear at
a logic circuit output under normal conditions.

4. Noise Margin

5. Noise Margin
• The noise immunity of a logic circuit refers to the
circuit’s ability to tolerate noise without causing
spurious changes in the output voltage.
• Noise margin:
• VNH=VOH(min)-VIH(min)
• VNL=VIL(max)-VOL(max)
• High state noise margin is the difference between
the lowest possible high output and the minimum
input voltage required for a HIGH.
• Low state noise margin is the difference between
the largest possible low output and the maximum
input voltage for a low.

6. 2- input TTL NAND GATE

7. Transistor Transistor Logic (TTL)
• Dependence on transistors
• Most widely used bipolar digital IC family
• Operating at saturated mode
• Faster of the saturated logic families
• Merits-Good speed, low manufacturing cost, wide
range of circuits
• Demerits- High power consumption, moderate
package density, generating of noise spikes,
susceptibility to power transmit.

8. TTL
• Different families electrical characteristics- Delay
time, power consumption, switching speed, fan
out, fan in, noise margin.
• Standard TTL- 0V to 0.8V- logic 0, 2V to 5V –
logic 1, signals -0.8V to 2V range applied as input
on the corresponding response- indeterminate.
• Current Sink- Low state, Q4, Pull down transistor
• Current Source- High state, Q3, Pull up transistor

9. 3 INPUT TTL NAND GATE

10. Emitter Coupled Logic (ECL)

11. ECL- High frequency applications
• Current mode logic or Current Steering logic
• Faster of all logic families
• Non saturated logic(Emitter Follower mode),
Storage time delay- eliminated, speed- increases
• Current kept high and output impedence – low,
output stray capacitances quickly charged and
discharged.
• Limited voltage swing
• Uses of BJT, Coupled(joined) at their emitters
• Difficult to achieve good noise immunity
• Power consumption increases.
• Current drawn from supply- steady and do not
experience large switching transient.

12. MOS Transistor
• Simpler and inexpensive to fabricate
• Less power
• Better noise margin
• Greater supply voltage range
• Higher fan-out
• Less chip area
• Slower in operating speed and susceptible to static
charge damage.
• Propagation delay- MOS gates is large(50ns)-
higher output resistance

13. MOS Transistor
• Very small space- requires only one basic
element- NMOS or PMOS transistor
• Low power dissipation- suited for LSI,VLSI
and ULSI for applications such as memories,
calculator chips, large microprocessor etc.
• Operating speed- slower than TTL
• Greater package density-MOS ICs- high
reliability in the number of external
connections

14. MOS Transistor
• Two types of MOSFETs- Depletion type and
enhancement type.
• The MOSFET can be NMOS type and PMOS type.
• Modern MOSFET circuitry- constructed using NMOS
devices- operate about 3 times speed and twice the
package density of PMOS.
• CMOS-uses both P &N channel MOSFET- same circuit
• CMOS-greater complexity and the lowest package
density of all the MOS families.
• CMOS- higher speed and much lower power
dissipation.
• CMOS- Operating at high voltage- improved noise
margin.

15. CMOS Transistor
• Applications from general purpose logic to
microprocessors
• Useful for watches and calculators.
• CMOS- very high input resistance –draws zero current
from the driving gate and fan out is very high.
• Output resistance – small, so faster than NMOS.
• CMOS loses some of its advantages at high
frequencies.
• CMOS- battery power or battery backup power.
• CMOS slower than TTL

16. NMOSFET

17. PMOSFET

18. CMOS INVERTER

19. 2 INPUT CMOS NAND GATE

20. 2 INPUT CMOS NAND GATE

21. CMOS NOR GATE

22. CMOS NOR GATE

23. MEMORY ORGANIZATION AND
OPERATION

24. Memory organization
• Storing binary information or bits
• Each location identified by an address.
• Word- group of bits used to represent one
entity of information- one numerical value.
• Word size- the number of bits/bytes in a word.
• 8 bit-8 latches- Each latch- one bit of a word-
cell
• 2^10=1024 (1K), 2^11=2048 (2K)

25. ROM ORGANIZATION
• ROM is organized- 16 addresses, each of which stores
8 bits.
• Total capacity of ROM-128 bits
• The dark squares (fig.)represent stored 1 by means of
base connected transistor or gate connected MOSFET.
Light squares represent stored 0.
• 4 bit binary address applied to the address inputs,
corresponding ROW line becomes High.
• This high is connected to the Column line through the
transistor at each junction where 1 is stored.
• Column line stays LOW at each cell where 0 is stored
because of the terminating resistor.
• Column line form data output.
• Eight data bits stored in the selected ROW appear on
the output lines.

26. ROM ORGANIZATION

27. RAM and ROM
• ROM- cannot be written into.
• ROM-permanent storage of programs and data
• ROM-non-volatile
• RAM-read/write memory(RWM)-accessed for both
these kind of operations.
• RAM- semiconductor devices- all data will be lost if
power is removed or interrupted or turned off
• RAM-Volatile
• RAM- memory locations can be accessed directly and
immediately
• RAM-Temporary storage of programs and data

28. RAM
• CMOS RAM- use small amount of power in
the standby mode- powered from batteries
whenever the main power is interrupted.
• RAM- number of registers- storing a single
data word and having unique address.

29. RAM and ROM
• IC Memories- BJT and MOSFET
Technologies
• MOSFET- easily manufactured than BJT,
occupy less space and more dominant
• BJT- faster than MOSFET. Used in high speed
applications.

30. APPLICATIONS OF ROM
• Microcomputer program storage(Firmware)
• Bootstrap memory
• Data tables
• Data converters
• Character generators
• Function generator

31. TYPES OF MEMORIES

32. STATIC RAM(SRAM)
• Store data as long as power is applied to the chip
• Memory cells- flip flops – stay in a given state
indefinitely, provided that power to the circuit is
not interrupted.
• SRAM- both in BJT and MOSFET Technologies.
• Majority of applications use- NMOS or CMOS
RAMs
• BJT- advantage of speed
• CMOS- much greater capacities and lower power
consumption

33. SRAM

34. SRAM

35. SRAM
• Bipolar static memory cell- two multi emitter
transistors and two resistors
• NMOS static memory cell- four N channel
MOSFETs.
• CMOS Cell- two CMOS FETs
• SRAM- used in internal memory of a
computer.
• The memory chip interfaced to CPU have to be
fast enough to respond to the CPU read and
write commands

36. SRAM APPLICATIONS
• Microprocessor controlled instruments and
small memory capacity requirements.
• Digital Storage Oscilloscopes and Logic
Analyzers require very high speed memory.
• Computers- functions requiring maximum
speed such as video graphics.
• SRAM is thus used as cache memory and has
very fast access.

37. CHARACTERISTICS OF SRAM
• Long life
• No need to refresh
• Faster
• Used as cache memory
• Large size
• Expensive
• High power consumption

38. DYNAMIC RAM (DRAM)
• DRAM store data as charges on capacitors.
• The stored data will disappear because of
capacitance discharge.
• Necessary to periodically refresh the data to
replenish the stored charges.
• DRAM – only MOSFET Technology
• Very large number(high capacity) of memory
cells in the single circuit and low power
consumption.

39. DRAM

40. DRAM
• The single transistor cell- serve as a transmission
gate controlled by the address line.
• To read, the address line- high, turning on the
transmission gate and capacitor voltage appears
on the bit line.
• To write, the address line- high, the voltage on the
bit lines charges or discharges the capacitor
through the transmission gate.
• Every read operation is followed by write
operation.

41. DRAM
• Additional circuitry to implement the memory
refresh operation during the time intervals when
the memory was not accessed for read or write
operation.
• For small memories(<64K words)- integrated
RAM(iRAM) IC- refresh circuitry on same chip.
• For large memories(>64K)- uses LSI chips-
dynamic memory controllers- contain all of the
necessary logic for refreshing the DRAM chips
that make up the system. Reduce extra circuitry.

42. DRAM
• DRAM- four times the density of SRAM
• One fourth- same amount of memory.
• Cost per bit of DRAM-one fifth to one fourth
that of SRAM
• DRAM-lower power consumption- one sixth
to one half that of a SRAM
• Internal memory of personal computers is
DRAM.

43. CHARACTERISTICS OF DRAM
• Short data lifetime
• Needs to be refreshed continuously
• Slower as compared to SRAM
• Used as RAM
• Smaller in size
• Less expensive
• Less power consumption

44. TYPES OF ROM
• PROM(Programmable Read Only Memory)
• MROM(Mask Read Only Memory)
• EPROM(Electrically Programmable Read
Only Memory)
• EEPROM(Electrically Erasable Programmable
Read Only Memory)

45. PROM
• PROM has fixed AND array constructed as a decoder
and a programmable OR array.
• AND gates are programmed- provide the product
term of boolean functions, logically summed in each
OR gate.
• The data pattern is programmed electrically by the
user using a special circuit known as PROM
programmer.
• It can be programmed only once during its life time.
• Once programmed, the data cannot be altered.
• These are highly useful for high volume usage due to
their low cost of production.
• Used in the control of electrical equipment such as
washing machines and electric ovens.

46. PROM

47. MASK PROGRAMMABLE READ
ONLY MEMORY (MROM)
• The user specifies the data to be stored to the
manufacturer of the memory.
• The data pattern specified by the user are
programmed as a part of the fabrication process.
• Once programmed, the data pattern can never be
changed.
• Highly suited for very high volume of usage due to
their low cost.

48. MASK PROGRAMMED ROM
(MROM)

49. ERASABLE PROGRAMMABLE
READ ONLY MEMORY(EPROM)
• Data can be written any number of times, i.e,
reprogrammable.
• Before it is reprogrammed, the contents already stored
are erased by exposing the chip to ultraviolet radiation
for about 30 minutes.
• Programming done using- PROM Programmer
• The data bits are represented by the presence or
absence of a stored charge.
• EPROM Cell- n channel enhancement MOSFET with
insulated gate structure.
• Consist of Floating gate formed within SiO2 layer and
control gate.

50. EPROM
• During programming, an electrical charge is
trapped in an insulated gate region. The charge
is retained for more than 10 years because the
charge has no leakage path. For erasing this
charge, ultra-violet light is passed through a
quartz crystal window (lid). This exposure to
ultra-violet light dissipates the charge. During
normal use, the quartz lid is sealed with a
sticker.

51. EEPROM

52. DISADVANTAGES OF EPROM
• Changes in the selected memory cannot be
made in the reprogramming.
• Entire memory should be erased before
reprogramming
• The EPROM IC must be removed from the
circuit and the stored program can be erased by
exposing the memory cells to UV light through
a “window” on the IC package.

53. ELECTRICALLY ERASABLE AND
PROGRAMMABLE READ ONLY
MEMORY(EEPROM)
• Erasing is done electrically rather than exposing
the chip to the ultraviolet radiation.
• EAPROM-Electrically Alterable Programmable
Read Only Memory.
• Erased and programmed by the application of
controlled electric pulses to the IC in the circuit.
• Changes can be made in the selected memory
locations without disturbing the correct data in
other memory locations.

54. EEPROM
• It can be erased and reprogrammed about ten
thousand times. Both erasing and
programming take about 4 to 10 ms
(millisecond). In EEPROM, any location can
be selectively erased and programmed.
EEPROMs can be erased one byte at a time,
rather than erasing the entire chip. Hence, the
process of reprogramming is flexible but slow.

55. COMPARISON OF LOGIC
FAMILIES

56. ECL-absence of minority charge
storage
• Emitter-Coupled Logic (ECL) is a high-speed integrated circuit bipolar
transistor logic family. ECL uses an overdriven BJT differential amplifier
with single-ended input and limited emitter current to avoid the saturated
(fully on) region of operation and its slow turn-off behavior.[2] As the
current is steered between two legs of an emitter-coupled pair, ECL is
sometimes called current-steering logic (CSL),[3] current-mode logic
(CML)[4] or current-switch emitter-follower (CSEF) logic.[5]
• In ECL, the transistors are never in saturation, the input/output voltages
have a small swing (0.8 V), the input impedance is high and the output
resistance is low; as a result, the transistors change states quickly, gate
delays are low, and the fanout capability is high.[6] In addition, the
essentially constant current draw of the differential amplifiers minimises
delays and glitches due to supply-line inductance and capacitance, and the
complementary outputs decrease the propagation time of the whole circuit
by reducing inverter count.
• ECL's major disadvantage is that each gate continuously draws current,
which means that it requires (and dissipates) significantly more power than
those of other logic families, especially when quiescent.

57. transmission gate
• A transmission gate, or analog switch, is defined
as an electronic element that will selectively
block or pass a signal level from the input to the
output. This solid-state switch is comprised of a
pMOS transistor and nMOS transistor.
• that can conduct in both directions or block by a
control signal with almost any voltage potential. It
is a CMOS-based switch, in which PMOS passes
a strong 1 but poor 0, and NMOS passes strong 0
but poor 1. Both PMOS and NMOS work
simultaneously.