The document provides an introduction to embedded systems and Internet of Things. It discusses embedded systems, their characteristics, categories including stand-alone, real-time, networked and mobile systems. It also covers ARM processors, their architecture featuring RISC load/store architecture and features like reduced instruction set. Real-time scheduling algorithms like Rate Monotonic, Deadline Monotonic and dynamic algorithms like Earliest Deadline First, Least Laxity First are also summarized.

1. Introduction to embedded system
and
Internet of Things
Unit I
Mrs. K.M. Sanghavi

4. 1.1 Embedded System
It is an electronic system which includes a single chip
microcomputer(Microcontrollers) like ARM, Cortex.
It is configured to perform certain dedicated application.
S/w is programmed into the on-chip ROM of the
microcontroller, to solve limited range of problems.
The microcontroller is embedded inside the system.

5. Embedded System…cont
In real
time
Accepts
input
Performs
computation
Generates
Output
Executes

7. Embedded System…cont
For eg. A typical mobile contains average of 10 microcontrollers
Modern houses approx. 150 microcontrollers per day.
Embedded system generally covers every branch from day-to-day science and
technology like communication, military, medical, consumer, machine control.
Eg. Cell phone, Digital camera , microwave, MP3 player, Automobile Anti
braking system.

10. 1.2 Characteristics of Embedded
System
Speed (bytes/sec) :
should be high.
Power(watts) : Low
power tolerance
Size and weight : Small
size and low weight
Accuracy(0.9999) :
Must be very accurate
Adaptability : High
adaptability and
accessibility
Reliability : Must be
reliable for a longer
period of time

11. Categories of Embedded System
Stand
Alone
Real Time Networked Mobile

12. Stand Alone System
Works by itself : self-contained device
Does not require any host system like computer
Takes digital/ analog input , calibrates , converts and processes the
data and outputs the resulting data to its attached o/p device
Eg : MP3 players, digital cameras, Video game consoles, Microwave
oven

13. Real Time Systems
System which strictly follows time deadline
for completion of task is real time system
Two types of Real Time Systems Exist
• Soft : Violation of time constraint just degrades quality
of the system but the system continues to work
• Hard : Violation of time causes critical failure and loss of
life or property damage.

14. Soft Real System Examples

15. Hard Real Time
Delayed alarm during gas leakage
Failure in RADAR functioning
Deadline in missile control

16. Networked System
Related to n/w interface to access
resources
Connected n/w may be LAN , WAN and
connection can be wired or wireless
Eg : Home security system

17. Mobile Systems
• MP3 players, Mobiles, Cellphones, PDAs,
Digital cameras which have the limitation of
memory

18. ARM Processor & Its Architecture

19. ARM

20. ARM
processor
 An ARM processor is one of a family
of CPUs based on the RISC (reduced
instruction set computer) architecture
developed by Advanced RISC Machines
(ARM).
 ARM makes 32-bit and 64-bit RISC multi-
core processors
 RISC processors are designed to perform a
smaller number of types of
computer instructions so that they can
operate at a higher speed, performing
more millions of instructions per second
(MIPS).

21. ARM
Processor
 ARM processors are extensively used in
consumer electronic devices such
as smartphones, tablets, multimedia players
and other mobile devices, such
as wearables.
 Because of their reduced instruction set,
they require fewer transistors, which
enables a smaller die size for the
integrated circuitry (IC).
 The ARM processor’s smaller size, reduced
complexity and lower power
consumption makes them suitable for
increasingly miniaturized devices.

22. ARM
PROCESSOR
FEATURES
 Load/store architecture.
 An orthogonal instruction set.
 Mostly single-cycle execution.
 Enhanced power-saving design.
 64 and 32-bit execution states for
scalable high performance.
 Hardware virtualization support.

23. ARM Architecture
• ARM machines have a 32 bit Reduced Instruction
Set Computer (RISC) Load Store Architecture.
• The direct manipulation of memory isn’t
possible in this architecture and is done through
the use of registers.
• The instruction set offers many conditional and
other varieties of operations with the primary
focus being on reducing the number of cycles per
instruction featuring mostly single cycle
operations.

24. ARM Architecture….Contd[2]
The main Features of ARM7 is,
• 32/16-bit RISC architecture.
• 32-bit ARM instruction set for maximum performance and
flexibility.
• 16-bit Thumb instruction set for increased code density.
• Unified bus interface, 32-bit data bus carries both instructions and
data.
• Three-stage pipeline : FETCH, DECODE and EXECUTE.
• 32-bit ALU.
• Very small die size and low power consumption.
• Fully static operation.
• Coprocessor interface.
• Extensive debug facilities (Embedded ICE debug unit accessible via
JTAG interface unit) : that allows programs to be downloaded and
fully debugged in-system.

25. ARM Architecture

26. ARM Architecture….Contd
• Control over both the Arithmetic Logic Unit (ALU)
and shifter in most data-processing instructions
to maximize the use of an ALU and a shifter.
• Auto-increment and auto-decrement addressing
modes to optimize program loops.
• Load and Store Multiple instructions to maximize
data throughput.
• Conditional execution of almost all instructions to
maximize execution throughput

27. • ARM has 31 general-purpose 32-bit registers,
At any one time, 16 of these registers are
visible
• These registers are used by all unprivileged
code.(User mode Registers) i.e less access to
memory and coprocessor

28. Privileged execution modes
• Fast interrupt processing mode Used when processor
receives an interrupt signal from the designated fast
interrupt source.
• Normal interrupt processing mode: When processor
receives an interrupt signal from any other interrupt
source.
• Software interrupt mode : When the processor encounters
a software interrupt instruction.
• Undefined instruction mode :When the processor
attempts to execute an instruction that is supported
neither by the main integer core nor by one of the
coprocessors.
• System mode is used for running privileged operating
system tasks.
• Abort mode is : When memory fault exists

29. ARM SOC..>System On CHip
• Whole system on a small single chip.
• It is called as an IC that holds together memory,
clock, GPIO pins, digital and analog pins and the
processor at its core.
• A microcontroller, microprocessor or DSP core(s).
Some SoCs—called multiprocessor system on chip
(MPSoC)—include more than one processor core.
• Memory blocks including a selection of ROM, RAM,
EEPROM and flash memory.

31. ARM SOC..>System On CHip
• Timing sources including oscillators and phase-
locked loops.
• Peripherals including counter-timers, real-time
timers and power-on reset generators.
• External interfaces including industry standards
such as USB, FireWire, Ethernet, USART, SPI.
• Analog interfaces including ADCs and DACs.
• Voltage regulators and power management circuits

33. ARM Register Set
Num of Registers : Total 37 registers. 20 (banked) not visible at all
times. Min 17 visible in all modes. 16 general purpose, 1 status
related.
Banked Registers: Each mode has a set of extra registers called
banked registers. Banked registers are swapped in whenever mode
change happens.
R13 - SP; holds stack head in the current processor mode.
R14 - LR( points to the return address when calling subroutine)
R15 - PC. Program counter. Contains the address of the next
instruction to be fetched by the processor.
In addition to the main registers there is also a status register:
CPSR is the current program status register. This holds flags:
results of arithmetic and logical operations.

35. CPSR Of ARM

36. ARM Instruction Set

37. ARM Instruction Set

38. ARM Instruction Set

39. ARM Reference
[1] https:// www. computerhope.com /jargon /a/
arm.htm
[2]
https://www.pantechsolutions.net/microcontroller-
tutorials/getting-started-with-arm-architecture
[3]
http://users.ece.utexas.edu/~valvano/EE345M/Arm_E
E382N_4.pdf

40. Real Time Systems
Mrs. K.M. Sanghavi

43. MultiTasking is done by a controller using a scheduler

44. Most Important Aspect of Real Time
System

45. Types of Real Time Systems
Hard …Follows Absolute Deadline (i.e Task must
Perform its Operation in a certain time) . These
have time constraints.
Soft …Follows Relaxed Deadline (i.e Task should
Perform its Operation in a certain time or so.).
These do not follow time constraints strictly.
Hence Real Time Systems use the concept of Priority

46. Real Time Scheduling
Mrs. K.M. Sanghavi

47. Real Time Scheduling Times
• Arrival Term
• Ready Time
• Scheduling Time
• Burst / Run Time
• Waiting Time
• Completion Time
• Deadline Time
• Tardiness : When Task misses the deadline
– Completion Time - Deadline
• Laxity : Task follows Deadline
– Deadline – Completion Time

48. RM DM

49. Rate Monotic
• Rate Monotonic refers to assigning priorities as a monotonic
function of the rate (frequency of occurrence) of those
processes.
• Rate Monotonic Scheduling (RMS) can be accomplished based
upon rate monotonic principles.
• Priority and Time period are inversely proportional
• Higher the time period lower the priority.
• This is a preemptive static priority algorithm.

50. Frank Drews Real-Time Systems
Rate Monotonic Analysis: Assumptions
A1: Tasks are periodic (activated at a constant rate).
Period = Interval between two consecutive activations of task
A2: All instances of a periodic task have
the same computation time
A3: All instances of a periodic task have the same relative deadline,
which is equal to the period
A4: All tasks are independent
(i.e., no precedence constraints and no resource constraints)
Implicit assumptions:
A5: Tasks are preemptable
A6: No task can suspend itself
A7: All tasks are released as soon as they arrive
A8: All overhead in the kernel is assumed to be zero (or part of )
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51. Rate Monotonic Algorithm
Algorithm
to schedule
priority
tasks
It is based on
priorities
A Higher
priority
process will
preempt a
lower priority
process
Process Burst Time Period
P1 2 10
P2 1 5
P3 5 30
P4 2 15

52. Utilization Bound (UB) Test
Processor Utilization for a task, i Ui =
Ci
Ti
Utilization Bound for n tasks U(n) = n(2 - 1)
1
n
Results:
• If S Ui ≤ U(n) then the set of tasks is schedulable.
• If S Ui > 1 then the set of tasks is unschedulable.
• If U(n) < S Ui ≤ 1 then the test is inconclusive.

53. RMA
• For that we need to use two formulas and check
L.H.S (CPU Utilization) <= R.H.S (Utilization Bound Tasks) :
≤

54. RMA
• Will never miss a deadline if RMA is applied

55. • Now Schedule the task
Process Burst Time Period
P1 2 10
P2 1 5
P3 5 30
P4 2 15

56. Process Burst Time Period
P1 2 10
P2 1 5
P3 5 30
P4 2 15

57. Example
Process Burst Time Period
P1 2 10
P2 4 15
P3 10 35
≤

58. Deadline Monotonic Algorithm
• Deadline Monotonic refers to
assigning higher priorities to the task
having less deadline
• This is a preemptive static priority
algorithm.

59. Deadline Monotonic Algorithm

60. Dynamic Algorithm….
Earliest DeadLine First
• Similar to Deadline Monotonic Algorithm but only priorities change
dynamically.
• This is a preemptive dynamic priority algorithm.
• For this we have to perform a schedulability test, as follows :
𝐶𝑖
𝑇𝑖
𝑛
𝑖=1
≤ 1

61. Dynamic Algorithm….
Earliest DeadLine First

62. Dynamic Algorithm….
Least Laxity First
• This is a preemptive dynamic priority algorithm.
• For this we have to calculate Laxity for Each task
at each time unit as follows :
L(t) = Deadline – current time – Remaining
Execution time of a Task

63. Dynamic Algorithm….
Least Laxity First

64. Dynamic Algorithm….
Least Laxity First