This document contains 5 sample question papers from previous years' examinations for a Digital Electronics Circuit course. Each paper contains 4-5 questions testing various concepts in digital logic design including:
- Boolean algebra simplification and logic minimization techniques
- Code conversions (binary to gray, decimal to BCD)
- Combinational logic circuits (multiplexers, decoders, adders)
- Sequential logic circuits (latches, flip-flops, counters)
- Logic families and their characteristics (TTL, CMOS, ECL)
Hamming net based Low Complexity Successive Cancellation Polar DecoderRSIS International
This paper aims to implement hybrid based Polar
encoder using the knowledge of mutual information and channel
capacity. Further a Hamming weight successive cancellation
decoder is simulated with QPSK modulation technique in
presence of additive white gaussian noise. The experimentation
performed with the effect of channel polarization has shown that
for 256- bit data stream, 30% channels has zero bit and 49%
channels are with a one bit capacity. The decoding complexity is
reduced to almost half as compared to conventional successive
cancellation decoding algorithm. However, the required SNR of
7 dB is achieved at the targeted BER of 10 -4. The penalty paid is
in terms of training time required at the decoding end.
MODIFIED GOLDEN CODES FOR IMPROVED ERROR RATES THROUGH LOW COMPLEX SPHERE DEC...cscpconf
In recent years, the golden codes have proven to exhibit a superior performance in a wireless MIMO (Multiple Input Multiple Output) scenario than any other code. However, a serious limitation associated with it is its increased decoding complexity. This paper attempts to resolve this challenge through suitable modification of golden code such that a less complex sphere decoder could be used without much compromising the error rates. In this paper, a minimum
polynomial equation is introduced to obtain a reduced golden ratio (RGR) number for golden code which demands only for a low complexity decoding procedure. One of the attractive
approaches used in this paper is that the effective channel matrix has been exploited to perform a single symbol wise decoding instead of grouped symbols using a sphere decoder with tree search algorithm. It has been observed that the low decoding complexity of O (q1.5) is obtained against conventional method of O (q2.5). Simulation analysis envisages that in addition to reduced decoding, improved error rates is also obtained.
Encryption Quality Analysis and Security Evaluation of CAST-128 Algorithm and...IJNSA Journal
This paper demonstrates analysis of well known block cipher CAST-128 and its modified version using avalanche criterion and other tests namely encryption quality, correlation coefficient, histogram analysis and key sensitivity
tests.
Hamming net based Low Complexity Successive Cancellation Polar DecoderRSIS International
This paper aims to implement hybrid based Polar
encoder using the knowledge of mutual information and channel
capacity. Further a Hamming weight successive cancellation
decoder is simulated with QPSK modulation technique in
presence of additive white gaussian noise. The experimentation
performed with the effect of channel polarization has shown that
for 256- bit data stream, 30% channels has zero bit and 49%
channels are with a one bit capacity. The decoding complexity is
reduced to almost half as compared to conventional successive
cancellation decoding algorithm. However, the required SNR of
7 dB is achieved at the targeted BER of 10 -4. The penalty paid is
in terms of training time required at the decoding end.
MODIFIED GOLDEN CODES FOR IMPROVED ERROR RATES THROUGH LOW COMPLEX SPHERE DEC...cscpconf
In recent years, the golden codes have proven to exhibit a superior performance in a wireless MIMO (Multiple Input Multiple Output) scenario than any other code. However, a serious limitation associated with it is its increased decoding complexity. This paper attempts to resolve this challenge through suitable modification of golden code such that a less complex sphere decoder could be used without much compromising the error rates. In this paper, a minimum
polynomial equation is introduced to obtain a reduced golden ratio (RGR) number for golden code which demands only for a low complexity decoding procedure. One of the attractive
approaches used in this paper is that the effective channel matrix has been exploited to perform a single symbol wise decoding instead of grouped symbols using a sphere decoder with tree search algorithm. It has been observed that the low decoding complexity of O (q1.5) is obtained against conventional method of O (q2.5). Simulation analysis envisages that in addition to reduced decoding, improved error rates is also obtained.
Encryption Quality Analysis and Security Evaluation of CAST-128 Algorithm and...IJNSA Journal
This paper demonstrates analysis of well known block cipher CAST-128 and its modified version using avalanche criterion and other tests namely encryption quality, correlation coefficient, histogram analysis and key sensitivity
tests.
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
FURTHER RESULTS ON THE DIRAC DELTA APPROXIMATION AND THE MOMENT GENERATING FU...IJCNC
In this article, we employ two distinct methods to derive simple closed-form approximations for the
statistical expectations of the positive integer powers of Gaussian probability integral Eg [Qp ( bWg )]
with
respect to its fading signal-to-noise ratio (SNR) g random variable. In the first approach, we utilize the
shifting property of Dirac delta function on three tight bounds/approximations for Q(.) to circumvent the
need for integration.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
Question bank on digital electronics. Total 194 questions. Covering questions on basics of digital electronics, number systems, digital gates, logic families, the sum of product, the product of sum, boolean theorem, karnaugh map, coders, etc.
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...IJECEIAES
This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding Equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.
High Speed Memory Efficient Multiplier-less 1-D 9/7 Wavelet Filters Based NED...IJERA Editor
Conventional distributed arithmetic (DA) is popular in field programmable gate array (FPGA) design, and it
features on-chip ROM to achieve high speed and regularity. In this paper, we describe high speed area efficient
1-D discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA)
Technique. Being area efficient architecture free of ROM, multiplication, and subtraction, NEDA can also
expose the redundancy existing in the adder array consisting of entries of 0 and 1. This architecture supports any
size of image pixel value and any level of decomposition. The parallel structure has 100% hardware utilization
efficiency.
Mapping between Discrete Cosine Transform of Type-VI/VII and Discrete Fourier...IJERA Editor
In this paper, the mapping between discrete cosine transform of types VI and VII (DCT-VI/VII) of even length
N and (2N – 1)-point one dimensional discrete Fourier transform (1D-DFT) is presented. The technique used in
this paper is the mapping between the real-valued data sequence to an intermediate sequence used as an input to
DFT
Ec2203 digital electronics questions anna university by www.annaunivedu.organnaunivedu
EC2203 Digital Electronics Anna University Important Questions for 3rd Semester ECE , EC2203 Digital Electronics Important Questions, 3rd Sem Question papers,
http://www.annaunivedu.org/digital-electronics-ec-2203-previous-year-question-paper-for-3rd-sem-ece-anna-univ-question/
Design of Reversible Sequential Circuit Using Reversible Logic SynthesisVLSICS Design
Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.
FURTHER RESULTS ON THE DIRAC DELTA APPROXIMATION AND THE MOMENT GENERATING FU...IJCNC
In this article, we employ two distinct methods to derive simple closed-form approximations for the
statistical expectations of the positive integer powers of Gaussian probability integral Eg [Qp ( bWg )]
with
respect to its fading signal-to-noise ratio (SNR) g random variable. In the first approach, we utilize the
shifting property of Dirac delta function on three tight bounds/approximations for Q(.) to circumvent the
need for integration.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
Question bank on digital electronics. Total 194 questions. Covering questions on basics of digital electronics, number systems, digital gates, logic families, the sum of product, the product of sum, boolean theorem, karnaugh map, coders, etc.
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...IJECEIAES
This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding Equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.
High Speed Memory Efficient Multiplier-less 1-D 9/7 Wavelet Filters Based NED...IJERA Editor
Conventional distributed arithmetic (DA) is popular in field programmable gate array (FPGA) design, and it
features on-chip ROM to achieve high speed and regularity. In this paper, we describe high speed area efficient
1-D discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA)
Technique. Being area efficient architecture free of ROM, multiplication, and subtraction, NEDA can also
expose the redundancy existing in the adder array consisting of entries of 0 and 1. This architecture supports any
size of image pixel value and any level of decomposition. The parallel structure has 100% hardware utilization
efficiency.
Mapping between Discrete Cosine Transform of Type-VI/VII and Discrete Fourier...IJERA Editor
In this paper, the mapping between discrete cosine transform of types VI and VII (DCT-VI/VII) of even length
N and (2N – 1)-point one dimensional discrete Fourier transform (1D-DFT) is presented. The technique used in
this paper is the mapping between the real-valued data sequence to an intermediate sequence used as an input to
DFT
Ec2203 digital electronics questions anna university by www.annaunivedu.organnaunivedu
EC2203 Digital Electronics Anna University Important Questions for 3rd Semester ECE , EC2203 Digital Electronics Important Questions, 3rd Sem Question papers,
http://www.annaunivedu.org/digital-electronics-ec-2203-previous-year-question-paper-for-3rd-sem-ece-anna-univ-question/
This page is vert helpful those students they prepare junior engineer exam like.. SSC JEn, PWD, PHED, RSEB, BSNL JTO, TTA, WRD, DMRC, JMRC, RIICO etc exam
This page is vert helpful those students they prepare junior engineer exam like.. SSC JEn, PWD, PHED, RSEB, BSNL JTO, TTA, WRD, DMRC, JMRC, RIICO etc exams
Unix and Shell Programming,
Q P Code: 60305.
Additional Mathematics I
Q P Code: 60306
Computer Organization and Architecture
Q P Code: 62303
Data Structures Using C
Q P Code: 60303
Discrete Mathematical Structures
Q P Code: 60304
Engineering Mathematics - III
Q P Code: 60301
Soft Skill Development
Q P Code: 60307
Unix and Shell Programming,
Q P Code: 60305.
Additional Mathematics I
Q P Code: 60306
Computer Organization and Architecture
Q P Code: 62303
Data Structures Using C
Q P Code: 60303
Discrete Mathematical Structures
Q P Code: 60304
Engineering Mathematics - III
Q P Code: 60301
Soft Skill Development
Q P Code: 60307
1 Introduction
2 General measurement and diagnostic system
3 Biomedical Signal Analysis - Computer-Aided Diagnosis
4 Concurrent, coupled, and correlated processes - illustration with case studies
5 Questions
Total slides: 73
Universal Asynchronous Receiver Transmitter (UART)
Introduction to Serial Communication
Types of Transmission
Simplex Communication
Duplex Communication
Half Duplex Communication
Full Duplex Communication
Methods of Serial data Transmission
Synchronous serial data transfer
Asynchronous serial data transfer
Differences Synchronous Asynchronous
Data Transfer Rate
Calculation of Baud Rate
SCON Register
SBUF Register
Writing to the Serial port
Reading the Serial port
PCON Register
Programming of transmission byte serially
Programming of reception of byte serially
Examples
Programmable Peripheral Interface (PPI) 8255
Features of 8255
Block Diagram of 8255 PPI
3 Modes of operation of 8255 PPI
BSR Mode of 8255 PPI
Parallel IO of 8255 PPI
IC 8155/8156
Features of 8155/8156
Block Diagram of 8155/8156
Chip Enable Logic & Port Addresses (Peripheral I/O Addressing
Scheme
Control Word Register of 8155
Timers of 8155/8156
Modes of Timers of 8155
IC 8355/8755
Block Diagram of 8155/8156
Basics of Microprocessor 8085
Architecture of 8085
Registers of 8085
Arithmetic Logic Unit of 8085
Instruction Decoder
Address buffer
Address/data buffer
Increment / decrement address latch
Interrupt control
Serial input / output control
Timing and control circuitry
Pin configuration of Microprocessor 8085
Addressing Modes of 8051
Symbol or nomenclature used for data or memory
Instruction sets of 8051
Assembler and Assembler Directives
Delay Calculation
Examples on Delay Calculation
The Microcontroller 8051 Family
Features of 8051 Microcontroller
Pin Configuration of 8051 Microcontroller
Ports of 8051 Microcontroller
Architecture of 8051 Microcontroller
Registers of 8051
Special Function Registers (SFR's)
Bit addressable RAM
Register Bank and Stack of 8051
Semiconductor Memory Fundamentals
Memory Types
Memory Structure and its requirements
Memory Decoding
Examples
Input - Output Interfacing
Types of Parallel Data Transfer or I/O Techniques
Introduction to Interrupts
What happens when the interrupt is occurs
Interrupt Vs Polling
Classfication of Interrupts
Hardware Interrupts of 8085
Software Interrupts of 8085
Maskable Interrupts of Microprocessor 8085
Non - Maskable Interrupts of Microprocessor 8085
Vectored Interrupts of Microprocessor 8085
Non - Vectored Interrupts of Microprocessor 8085
8085 Microprocessor Interrupt Structure
Interrupt Structure of Microprocessor 8085
SIM Instruction
Non - Vectored Interrupt
Pending Interrupts
What is Interrupt
Introduction to 8051 Microcontroller Interrupts
Interrupts of 8051 Microcontroller
Interrupt Vs Polling
IE register
IP register
What happens when an interrupt occurs?
What happens when an interrupt Ends?
Programming Timer Interrupt
Serial Interrupt
External Hardware Interrupt
Examples
Introduction
Embedded Operating Systems
Applications of Embedded Systems
Characteristics of Embedded Systems
Architecture of Real Embedded Systems
Embedded Operating System
Real Time Operating Systems (RTOS)
Total slides: 102
Depletion Layer in PN Junction
Barrier Potential in a PN junction
Energy Diagram of PN Junction
Biasing The PN Junction
V-I Characteristics of P-N junction Diode
Applications of Diode - Rectiers
Photodiode
Light Emitting Diodes - LED
Zener Diode
Total slides: 75
What is Transducers
Selection Criteria of the Transducers
Basic Requirements of a Transducers
Strain Gauge
Inductive Transducer - LVDT
Load Cell
Temperature Transducers
Photoelectric Transducer
LDR
Photovoltaic Solar Cells
Introduction
How a transistor works - the basics
Summary of transistor junction bias scenarios
Bipolar Transistor Configurations
Bipolar Transistor Summary
NPN Transistor
PNP Transistor
Output Characteristics Curves of a BJT
Application of BJT - as a Switch
Cut-off Regio
Saturation Region
Total slides: 109
Light Emitting Diodes
Seven Segment LED
LCD Interfacing
Stepper Motor Interfacing
Digital to Analog Converter
ADC Interfacing
Keyboard Interfacing
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COLLEGE BUS MANAGEMENT SYSTEM PROJECT REPORT.pdfKamal Acharya
The College Bus Management system is completely developed by Visual Basic .NET Version. The application is connect with most secured database language MS SQL Server. The application is develop by using best combination of front-end and back-end languages. The application is totally design like flat user interface. This flat user interface is more attractive user interface in 2017. The application is gives more important to the system functionality. The application is to manage the student’s details, driver’s details, bus details, bus route details, bus fees details and more. The application has only one unit for admin. The admin can manage the entire application. The admin can login into the application by using username and password of the admin. The application is develop for big and small colleges. It is more user friendly for non-computer person. Even they can easily learn how to manage the application within hours. The application is more secure by the admin. The system will give an effective output for the VB.Net and SQL Server given as input to the system. The compiled java program given as input to the system, after scanning the program will generate different reports. The application generates the report for users. The admin can view and download the report of the data. The application deliver the excel format reports. Because, excel formatted reports is very easy to understand the income and expense of the college bus. This application is mainly develop for windows operating system users. In 2017, 73% of people enterprises are using windows operating system. So the application will easily install for all the windows operating system users. The application-developed size is very low. The application consumes very low space in disk. Therefore, the user can allocate very minimum local disk space for this application.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Democratizing Fuzzing at Scale by Abhishek Aryaabh.arya
Presented at NUS: Fuzzing and Software Security Summer School 2024
This keynote talks about the democratization of fuzzing at scale, highlighting the collaboration between open source communities, academia, and industry to advance the field of fuzzing. It delves into the history of fuzzing, the development of scalable fuzzing platforms, and the empowerment of community-driven research. The talk will further discuss recent advancements leveraging AI/ML and offer insights into the future evolution of the fuzzing landscape.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Automobile Management System Project Report.pdfKamal Acharya
The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
When a customer search for a automobile, if the automobile is available, they will be taken to a page that shows the details of the automobile including automobile name, automobile ID, quantity, price etc. “Automobile Management System” is useful for maintaining automobiles, customers effectively and hence helps for establishing good relation between customer and automobile organization. It contains various customized modules for effectively maintaining automobiles and stock information accurately and safely.
When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
Also when the user tries to sale items which are not in stock, the system will prompt the user that the stock is not enough. Customers of this system can search for a automobile; can purchase a automobile easily by selecting fast. On the other hand the stock of automobiles can be maintained perfectly by the automobile shop manager overcoming the drawbacks of existing system.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Halogenation process of chemical process industries
Digital Electronics University Question Bank
1.
Department of Electronics & Communication Engineering
Sanjay Ghodawat University Kolhapur, Maharashtra
Question Bank
Dr. Nilesh B. Bahadure, Department of Electronics Engineering Page 1
Digital Electronics Circuit
University Question Bank
Examination NOV – DEC 2011
1. (a) What are the unit distance codes?
(b) (i) Convert (1001001.011)2 to its equivalent decimal number
(ii) Find 10’s complement of (935)11
(iii) Convert 8686 in BCD
(iv) Convert (250.5)10 into base 3
(c) Simplify the following Boolean function to minimum number of literals.
(i) xy + xy’
(ii) (x+y)(x+y’)
(iii) xyz + x’y + xyz
(iv) zx + zx’y
(v) (A + B)’ (A’ + B’)’
(vi) y(wz’ + wz) + xy
(d) State and explain Demorgan’s theorem of Boolean algebra
2. (a) why and which code used for labeling the cell of k – map?
(b) Determine the minimized expression of the logic function given as
𝒇 ∑ 𝒎 𝟐, 𝟑, 𝟓, 𝟕, 𝟗, 𝟏𝟏, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓
(c) Draw k – map for the function
𝒇𝜶 𝑨𝑫 𝑩𝑫 𝑨 𝑩 𝑪
𝒇𝜷 A’B + BD’
And hence derive the K – map for
𝒇𝟏 𝒇𝜶 . 𝒇𝜷 𝒂𝒏𝒅 𝒇𝟐 𝒇𝜶 𝒇𝜷
Simplify the map for f1 and f2 and give the resulting expression in SOP form.
(d) Simplify the following Boolean function by using the tabulation method
𝒇 ∑ 𝒎 𝟎, 𝟏, 𝟐, 𝟖, 𝟏𝟎, 𝟏𝟏, 𝟏𝟒, 𝟏𝟓
3. (a) Explain the term multiplexing and demultiplexing
(b) Implement a full subtractor using two half subtractor and OR gate.
(c) Describe operation of PLA.
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(d) Explain the operation of four – bit carry – look – ahead adder circuit. What is the merit
of carry – look – ahead adder?
4. (a) Write difference between latch and flip ‐ flop
(b) What is race around condition for J – K flip flop? How it can be avoided in master slave
flip – flop?
(c) Design a Asynchronous decade counter.
(d) Draw and describe the working of parallel – in – serial out (PISO) shift register. Explain
how a number can be shifted in add out from such register.
5. (a) What is tristate logic?
(b) Give comparison among various logic families.
(c) Design NAND, NOR gate using CMOS logic
(d) Define the following parameters.
(i) Noise margin
(ii) Propagation delay
(iii) Power dissipation
(iv) Speed power product
Examination April – May 2011
1. (a) Define self complementing code and gray code
(b) Simplify the following Boolean algebra
i. 𝒀 𝑨𝑩 𝑨 𝑩 𝑪 𝑩 𝑩 𝑪
ii. 𝒀 𝑨𝑩 𝑨. 𝑩 𝑨 𝑪
(c) Explain briefly how hamming code is useful for detecting and correcting errors in
digital communication system
(d) State and explain principal of duality
2. (a) What is k ‐ Map
(b) Simplify using k – map
𝑭 𝑨, 𝑩, 𝑪, 𝑫 ∑ 𝒎 𝟏, 𝟑, 𝟕, 𝟏𝟏, 𝟏𝟓 𝒅 𝟎, 𝟐, 𝟓
(c) Minimize the logic function by using K – Map
𝒀 𝝅𝒎 𝟒, 𝟓, 𝟔, 𝟕, 𝟖, 𝟏𝟐 𝒅 𝟎, 𝟏, 𝟐, 𝟑, 𝟗, 𝟏𝟏, 𝟏𝟒
(d) Simplify the Boolean function by using the tabulation method (Quine – McClusky
method)
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𝑭 𝒂, 𝒃, 𝒄, 𝒅 ∑ 𝒎 𝟏, 𝟑, 𝟒, 𝟓, 𝟗, 𝟏𝟎, 𝟏𝟏 ∑ 𝒅 𝟔, 𝟖
3. (a) What is PAL and PLA?
(b) Implement a full subtractor using two half subtractor OR gate
(c) What is encoder? Draw the logic diagram of octal to binary encoder and explain its
working
(d) Draw a circuit diagram of 4:1 MUX using gates and explain its working
4. (a) What do you mean by race around condition in JK flip flop
(b) Convert JK flip flop into D Flip flop and T Flip flop
(c) Draw logic diagram and waveform for ring counter
(d) With the help of schematic diagram, explain how a shift left and shift right operation
is performed in shift register.
5. (a) Define ‘figure of merit’
(b) Draw a TTL circuit with totem pole output and explain its working
(c) Draw and explain the basic CMOS inverter circuit
(d) Explain with circuit diagram of two input ECL, OR – NOR gate.
Examination NOV – DEC 2010
1. (a) Explain significance of gray code. Convert the binary 1001 to gray code
(b) Implement the following function by using only NOR gates.
𝑭 𝒂 𝒃 𝒄𝒅 𝒃 𝒄′
(c) Reduce the expression by using rule of Boolean algebra
𝑭 𝒙 𝒛 𝒚 𝒛 𝒚 𝒛 𝒙 𝒚 𝒛
(d) Using Boolean algebra show that:
𝑨 𝑩 𝑨 𝑩 𝑫 𝑨 𝑩 𝑫 𝑨 𝑪 𝑫 𝑨 𝑩 𝑪 𝑨 𝑩 𝑪 𝑪 𝑫′
2. (a) Simplify the expression
𝑭 𝒙 𝒚 𝒙𝒚 𝒙 𝒚
(b) Reduce the function by using K – map
𝑭 ∑ 𝒎 𝟏, 𝟓, 𝟔, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒 𝒅 𝟐, 𝟒
(c) Simplify the function by using k – map
𝑭 ∑ 𝒎 𝟎, 𝟐, 𝟒, 𝟔, 𝟕, 𝟖, 𝟏𝟎, 𝟏𝟐, 𝟏𝟑, 𝟏𝟓
(d) Using the Quine – McClusky method, solve the function
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𝒇 𝒘, 𝒙, 𝒚, 𝒛 ∑ 𝒎 𝟎, 𝟏, 𝟓, 𝟕, 𝟖, 𝟏𝟎, 𝟏𝟒, 𝟏𝟓
3. (a) Design full adder by using two half adder
(b) Implement the following function with a MUX
𝑭 𝒂, 𝒃, 𝒄 ∑ 𝒎 𝟏, 𝟑, 𝟓, 𝟔
(c) Design 4 to 16 Decoder using two 3 to 8 decoder
(d) Explain in brief about PLA (programmable logic array)
4. (a) Draw SR latch by using NOR gate
(b) Design MOD – 10 asynchronous counter
(c) Design MOD – 6 synchronous counter.
(d) Do conversion of SR Flip flop to JK flip flop
5. (a) Explain in brief about noise margin
(b) Draw the circuit diagram of two input NAND gate using TTL logic and explain
(c) Define inverter by using CMOS logic and explain
(d) Define the following term with reference to gate
i. Threshold voltage
ii. Propagation delay
iii. Power dissipation
iv. Fan out
Examination April – May 2010
1. (a) Define weighted and non weighted code with suitable example
(b) Simplify the Boolean expression and draw logic diagram
𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁′
(c) Explain with example how hamming code is useful for detecting and correcting errors
in digital communication system
(d) Explain and state principal of duality
2. (a) Differentiate between combinational and sequential circuits
(b) Minimize the logic function by using K – map
𝒀 𝝅𝒎 𝟎, 𝟏, 𝟑, 𝟓, 𝟔, 𝟕, 𝟏𝟎, 𝟏𝟒, 𝟏𝟓
(c) Use tabular method to minimize the expression (Quine – McClusky method)
𝒇 ∑ 𝒎 𝟎, 𝟐, 𝟑, 𝟔, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟑
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(d) Why it is essential to use minimization techniques before designing any digital circuit?
Differentiate between expansion in SOP and POS form.
3. (a) Differentiate between active low o/p and active high o/p giving example
(b) Design a 4 bit (digit) BCD adder circuit
(c) Construct a 4 x 16 decoder using 3 to 8 decoder
(d) Design a 4 bit comparator circuit
4. (a) what is difference between pulse triggering and edge triggering circuit
(b) Design a SR flip flop using NAND gate and describe working with truth table?
(c) What is race around condition for JK flip flop? How it can be avoided in master slave
flip flop
(d) Design a mod – 5 synchronous counter using T – flip flop
5. (a) Define the term fan – in and fan – out with suitable example?
(b) Why DTL is faster than TTL?
(c) Design NAND, NOR gate using CMOS logic?
(d) Explain characteristics of digital integrated circuit (IC)?
Examination NOV – DEC 2009
(a) Each questions carry equal marks
(b) Attempt any two part of each question
1. (a) What do you mean by universal gate? Design other basic gate using universal gate
(b) Convert followings
I. (134)8 to Hexadecimal
II. Give excess – 3 code of 38H
III. Subtract using 9’s complement (5250)10 – (9678)10
IV. (1001001.011)2 in decimal
(c) Simplify following in minimum numbers of literals
I. 𝒙 𝒚 𝒛 𝒙 𝒚 𝒙 𝒚 𝒛′
II. 𝒚 𝒘 𝒛 𝒘 𝒛 𝒙 𝒚
III. 𝒛 𝒙 𝒛 𝒙 𝒚
IV. 𝒙 𝒚 𝒙 𝒚
2. (a) Simplify the logic expression using K – map
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𝑭 𝑨, 𝑩, 𝑪, 𝑫 ∑ 𝒎 𝟎, 𝟏, 𝟐, 𝟑, 𝟓, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟐, 𝟏𝟑 and also design logic circuit
using gates.
(b) Simplify the following using tabulation method
𝑭 𝑨𝑩𝑪𝑫𝑬𝑭𝑮 ∑ 𝒎 𝟐𝟎, 𝟐𝟖, 𝟓𝟐, 𝟔𝟎
(c) Write down the steps to minimize Boolean expression and also discuss different
theorem involve in it.
3. (a) Design digital circuit to perform addition of two BCD number and also discuss the
difference between parallel binary adder and BCD adder
(b) Implement full adder using multiplexer
(c) Write down the brief notes on PLA (Programmable logic array)
4. (a) Convert SR flip flop into JK flip flop and also discuss the race around condition in JK flip
flop
(b) What is difference between synchronous and asynchronous counter? Design MOD ‐10
synchronous counter
(c) What is register? Give the SISO (serial in serial out) configuration of the register
5. (a) Discuss TTL logic family and also give detail of totem pole output driver
(b) What is ECL logic why it is not so popular? Give advantages and disadvantages of it
(c) Give the various characteristics of digital IC’s? Basis of which the performance of IC’s
can be compared.
Examination April – May 2009
1. (a) Assume that the data has been encoded in a 7 – bit even parity hamming code and
number 1011011 is received. Find out the bit in error. What will the corrected code
be?
(b)
i. Convert (1010000)gray code to its equivalent decimal number
ii. Find 15’s complement of (92B)16
iii. Find the value of base X : (193)x = (623)8
iv. Perform the decimal addition in excess – 3 code, (205 + 569)
v. Represent “CSVTU” in EBCDIC code
vi. Divide (11011.10)2 by (101)2
vii. Convert (1234)10 into self complemented code
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(c)
i. Demonstrate by means of truth table the validity of the Demorgan’s theorems
(both forms) for three variables.
ii. Using Boolean algebra show that:
𝑩 𝑪 𝑨 𝑪 𝑨 𝑩 𝑩 𝑪 𝑫 𝑩 𝑪 𝑨 𝑪′
(d) Implement the following function with NAND gates. Assume that both the normal and
complement inputs are available
𝑩 𝑫 𝑩 𝑪 𝑫 𝑨 𝑩 𝑪 𝑫 𝑨 𝑩 𝑪 𝑫′
With no more than six gates each having three inputs.
2. (a) Why and which code is used for the labeling the cell of K – map
(b) With the use of maps, find the simplest form in sum of product of the function F = f + g
and f – g, where f and g are given by
𝑭 𝒘 𝒙 𝒚 𝒚 𝒛 𝒘 𝒚 𝒛 𝒙 𝒚 𝒛′
𝒈 𝒘 𝒙 𝒚 𝒛 𝒙 𝒚 𝒛 𝒘 𝒚 𝒛
(c) Simplify the Boolean function F using the don’t care condition d in SOP and POS forms
and design using universal gate:
𝑭 𝑨 𝑩 𝑫 𝑨 𝑪 𝑫 𝑨 𝑩 𝑪
𝒅 𝑨 𝑩 𝑪 𝑫 𝑨 𝑪 𝑫 𝑨 𝑩 𝑫′
(d) Simplify the Boolean function F in POS form using tabulation method
𝑭 𝑨, 𝑩, 𝑪, 𝑫 𝟑, 𝟒, 𝟓, 𝟏𝟒, 𝟗 𝒅 𝟕, 𝟏𝟑, 𝟏𝟓
3. (a) Implement a 32 x 1 MUX using 16 x 1 and 2 x 1 MUX
(b) A combinational circuits is defined by the function
𝑭𝟏 𝑨, 𝑩, 𝑪 𝟑, 𝟓, 𝟔, 𝟕
𝑭𝟐 𝑨, 𝑩, 𝑪 𝟎, 𝟐, 𝟒, 𝟕
Implement the circuit with a PLA having three inputs, four product terms and two
outputs
(c) Figure shows the intersection of main highway with a secondary access road. Vehicle
detection sensors are placed along lanes C and D (main road) and A & B (access road).
These sensors output are low when no vehicle is present and high when vehicle is
present. The intersection of traffic light is to be controlled according to the following
logic
i. The E – W will be green whenever both lanes C and D are occupied
ii. The E – W will be green whenever either C or D is occupied but lanes A and B are
not both occupied
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iii. The N – S will be green whenever both A and B are occupied but C and D are not
both occupied.
iv. The N – S will be green either A or B is occupied while C and D are both vacant.
v. The E – W will be green when no vehicles are present. Using the sensor output and
inputs only two outputs N – S and E – W will go high when corresponding light is
green. Design it using minimum number of gates.
(d) Design 2’s complement circuit using IC 74283 and IC 74136
4. (a) Draw the logic diagram of 4 – bit Johnson ring counter
(b) Design a counter with the following binary sequences:
0, 4, 2, 1, 6 and repeat. Use J – K Flip flop
(c) Design a asynchronous decade counter
(d) The content of a 4 – bit shift register is initially 1101. The register is shifted six times to
the right, with the serial input being 101101. What is the content of the register after
each shift?
5. (a) What is fan – out?
(b) Define the following parameters
i. Current and voltage
ii. Noise margin
iii. Propagation delay
iv. Power dissipation
v. Speed power product
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(c) Draw the circuit diagram and explain the operation of 2 inputs TTL NAND gate with
totem – pole output
(d) Compare the characteristics of DTL, TTL, RTL and ECL logic families.
Examination NOV – DEC 2008
1. (a) What is hamming code?
(b) In block diagram form draw a circuit which satisfies simultaneously the conditions
i. The output is excited if any pair of input A1, A2 and A3 is excited. Provided
that B is also excited.
ii. The output is 1 if any one (and only) one of the inputs A1, A2 or A3 is 1,
provided B = 0
iii. No output is excited if A1, A2 and A3 are simultaneously excited
(c) What do you understand by minterms and maxterms? Expand
𝑨 𝑨 𝑩 𝑨 𝑩 𝑪 to maxterms and minterms.
(d) Write down the equation for switch circuit shown in figure and also draw equivalent
circuit using logic gates.
2. (a) What do you understand by don’t care terms? How they play an important role in
expression minimization?
(b) Reduce the following expression using tabular method
𝑭 ∑ 𝒎 𝟎, 𝟐, 𝟑, 𝟓, 𝟖, 𝟏𝟎, 𝟏𝟏, 𝟏𝟑
(c) Minimize the following expression using Quine – McClusky method
𝑭 ∑ 𝒎 𝟎, 𝟏, 𝟖, 𝟗, 𝟏𝟓, 𝟏𝟕, 𝟐𝟏, 𝟐𝟒, 𝟐𝟓, 𝟐𝟕, 𝟑𝟏
(d) Do the following:
i. Divide (4570.32)8 by 68
ii. Multiply (2763.5)8 by 68
3. (a) How many 2 x 4 decoders are required to construct one 3 to 8 decoder
(b) Design a full subtractor circuit using 2 inputs EX – OR gate and basic gates. Also give
block diagram of full subtractor using half subtractor.
(c) Design a 4 bit binary parallel adder cum subtractor dual purpose circuit.
(d) Draw and explain look ahead carry generator.
4. (a) Explain race around condition in JK flip flop
(b) Explain how multiplexer is used as universal function generator
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(c) Design and explain BCD counter.
(d) Design JK flip flop using SR flip flop
5. (a) What do you mean by ‘wired logic in TTL’
(b) Explain unsaturated logic and give its advantages.
(c) Explain open collector TTL with its application.
(d) Give comparison among various logic families.
Examination April – May 2008
1. (a) Define weighted and non weighted code with suitable example
(b) Describe De‐Morgan’s theorem and explain describing their proof
(c) explain gray to binary code conversion and convert the binary number (11001010)2
into gray code
(d) Simplify the Boolean expression and draw the logic diagram:
𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁′
2. (a) Simplify the expression in standard SOP form:
𝒀 𝑨 𝑩 𝑪 𝑨′ 𝑩𝑪 𝑩 𝑪 𝑨
(b) Reduce the following four pair variable function using K – map and implement it by
AND gate
𝑭 ∑ 𝒎 𝟎, 𝟒, 𝟏𝟐, 𝟖, 𝟏𝟑, 𝟗, 𝟕, 𝟏𝟓
(c) Simplify the following Boolean function by K – map
𝑭 ∑ 𝒎 𝟎, 𝟏, 𝟐, 𝟑, 𝟔, 𝟕, 𝟏𝟑, 𝟏𝟒 𝒅 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟐
(d) Reduce the following Boolean function by using tabular method
𝑭 ∑ 𝒎 𝟎, 𝟏, 𝟒, 𝟓, 𝟔, 𝟏𝟖, 𝟏𝟗, 𝟐𝟐, 𝟐𝟖
3. (a) Explain the term multiplexing and demultiplexing
(b) Design a 4 – bit BCD adder circuit
(c) Describe the operation of program array logic with suitable example
(d) Design a 4 – bit comparator circuit.
4. (a) “Flip flop is a sequential circuit”. Explain
(b) Design SR flip flop using NAND gate and describe the working with truth table
(c) Design a 4 bit asynchronous counter with provision for asynchronous leading
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(d) Draw and describe the working of a parallel – in – serial out (PISO) shift register.
Explain how a number can be shifted in and out from such register.
5. (a) Define the term fan out with suitable example
(b) Discuss interfacing of CMOS to TTL logic family
(c) Draw and describe the basic operation and fabrication of I2
L logic family
(d) Explain the logic circuit of TTL. What is totem pole output?
Examination NOV – DEC 2007
1. (a) What is application of gray codes?
(b) Explain with examples, how hamming code is useful for detecting and correcting
errors in digital communication system?
(c) Using Boolean algebra, prove that
i. 𝑨 𝑩 𝑨 𝑩 𝑪 𝑨 𝑩 𝑨
ii. 𝑩 𝑨 𝑩 𝑫 𝑨 𝑪 𝑪 𝑫 𝑩𝑪 𝑨𝑫
(d) State and explain principal of duality.
2. (a) Implement EX – OR gate using four NAND gates.
(b) Find expression for following and implement using logic gates
𝑭 𝑨, 𝑩, 𝑪, 𝑫 𝝅 𝑴 𝟎, 𝟐, 𝟒, 𝟓, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓
(c) Reduce expression using Quine McClusky method
𝒇 𝑨, 𝑩, 𝑪, 𝑫 ∑ 𝒎 𝟐, 𝟑, 𝟔, 𝟕, 𝟖, 𝟗, 𝟏𝟑, 𝟏𝟓 𝒅 𝟒, 𝟏𝟎, 𝟏𝟐
(d) Find reduced SOP form for following equation
𝑭 𝑨, 𝑩, 𝑪, 𝑫 ∑ 𝒎 𝟏, 𝟑, 𝟕, 𝟏𝟏, 𝟏𝟓 ∑ 𝒅 𝟎, 𝟐, 𝟓, 𝟖, 𝟏𝟒
3. (a) What is PAL and PLA?
(b) The input to a combinational logic circuit is a 4 bit binary number. Design the circuit
with minimum hardware for the following
i. Output y1 = 1 if the number is prime
ii. Output y2 = 1 if the number is divisible by 3
(c) Design circuit which will accept 4 bit binary and will provide 5 bit BCD code
(d) Design single digit BCD adder using IC 7483
4. (a) Draw following circuit:
i. RS NAND latch
ii. RS NOR latch
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(b) With the help of waveform explain the following terms:
i. Propagation delay
ii. Set up time
iii. Hold time of flip flop
(c) With the help of schematic diagram, explain how a shift left and shift operation is
performed in a shift register.
(d) Design synchronous counter for following state diagram.
5. (a) What is tristate logic?
(b) Explain various specifications of logic family
(c) Draw the circuit diagram of 2 input TTL NAND gate and explain its operation
(d) Explain with circuit diagram ECL OR / NOR gate
Examination April – May 2007
Attempt any one question from UNIT – III and attempt any two questions from I, II, IV and V
units. All questions carry equal marks. Write all parts of a unit together at one place.
1. (a) 1x 3 + 5
i. Find gray code equivalent of hexadecimal number (A2C)16
ii. Find XS – 3 code of octal number (267)8
iii. Find 5421 BCD equivalent of 83
iv. Construct the even parity seven bit hamming code for a word 1011.
(b)
i. Add 647 and 482 in 8421 BCD
ii. Add 36 and 39 in XS – 3 form
iii. Using 9’s complement, subtract 72532 ‐ 3250
(c)
i. Show that AB + ABC’ + BC’ = AC + B’C
ii. Express the Boolean function F = A + BC in SOP and POS form
2. (a) Reduce using mapping the following Boolean function in
13.
Department of Electronics & Communication Engineering
Sanjay Ghodawat University Kolhapur, Maharashtra
Question Bank
Dr. Nilesh B. Bahadure, Department of Electronics Engineering Page 13
i. Sum of products
ii. Product of sums
Also implement it is universal logic
𝑭 𝑨, 𝑩, 𝑪, 𝑫 𝒎 𝟎, 𝟏, 𝟐, 𝟑, 𝟓, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟐, 𝟏𝟑
(b) Design each of the following circuits that can be built using AND / OR / INVERT logic
and outputs 1 when:
i. A 4‐ bit hexadecimal input is an odd number from 0 to 9
ii. A 4 – bit BCD code translated to a number that uses the upper right segment
of a seven segment display
(c) Obtain minimal SOP expression for the function using Quine – McClusky method
𝑭 𝑨, 𝑩, 𝑪, 𝑫 ∑ 𝒎 𝟔, 𝟕, 𝟖, 𝟗 and don’t care conditions are
𝒅 𝟏𝟎, 𝟏𝟏, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓 Also implement it with NAND logic.
3. (a) Design 8421 BCD adder 16 x 3
(b) Designing BCD to seven segment decoder
(c) What is multiplexer? Implement function 𝑭 𝑨, 𝑩, 𝑪 ∑ 𝟏, 𝟑, 𝟓, 𝟔 with 4 x 1
multiplexer. Also design 8 x 1 multiplexer.
4. (a) Draw the logic diagram of JK flip flop and explain its working to:
i. Obtain the flip flop characteristics table
ii. Obtain characteristic equation
iii. Obtain excitation table
(b)
i. What is shift register? Explain various types of shift register in brief
ii. The content of 4 – bit shift register is initially 1101. The register is shifted six
times to the right, when serial input being 101101. What is the content of the
register after each shift?
(c) Design a synchronous counter that has a repeated sequence of six states
0 ‐ 1 ‐ 2 ‐ 4 ‐ 5 ‐ 6.
Use J – K flip flop.
5. (a) Explain the following terms with reference to a gate:
i. Threshold voltage
ii. Propagation delay
iii. Power dissipation
iv. Fan – in
v. Fan – out