Digital Electronics University Question Bank

Department of Electronics & Communication Engineering
Sanjay Ghodawat University Kolhapur, Maharashtra
Question Bank
Dr. Nilesh B. Bahadure, Department of Electronics Engineering Page 1

Digital Electronics Circuit
University Question Bank

Examination NOV – DEC 2011

1. (a) What are the unit distance codes?
(b) (i) Convert (1001001.011)2 to its equivalent decimal number
(ii) Find 10’s complement of (935)11
(iii) Convert 8686 in BCD
(iv) Convert (250.5)10 into base 3
(c) Simplify the following Boolean function to minimum number of literals.
(i) xy + xy’
(ii) (x+y)(x+y’)
(iii) xyz + x’y + xyz
(iv) zx + zx’y
(v) (A + B)’ (A’ + B’)’
(vi) y(wz’ + wz) + xy
(d) State and explain Demorgan’s theorem of Boolean algebra

2. (a) why and which code used for labeling the cell of k – map?
(b) Determine the minimized expression of the logic function given as
𝒇 ∑ 𝒎 𝟐, 𝟑, 𝟓, 𝟕, 𝟗, 𝟏𝟏, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓
(c) Draw k – map for the function
𝒇𝜶 𝑨𝑫 𝑩𝑫 𝑨 𝑩 𝑪
𝒇𝜷 A’B + BD’
And hence derive the K – map for
𝒇𝟏 𝒇𝜶 . 𝒇𝜷 𝒂𝒏𝒅 𝒇𝟐 𝒇𝜶 𝒇𝜷
Simplify the map for f1 and f2 and give the resulting expression in SOP form.
(d) Simplify the following Boolean function by using the tabulation method
𝒇 ∑ 𝒎 𝟎, 𝟏, 𝟐, 𝟖, 𝟏𝟎, 𝟏𝟏, 𝟏𝟒, 𝟏𝟓

3. (a) Explain the term multiplexing and demultiplexing
(b) Implement a full subtractor using two half subtractor and OR gate.
(c) Describe operation of PLA.

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(d) Explain the operation of four – bit carry – look – ahead adder circuit. What is the merit
of carry – look – ahead adder?

4. (a) Write difference between latch and flip ‐ flop
(b) What is race around condition for J – K flip flop? How it can be avoided in master slave
flip – flop?
(c) Design a Asynchronous decade counter.
(d) Draw and describe the working of parallel – in – serial out (PISO) shift register. Explain
how a number can be shifted in add out from such register.

5. (a) What is tristate logic?
(b) Give comparison among various logic families.
(c) Design NAND, NOR gate using CMOS logic
(d) Define the following parameters.
(i) Noise margin
(ii) Propagation delay
(iii) Power dissipation
(iv) Speed power product

Examination April – May 2011

1. (a) Define self complementing code and gray code
(b) Simplify the following Boolean algebra
i. 𝒀 𝑨𝑩 𝑨 𝑩 𝑪 𝑩 𝑩 𝑪
ii. 𝒀 𝑨𝑩 𝑨. 𝑩 𝑨 𝑪
(c) Explain briefly how hamming code is useful for detecting and correcting errors in
digital communication system
(d) State and explain principal of duality

2. (a) What is k ‐ Map
(b) Simplify using k – map
𝑭 𝑨, 𝑩, 𝑪, 𝑫 ∑ 𝒎 𝟏, 𝟑, 𝟕, 𝟏𝟏, 𝟏𝟓 𝒅 𝟎, 𝟐, 𝟓
(c) Minimize the logic function by using K – Map
𝒀 𝝅𝒎 𝟒, 𝟓, 𝟔, 𝟕, 𝟖, 𝟏𝟐 𝒅 𝟎, 𝟏, 𝟐, 𝟑, 𝟗, 𝟏𝟏, 𝟏𝟒
(d) Simplify the Boolean function by using the tabulation method (Quine – McClusky
method)

Question Bank

𝑭 𝒂, 𝒃, 𝒄, 𝒅 ∑ 𝒎 𝟏, 𝟑, 𝟒, 𝟓, 𝟗, 𝟏𝟎, 𝟏𝟏 ∑ 𝒅 𝟔, 𝟖

3. (a) What is PAL and PLA?
(b) Implement a full subtractor using two half subtractor OR gate
(c) What is encoder? Draw the logic diagram of octal to binary encoder and explain its
working
(d) Draw a circuit diagram of 4:1 MUX using gates and explain its working

4. (a) What do you mean by race around condition in JK flip flop
(b) Convert JK flip flop into D Flip flop and T Flip flop
(c) Draw logic diagram and waveform for ring counter
(d) With the help of schematic diagram, explain how a shift left and shift right operation
is performed in shift register.

5. (a) Define ‘figure of merit’
(b) Draw a TTL circuit with totem pole output and explain its working
(c) Draw and explain the basic CMOS inverter circuit
(d) Explain with circuit diagram of two input ECL, OR – NOR gate.


1. (a) Explain significance of gray code. Convert the binary 1001 to gray code
(b) Implement the following function by using only NOR gates.
𝑭 𝒂 𝒃 𝒄𝒅 𝒃 𝒄′
(c) Reduce the expression by using rule of Boolean algebra
𝑭 𝒙 𝒛 𝒚 𝒛 𝒚 𝒛 𝒙 𝒚 𝒛
(d) Using Boolean algebra show that:
𝑨 𝑩 𝑨 𝑩 𝑫 𝑨 𝑩 𝑫 𝑨 𝑪 𝑫 𝑨 𝑩 𝑪 𝑨 𝑩 𝑪 𝑪 𝑫′

2. (a) Simplify the expression
𝑭 𝒙 𝒚 𝒙𝒚 𝒙 𝒚
(b) Reduce the function by using K – map
𝑭 ∑ 𝒎 𝟏, 𝟓, 𝟔, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒 𝒅 𝟐, 𝟒
(c) Simplify the function by using k – map
𝑭 ∑ 𝒎 𝟎, 𝟐, 𝟒, 𝟔, 𝟕, 𝟖, 𝟏𝟎, 𝟏𝟐, 𝟏𝟑, 𝟏𝟓
(d) Using the Quine – McClusky method, solve the function

Question Bank

𝒇 𝒘, 𝒙, 𝒚, 𝒛 ∑ 𝒎 𝟎, 𝟏, 𝟓, 𝟕, 𝟖, 𝟏𝟎, 𝟏𝟒, 𝟏𝟓

3. (a) Design full adder by using two half adder
(b) Implement the following function with a MUX
𝑭 𝒂, 𝒃, 𝒄 ∑ 𝒎 𝟏, 𝟑, 𝟓, 𝟔
(c) Design 4 to 16 Decoder using two 3 to 8 decoder
(d) Explain in brief about PLA (programmable logic array)

4. (a) Draw SR latch by using NOR gate
(b) Design MOD – 10 asynchronous counter
(c) Design MOD – 6 synchronous counter.
(d) Do conversion of SR Flip flop to JK flip flop

5. (a) Explain in brief about noise margin
(b) Draw the circuit diagram of two input NAND gate using TTL logic and explain
(c) Define inverter by using CMOS logic and explain
(d) Define the following term with reference to gate
i. Threshold voltage
ii. Propagation delay
iii. Power dissipation
iv. Fan out


1. (a) Define weighted and non weighted code with suitable example
(b) Simplify the Boolean expression and draw logic diagram
𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁′
(c) Explain with example how hamming code is useful for detecting and correcting errors
in digital communication system
(d) Explain and state principal of duality

2. (a) Differentiate between combinational and sequential circuits
(b) Minimize the logic function by using K – map
𝒀 𝝅𝒎 𝟎, 𝟏, 𝟑, 𝟓, 𝟔, 𝟕, 𝟏𝟎, 𝟏𝟒, 𝟏𝟓
(c) Use tabular method to minimize the expression (Quine – McClusky method)
𝒇 ∑ 𝒎 𝟎, 𝟐, 𝟑, 𝟔, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟑

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(d) Why it is essential to use minimization techniques before designing any digital circuit?
Differentiate between expansion in SOP and POS form.

3. (a) Differentiate between active low o/p and active high o/p giving example
(b) Design a 4 bit (digit) BCD adder circuit
(c) Construct a 4 x 16 decoder using 3 to 8 decoder
(d) Design a 4 bit comparator circuit

4. (a) what is difference between pulse triggering and edge triggering circuit
(b) Design a SR flip flop using NAND gate and describe working with truth table?
(c) What is race around condition for JK flip flop? How it can be avoided in master slave
flip flop
(d) Design a mod – 5 synchronous counter using T – flip flop

5. (a) Define the term fan – in and fan – out with suitable example?
(b) Why DTL is faster than TTL?
(c) Design NAND, NOR gate using CMOS logic?
(d) Explain characteristics of digital integrated circuit (IC)?

(a) Each questions carry equal marks
(b) Attempt any two part of each question

1. (a) What do you mean by universal gate? Design other basic gate using universal gate
(b) Convert followings
I. (134)8 to Hexadecimal
II. Give excess – 3 code of 38H
III. Subtract using 9’s complement (5250)10 – (9678)10
IV. (1001001.011)2 in decimal
(c) Simplify following in minimum numbers of literals
I. 𝒙 𝒚 𝒛 𝒙 𝒚 𝒙 𝒚 𝒛′
II. 𝒚 𝒘 𝒛 𝒘 𝒛 𝒙 𝒚
III. 𝒛 𝒙 𝒛 𝒙 𝒚
IV. 𝒙 𝒚 𝒙 𝒚

2. (a) Simplify the logic expression using K – map

                Question Bank

𝑭 𝑨, 𝑩, 𝑪, 𝑫 ∑ 𝒎 𝟎, 𝟏, 𝟐, 𝟑, 𝟓, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟐, 𝟏𝟑 and also design logic circuit
using gates.
(b) Simplify the following using tabulation method
𝑭 𝑨𝑩𝑪𝑫𝑬𝑭𝑮 ∑ 𝒎 𝟐𝟎, 𝟐𝟖, 𝟓𝟐, 𝟔𝟎
(c) Write down the steps to minimize Boolean expression and also discuss different
theorem involve in it.

3. (a) Design digital circuit to perform addition of two BCD number and also discuss the
difference between parallel binary adder and BCD adder
(b) Implement full adder using multiplexer
(c) Write down the brief notes on PLA (Programmable logic array)

4. (a) Convert SR flip flop into JK flip flop and also discuss the race around condition in JK flip
flop
(b) What is difference between synchronous and asynchronous counter? Design MOD ‐10
synchronous counter
(c) What is register? Give the SISO (serial in serial out) configuration of the register

5. (a) Discuss TTL logic family and also give detail of totem pole output driver
(b) What is ECL logic why it is not so popular? Give advantages and disadvantages of it
(c) Give the various characteristics of digital IC’s? Basis of which the performance of IC’s
can be compared.


1. (a) Assume that the data has been encoded in a 7 – bit even parity hamming code and
number 1011011 is received. Find out the bit in error. What will the corrected code
be?
(b)
i. Convert (1010000)gray code to its equivalent decimal number
ii. Find 15’s complement of (92B)16
iii. Find the value of base X : (193)x = (623)8
iv. Perform the decimal addition in excess – 3 code, (205 + 569)
v. Represent “CSVTU” in EBCDIC code
vi. Divide (11011.10)2 by (101)2
vii. Convert (1234)10 into self complemented code

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(c)
i. Demonstrate by means of truth table the validity of the Demorgan’s theorems
(both forms) for three variables.
ii. Using Boolean algebra show that:
𝑩 𝑪 𝑨 𝑪 𝑨 𝑩 𝑩 𝑪 𝑫 𝑩 𝑪 𝑨 𝑪′
(d) Implement the following function with NAND gates. Assume that both the normal and
complement inputs are available
𝑩 𝑫 𝑩 𝑪 𝑫 𝑨 𝑩 𝑪 𝑫 𝑨 𝑩 𝑪 𝑫′
With no more than six gates each having three inputs.

2. (a)   Why and which code is used for the labeling the cell of K – map
(b) With the use of maps, find the simplest form in sum of product of the function F = f + g
and f – g, where f and g are given by
𝑭 𝒘 𝒙 𝒚 𝒚 𝒛 𝒘 𝒚 𝒛 𝒙 𝒚 𝒛′
𝒈 𝒘 𝒙 𝒚 𝒛 𝒙 𝒚 𝒛 𝒘 𝒚 𝒛
(c)        Simplify the Boolean function F using the don’t care condition d in SOP and POS forms
and design using universal gate:
𝑭 𝑨 𝑩 𝑫 𝑨 𝑪 𝑫 𝑨 𝑩 𝑪
𝒅 𝑨 𝑩 𝑪 𝑫 𝑨 𝑪 𝑫 𝑨 𝑩 𝑫′
(d) Simplify the Boolean function F in POS form using tabulation method
𝑭 𝑨, 𝑩, 𝑪, 𝑫 𝟑, 𝟒, 𝟓, 𝟏𝟒, 𝟗 𝒅 𝟕, 𝟏𝟑, 𝟏𝟓

3. (a) Implement a 32 x  1 MUX using 16 x 1 and 2 x 1 MUX
(b) A combinational circuits is defined by the function
𝑭𝟏 𝑨, 𝑩, 𝑪 𝟑, 𝟓, 𝟔, 𝟕
𝑭𝟐 𝑨, 𝑩, 𝑪 𝟎, 𝟐, 𝟒, 𝟕
Implement the circuit with a PLA having three inputs, four product terms and two
outputs
(c) Figure shows the intersection of main highway with a secondary access road. Vehicle
detection sensors are placed along lanes C and D (main road) and A & B (access road).
These sensors output are low when no vehicle is present and high when vehicle is
present. The intersection of traffic light is to be controlled according to the following
logic
i. The E – W will be green whenever both lanes C and D are occupied
ii. The E – W will be green whenever either C or D is occupied but lanes A and B are
not both occupied

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iii. The N – S will be green whenever both A and B are occupied but C and D are not
both occupied.
iv. The N – S will be green either A or B is occupied while C and D are both vacant.
v. The E – W will be green when no vehicles are present. Using the sensor output and
inputs only two outputs N – S and E – W will go high when corresponding light is
green. Design it using minimum number of gates.

(d) Design 2’s complement circuit using IC 74283 and IC 74136

4. (a) Draw the logic diagram of 4 – bit Johnson ring counter
(b) Design a counter with the following binary sequences:
0, 4, 2, 1, 6 and repeat. Use J – K Flip flop
(c) Design a asynchronous decade counter
(d) The content of a 4 – bit shift register is initially 1101. The register is shifted six times to
the right, with the serial input being 101101. What is the content of the register after
each shift?

5. (a) What is fan – out?
(b) Define the following parameters
i. Current and voltage
ii. Noise margin
iii. Propagation delay
iv. Power dissipation
v. Speed power product

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(c) Draw the circuit diagram and explain the operation of 2 inputs TTL NAND gate with
totem – pole output
(d) Compare the characteristics of DTL, TTL, RTL and ECL logic families.


1. (a) What is hamming code?
(b) In block diagram form draw a circuit which satisfies simultaneously the conditions
i. The output is excited if any pair of input A1, A2 and A3 is excited. Provided
that B is also excited.
ii. The output is 1 if any one (and only) one of the inputs A1, A2 or A3 is 1,
provided B = 0
iii. No output is excited if A1, A2 and A3 are simultaneously excited
(c) What do you understand by minterms and maxterms? Expand
𝑨 𝑨 𝑩 𝑨 𝑩 𝑪 to maxterms and minterms.
(d) Write down the equation for switch circuit shown in figure and also draw equivalent
circuit using logic gates.

2. (a) What do you understand by don’t care terms? How they play an important role in
expression minimization?
(b) Reduce the following expression using tabular method
𝑭 ∑ 𝒎 𝟎, 𝟐, 𝟑, 𝟓, 𝟖, 𝟏𝟎, 𝟏𝟏, 𝟏𝟑
(c) Minimize the following expression using Quine – McClusky method
𝑭 ∑ 𝒎 𝟎, 𝟏, 𝟖, 𝟗, 𝟏𝟓, 𝟏𝟕, 𝟐𝟏, 𝟐𝟒, 𝟐𝟓, 𝟐𝟕, 𝟑𝟏
(d) Do the following:
i. Divide (4570.32)8 by 68
ii. Multiply (2763.5)8 by 68

3. (a) How many 2 x 4 decoders are required to construct one 3 to 8 decoder
(b) Design a full subtractor circuit using 2 inputs EX – OR gate and basic gates. Also give
block diagram of full subtractor using half subtractor.
(c) Design a 4 bit binary parallel adder cum subtractor dual purpose circuit.
(d) Draw and explain look ahead carry generator.

4. (a) Explain race around condition in JK flip flop
(b) Explain how multiplexer is used as universal function generator

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(c) Design and explain BCD counter.
(d) Design JK flip flop using SR flip flop

5. (a) What do you mean by ‘wired logic in TTL’
(b) Explain unsaturated logic and give its advantages.
(c) Explain open collector TTL with its application.
(d) Give comparison among various logic families.


1. (a) Define weighted and non weighted code with suitable example
(b) Describe De‐Morgan’s theorem and explain describing their proof
(c) explain gray to binary code conversion and convert the binary number (11001010)2
into gray code
(d) Simplify the Boolean expression and draw the logic diagram:
𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁 𝑿 𝒀 𝒁′

2. (a) Simplify the expression in standard SOP form:
𝒀 𝑨 𝑩 𝑪 𝑨′ 𝑩𝑪 𝑩 𝑪 𝑨
(b) Reduce the following four pair variable function using K – map and implement it by
AND gate
𝑭 ∑ 𝒎 𝟎, 𝟒, 𝟏𝟐, 𝟖, 𝟏𝟑, 𝟗, 𝟕, 𝟏𝟓
(c) Simplify the following Boolean function by K – map
𝑭 ∑ 𝒎 𝟎, 𝟏, 𝟐, 𝟑, 𝟔, 𝟕, 𝟏𝟑, 𝟏𝟒 𝒅 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟐
(d) Reduce the following Boolean function by using tabular method
𝑭 ∑ 𝒎 𝟎, 𝟏, 𝟒, 𝟓, 𝟔, 𝟏𝟖, 𝟏𝟗, 𝟐𝟐, 𝟐𝟖

3. (a) Explain the term multiplexing and demultiplexing
(b) Design a 4 – bit BCD adder circuit
(c) Describe the operation of program array logic with suitable example
(d) Design a 4 – bit comparator circuit.

4. (a) “Flip flop is a sequential circuit”. Explain
(b) Design SR flip flop using NAND gate and describe the working with truth table
(c) Design a 4 bit asynchronous counter with provision for asynchronous leading

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(d) Draw and describe the working of a parallel – in – serial out (PISO) shift register.
Explain how a number can be shifted in and out from such register.

5. (a) Define the term fan out with suitable example
(b) Discuss interfacing of CMOS to TTL logic family
(c) Draw and describe the basic operation and fabrication of I2
L logic family
(d) Explain the logic circuit of TTL. What is totem pole output?


1. (a) What is application of gray codes?
(b) Explain with examples, how hamming code is useful for detecting and correcting
errors in digital communication system?
(c) Using Boolean algebra, prove that
i. 𝑨 𝑩 𝑨 𝑩 𝑪 𝑨 𝑩 𝑨
ii. 𝑩 𝑨 𝑩 𝑫 𝑨 𝑪 𝑪 𝑫 𝑩𝑪 𝑨𝑫
(d) State and explain principal of duality.
2. (a) Implement EX – OR gate using four NAND gates.
(b) Find expression for following and implement using logic gates
𝑭 𝑨, 𝑩, 𝑪, 𝑫 𝝅 𝑴 𝟎, 𝟐, 𝟒, 𝟓, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓
(c) Reduce expression using Quine McClusky method
𝒇 𝑨, 𝑩, 𝑪, 𝑫 ∑ 𝒎 𝟐, 𝟑, 𝟔, 𝟕, 𝟖, 𝟗, 𝟏𝟑, 𝟏𝟓 𝒅 𝟒, 𝟏𝟎, 𝟏𝟐
(d) Find reduced SOP form for following equation
𝑭 𝑨, 𝑩, 𝑪, 𝑫 ∑ 𝒎 𝟏, 𝟑, 𝟕, 𝟏𝟏, 𝟏𝟓 ∑ 𝒅 𝟎, 𝟐, 𝟓, 𝟖, 𝟏𝟒

3. (a) What is PAL and PLA?
(b) The input to a combinational logic circuit is a 4 bit binary number. Design the circuit
with minimum hardware for the following
i. Output y1 = 1 if the number is prime
ii. Output y2 = 1 if the number is divisible by 3
(c) Design circuit which will accept 4 bit binary and will provide 5 bit BCD code
(d) Design single digit BCD adder using IC 7483

4. (a) Draw following circuit:
i. RS NAND latch
ii. RS NOR latch

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(b) With the help of waveform explain the following terms:
i. Propagation delay
ii. Set up time
iii. Hold time of flip flop
(c) With the help of schematic diagram, explain how a shift left and shift operation is
performed in a shift register.
(d) Design synchronous counter for following state diagram.

5. (a) What is tristate logic?
(b) Explain various specifications of logic family
(c) Draw the circuit diagram of 2 input TTL NAND gate and explain its operation
(d) Explain with circuit diagram ECL OR / NOR gate

Attempt any one question from UNIT – III and attempt any two questions from I, II, IV and V
units. All questions carry equal marks. Write all parts of a unit together at one place.

1. (a) 1x 3 + 5
i. Find gray code equivalent of hexadecimal number (A2C)16
ii. Find XS – 3 code of octal number (267)8
iii. Find 5421 BCD equivalent of 83
iv. Construct the even parity seven bit hamming code for a word 1011.
(b)
i. Add 647 and 482 in 8421 BCD
ii. Add 36 and 39 in XS – 3 form
iii. Using 9’s complement, subtract 72532 ‐ 3250
(c)
i. Show that AB + ABC’ + BC’ = AC + B’C
ii. Express the Boolean function F = A + BC in SOP and POS form

2. (a) Reduce using mapping the following Boolean function in

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i. Sum of products
ii. Product of sums
Also implement it is universal logic
𝑭 𝑨, 𝑩, 𝑪, 𝑫 𝒎 𝟎, 𝟏, 𝟐, 𝟑, 𝟓, 𝟕, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟐, 𝟏𝟑
(b) Design each of the following circuits that can be built using AND / OR / INVERT logic
and outputs 1 when:
i. A 4‐ bit hexadecimal input is an odd number from 0 to 9
ii. A 4 – bit BCD code translated to a number that uses the upper right segment
of a seven segment display
(c) Obtain minimal SOP expression for the function using Quine – McClusky method
               𝑭 𝑨, 𝑩, 𝑪, 𝑫 ∑ 𝒎 𝟔, 𝟕, 𝟖, 𝟗 and don’t care conditions are
               𝒅 𝟏𝟎, 𝟏𝟏, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓 Also implement it with NAND logic.

3. (a) Design 8421 BCD adder   16 x 3
(b) Designing BCD to seven segment decoder
(c) What is multiplexer? Implement function 𝑭 𝑨, 𝑩, 𝑪 ∑ 𝟏, 𝟑, 𝟓, 𝟔 with 4 x 1
multiplexer. Also design 8 x 1 multiplexer.

4. (a) Draw the logic diagram of JK flip flop and explain its working to:
i. Obtain the flip flop characteristics table
ii. Obtain characteristic equation
iii. Obtain excitation table
(b)
i. What is shift register? Explain various types of shift register in brief
ii. The content of 4 – bit shift register is initially 1101. The register is shifted six
times to the right, when serial input being 101101. What is the content of the
register after each shift?
(c) Design a synchronous counter that has a repeated sequence of six states
0   ‐ 1 ‐ 2 ‐ 4 ‐ 5 ‐ 6.
Use J – K flip flop.

5. (a) Explain the following terms with reference to a gate:
i. Threshold voltage
ii. Propagation delay
iii. Power dissipation
iv. Fan – in
v. Fan – out

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vi. Noise margin
vii. Operating temperature
viii. Speed power product
(b) Compare TTL, ECL, IIL, and CMOS with respect to Fan – in, Fan – out and Tpd
(propagation delay), noise margin, and power dissipation
(c) Explain and draw the circuit diagram for the following
i. Positive logic RTL NOR gate
ii. Positive logic DTL NAND gate.

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