Devry ecet 105 week 3 i lab introduction to digital logic gates new

DEVRY ECET 105 Week 3 iLab Introduction to Digital Logic
Gates NEW
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105-week-3-ilab-introduction-to-digital-logic-gates-new
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I. OBJECTIVES
To understand basic logic functions (AND, OR, and NOT) and
their complement used in Boolean algebra and digital logic
design.
To test simple logic small-scale integration (SSI) integrated
circuit (IC) devices.
II. PARTS LIST
Equipment:
IBM PC or Compatible with Windows 2000 or
Higher
Parts:
1 – 74LS00 Quad 2-Input NAND Gate IC
1 – 74LS02 Quad 2-Input NOR Gate IC
1 – 74LS04 Hex INVERTER Gate IC
1 – 74LS08 Quad 2-Input AND Gate IC
1 – 74LS32 Quad 2-Input OR Gate IC
1 – 74LS86 Quad 2-Input XOR Gate IC
1 – Set of Four Single-Pole-Double-Throw (SPDT)
Switches, DIP Style
1 – 330 Ω resistor
1 – Light emitting diode (LED), red

III. PROCEDURE
OR Gate Operation
Using the Internet or the campus library, acquire a hard copy of
a data sheet for the 74LS32 quad 2-input OR gate. (HINT: Look
at ti.com for possible help.) One of the OR gates is shown below
in Figure 5.1.
Figure 5.1 – 2-Input OR Gate
Fill in the Table 5.1 for ALL possible logic conditions, based on
the information found on the data sheet.
Input (Pin 1) Input (Pin 2) Output (Pin 3)
Table 5.1 - 2-Input OR Gate Theoretical Truth Table
Write the Boolean expression below for the relationship
between the device inputs (labeled as A and B) and output
(labeled as Y).
OUTPUT Y = ____________________________
Construct the circuit shown in Figure 5.2 (a layout of the
breadboard is shown in Figure 5.3). Be sure that the flat side of
the LED (called the cathode) is connected to ground and that
the 74LS32 is connected to power and ground (Pins 14 and 7,
respectively).
Figure 5.2 – OR Gate Test Circuit
Top View
Side View
Figure 5.3 – Breadboard Layout for Figure 5.2
Connect the circuit to verify the logic gate operation recording
the input and output voltages. Fill in Table 5.2below for ALL
possible logic conditions.
Table 5.2 - 2-Input OR Gate Measured Truth Table
Do the results match the manufacturer’s truth table?

__________ (YES or NO)
AND Gate Operation
Acquire a hard copy of a data sheet for the 74LS08 quad 2-input
AND gate.
Figure 5.4 – 2-Input AND Gate
Fill in the truth table below for ALL possible logic conditions
based on the information found on the data sheet.
Table 5.3 - 2-Input AND Gate Theoretical Truth Table
(labeled as Y).
OUTPUT Y = ____________________________
Construct the circuit shown in Figure 5.5 by replacing the
74LS32 from Figure 5.2 with a 74LS08.
Figure 5.5 - 2-Input AND Gate Test Circuit
the input and output voltages. Fill in the truth table below for
ALL possible logic conditions.
Table 5.4 - 2-Input AND Gate Measured Truth Table
__________ (YES or NO)
NAND Gate Operation
NAND gate.
Figure 5.6 – 2-Input NAND Gate
Fill in Table 5.5 for ALL possible logic conditions, based on the
information found on the data sheet.

Table 5.5 - 2-Input NAND Gate Theoretical Truth Table
(labeled as Y).
OUTPUT Y = ____________________________
Figure 5.7 – 2-Input NAND Gate Test Circuit
__________ (YES or NO)
Exclusive-OR Gate Operation
exclusive-OR (XOR) gate.
Figure 5.8 – 2-Input XOR Gate
Fill in the truth table below for ALL possible logic conditions,
Table 5.7 - 2-Input XOR Gate Theoretical Truth Table
(labeled as Y).
OUTPUT Y = ____________________________
Figure 5.9 – 2-Input XOR Gate Test Circuit

__________ (YES or NO)
NOR Gate Operation
NOR gate.
Figure 5.10 – 2-Input NOR Gate
Table 5.9 - 2-Input NOR Gate Theoretical Truth Table
(labeled as Y).
OUTPUT Y = ____________________________
Construct the circuit shown in Figure 5.11. Note that the pin
numbers for inputs and outputs have changes from Figure 5.9
(output is now Pin 1, inputs are on Pins 2 and 3).
Figure 5.11 – 2-Input NOR Gate Test Circuit
Table 5.10 - 2-Input NOR Gate Measured Truth Table
__________ (YES or NO)
NOT Gate Operation
Acquire a hard copy of a data sheet for the 74LS04 hex NOT
gate.
Figure 5.12 – NOT Gate

Table 5.11 - NOT Gate Theoretical Truth Table
between the device input (labeled as A) and output (labeled as
Y).
OUTPUT Y = ____________________________
Construct the circuit shown in Figure 5.13. Note that the pin
numbers for inputs and outputs have changes from Figure 5.11
(output is now Pin 2, input is on Pin 1).
Figure 5.13 – 2-Input NOR Gate Test Circuit
Input (Pin 1) Output (Pin 2)
Table 5.12 - NOT Gate Measured Truth Table
__________ (YES or NO)
TROUBLESHOOTING
Describe any problems encountered and how those problems
were solved.

Devry ecet 105 week 3 i lab introduction to digital logic gates new

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