This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for burst mode applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed CDR circuit leads to higher speed operation and lower power consumption. In addition, to accommodate process, voltage, and temperature (PVT) variations and to increase the lock range, a frequency locked loop is proposed to use in this circuit. The circuit is designed in 0.18 µm CMOS and the simulations for 27-1 pseudo random bit sequence (PRBS) show that the circuit consumes 55.3 mW at 20 Gb/s, while the recovered clock rms jitter is 1.1 ps.
A 20 gbs injection locked clock and data recovery circuitVLSICS Design
This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for burst mode
applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed CDR circuit leads to
higher speed operation and lower power consumption. In addition, to accommodate process, voltage, and
temperature (PVT) variations and to increase the lock range, a frequency locked loop is proposed to use in
this circuit. The circuit is designed in 0.18 μm CMOS and the simulations for 27-1 pseudo random bit
sequence (PRBS) show that the circuit consumes 55.3 mW at 20 Gb/s, while the recovered clock rms jitter
is 1.1 ps
PAM4 Analysis and Measurement Considerations WebinarHilary Lustig
This webinar explores the acquisition and analysis of PAM4 waveforms. We will show PAM4 Test Configurations, Compliance Measurements and Debug Techniques.
Design and Implementation of Submicron Level 10T Full Adder in ALU Using Cell...IJERA Editor
As technology scales into the nanometer regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex circuits. The main concern in mobile and battery based systems are leakage current and power dissipation. A transistor resizing approach for 10 transistor single bit full adder cells is used to determine optimal sleep transistor size which reduces power dissipation and leakage current. A submicron level 10-transistor single bit full adder cell is considered to achieve low leakage current, reduced power dissipation and high speed. In this paper initially 10T full adder cell is designed with submicron technique and later this is employed to design an ALU adder unit. The modified ALU is simulated and synthesized successfully on cadence 180nm technology.
A 20 gbs injection locked clock and data recovery circuitVLSICS Design
This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for burst mode
applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed CDR circuit leads to
higher speed operation and lower power consumption. In addition, to accommodate process, voltage, and
temperature (PVT) variations and to increase the lock range, a frequency locked loop is proposed to use in
this circuit. The circuit is designed in 0.18 μm CMOS and the simulations for 27-1 pseudo random bit
sequence (PRBS) show that the circuit consumes 55.3 mW at 20 Gb/s, while the recovered clock rms jitter
is 1.1 ps
PAM4 Analysis and Measurement Considerations WebinarHilary Lustig
This webinar explores the acquisition and analysis of PAM4 waveforms. We will show PAM4 Test Configurations, Compliance Measurements and Debug Techniques.
Design and Implementation of Submicron Level 10T Full Adder in ALU Using Cell...IJERA Editor
As technology scales into the nanometer regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex circuits. The main concern in mobile and battery based systems are leakage current and power dissipation. A transistor resizing approach for 10 transistor single bit full adder cells is used to determine optimal sleep transistor size which reduces power dissipation and leakage current. A submicron level 10-transistor single bit full adder cell is considered to achieve low leakage current, reduced power dissipation and high speed. In this paper initially 10T full adder cell is designed with submicron technique and later this is employed to design an ALU adder unit. The modified ALU is simulated and synthesized successfully on cadence 180nm technology.
A universal asynchronous receiver-transmitter is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable.
SDH (Synchronous Digital Hierarchy) & Its Architectureijsrd.com
The SDH (Synchronous Digital Hierarchy) tell us about transferring large amount of data over an same optical fiber and this document gives us the information about the structure and architecture of SDH.
Total slides: 73
Universal Asynchronous Receiver Transmitter (UART)
Introduction to Serial Communication
Types of Transmission
Simplex Communication
Duplex Communication
Half Duplex Communication
Full Duplex Communication
Methods of Serial data Transmission
Synchronous serial data transfer
Asynchronous serial data transfer
Differences Synchronous Asynchronous
Data Transfer Rate
Calculation of Baud Rate
SCON Register
SBUF Register
Writing to the Serial port
Reading the Serial port
PCON Register
Programming of transmission byte serially
Programming of reception of byte serially
Examples
Implementation of UART with Status Register using Multi Bit Flip-FlopIJMER
A UART (Universal Asynchronous Receiver and Transmitter) is a device allowing the
reception and transmission of information, in a serial and asynchronous way. This project focuses on
the implementation of UART with status register using multi bit flip-flop. During the reception of data,
status register indicates parity error, framing error, overrun error and break error.In modern very large
scale integrated circuits, Power reduction and area reduction has become a vital design goal for
sophisticated design applications. Multi-bit flip-flop is an effective power saving implementation
methodology by merging single bit flip-flops in the design. The underlying idea behind multi-bit flip-flop
method is to eliminate total inverter number by sharing the inverters in the flip-flops. Based on the
elimination feature of redundant inverters in merging single bit flip-flops into multi bit flip-flops, gives
reduction of wired length and this result in reduction of power consumption and area
Fast detection of number of antenna ports in lte systemeSAT Journals
Abstract
In LTE system, during initial cell selection UE is unaware about the number of antennas used by eNB for transmission. So, UE blindly tries multiple times to detect the right number of antennas used for transmission in the system. This wastes lot of time and UE processing power, as UE needs to do channel estimation, equalization/demodulation, decoding process multiple times with assumption of 1 or 2 and 4 antenna ports each time.
The objective of this paper is to find out a faster and efficient method for detecting the number of antenna ports used by the eNB for signal transmission. A new method is explored for detecting the number of eNB transmit antennas before starting PBCH decoding and CRC checking by exploiting the presence of downlink reference signals at various Resource Element (RE) positions in the Resource Blocks (RB) and using the PBCH SFBC data patterns. This helps for faster detection of number of antennas used for transmission that in turn helps to reduce the UE power consumption as well as reduces the initial cell search time.
Keywords: UE- User Equipment, LTE- Long-Term Evolution, eNB- evolved Node B, RAT- Radio Access Technology, PBCH- Physical Broadcast Channel, SFBC- Space Frequency Block Codes, DL – Down Link.
The Master Information Block (MIB), which includes a limited number of the most frequently transmitted parameters which are essential for a UE’s initial access to the network.
System Information Block Type 1 (SIB1), which contains parameters needed to determine if a cell is suitable for cell selection, as well as information about the time domain scheduling of the other SIBs.
System Information Block Type 2 (SIB2), which includes common and shared channel information
The paper introduces a multi-pass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.
Performance Evaluation of IEEE STD 802.16d TransceiverIOSR Journals
WiMAX ("Worldwide Interoperability for Microwave Access") technology is developed to meet the
growing demand of increased data rate and accessing the internet at high speeds. 802.16 family of standards is
officially called Wireless MAN in IEEE. Orthogonal frequency division multiplexing (OFDM) is multicarrier
modulation technique used in IEEE 802.16d (fixed WiMAX) communication standard. OFDM is used to
increase data rate of wireless medium with higher spectral efficiency. The proposed work is to evaluate
performance of IEEE Std 802.16d transceiver in MATLAB R2009b simulink environment. System performance
evaluated using BER vs SNR for different modulation technique such as 4 QAM, 16 QAM, 64 QAM under
different channel condition
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A universal asynchronous receiver-transmitter is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable.
SDH (Synchronous Digital Hierarchy) & Its Architectureijsrd.com
The SDH (Synchronous Digital Hierarchy) tell us about transferring large amount of data over an same optical fiber and this document gives us the information about the structure and architecture of SDH.
Total slides: 73
Universal Asynchronous Receiver Transmitter (UART)
Introduction to Serial Communication
Types of Transmission
Simplex Communication
Duplex Communication
Half Duplex Communication
Full Duplex Communication
Methods of Serial data Transmission
Synchronous serial data transfer
Asynchronous serial data transfer
Differences Synchronous Asynchronous
Data Transfer Rate
Calculation of Baud Rate
SCON Register
SBUF Register
Writing to the Serial port
Reading the Serial port
PCON Register
Programming of transmission byte serially
Programming of reception of byte serially
Examples
Implementation of UART with Status Register using Multi Bit Flip-FlopIJMER
A UART (Universal Asynchronous Receiver and Transmitter) is a device allowing the
reception and transmission of information, in a serial and asynchronous way. This project focuses on
the implementation of UART with status register using multi bit flip-flop. During the reception of data,
status register indicates parity error, framing error, overrun error and break error.In modern very large
scale integrated circuits, Power reduction and area reduction has become a vital design goal for
sophisticated design applications. Multi-bit flip-flop is an effective power saving implementation
methodology by merging single bit flip-flops in the design. The underlying idea behind multi-bit flip-flop
method is to eliminate total inverter number by sharing the inverters in the flip-flops. Based on the
elimination feature of redundant inverters in merging single bit flip-flops into multi bit flip-flops, gives
reduction of wired length and this result in reduction of power consumption and area
Fast detection of number of antenna ports in lte systemeSAT Journals
Abstract
In LTE system, during initial cell selection UE is unaware about the number of antennas used by eNB for transmission. So, UE blindly tries multiple times to detect the right number of antennas used for transmission in the system. This wastes lot of time and UE processing power, as UE needs to do channel estimation, equalization/demodulation, decoding process multiple times with assumption of 1 or 2 and 4 antenna ports each time.
The objective of this paper is to find out a faster and efficient method for detecting the number of antenna ports used by the eNB for signal transmission. A new method is explored for detecting the number of eNB transmit antennas before starting PBCH decoding and CRC checking by exploiting the presence of downlink reference signals at various Resource Element (RE) positions in the Resource Blocks (RB) and using the PBCH SFBC data patterns. This helps for faster detection of number of antennas used for transmission that in turn helps to reduce the UE power consumption as well as reduces the initial cell search time.
Keywords: UE- User Equipment, LTE- Long-Term Evolution, eNB- evolved Node B, RAT- Radio Access Technology, PBCH- Physical Broadcast Channel, SFBC- Space Frequency Block Codes, DL – Down Link.
The Master Information Block (MIB), which includes a limited number of the most frequently transmitted parameters which are essential for a UE’s initial access to the network.
System Information Block Type 1 (SIB1), which contains parameters needed to determine if a cell is suitable for cell selection, as well as information about the time domain scheduling of the other SIBs.
System Information Block Type 2 (SIB2), which includes common and shared channel information
The paper introduces a multi-pass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.
Performance Evaluation of IEEE STD 802.16d TransceiverIOSR Journals
WiMAX ("Worldwide Interoperability for Microwave Access") technology is developed to meet the
growing demand of increased data rate and accessing the internet at high speeds. 802.16 family of standards is
officially called Wireless MAN in IEEE. Orthogonal frequency division multiplexing (OFDM) is multicarrier
modulation technique used in IEEE 802.16d (fixed WiMAX) communication standard. OFDM is used to
increase data rate of wireless medium with higher spectral efficiency. The proposed work is to evaluate
performance of IEEE Std 802.16d transceiver in MATLAB R2009b simulink environment. System performance
evaluated using BER vs SNR for different modulation technique such as 4 QAM, 16 QAM, 64 QAM under
different channel condition
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Spur Reduction Of MB-OFDM UWB System using CMOS Frequency SynthesizerIDES Editor
As Technology progress deeper into submicron
CMOS, traditional analog circuits face problems that are
not to be solved purely by analog innovations. Instead,
new architectures are being proposed which take advantages
of the relatively cheaper of the digital circuits to augment or
improve the diminishing performance of the analog
circuitry. The conventional approach performs the design of
14 bands CMOS frequency synthesizers with spur reduction
for MB-OFMD for analog circuits which have high
distortions and noise. My proposed work is to replace the
analog input PLL into All Digital PLL with spur reduction.
Then the frequency mixing architecture alleviates
harmonics mixing and pulling to diminish spur
generation. The simulation is performed using Model SIM
and the implementation using Microwind to diminish spur
reduction.
Duty Cycle Corrector Using Pulse Width ModulationVLSICS Design
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW.
International Journal of VLSI design & Communication Systems (VLSICS) VLSICS Design
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW.
DUTY CYCLE CORRECTOR USING PULSE WIDTH MODULATIONVLSICS Design
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with
respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much
necessary to see to it that the clock signals are properly received specially in receiver circuits where data
sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew,
interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that
ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed
and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency
range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power
consumption is 1.01mW.
250 MHz Multiphase Delay Locked Loop for Low Power Applications IJECEIAES
Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8 V . It has power consumption of 1.39 mW at 125 center frequency with locking range from 0.5 MHz to 250 MHz . MHz
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
In this paper, we use the SV1C Personalized SerDes Tester to
rapidly develop and execute PLL Jitter transfer function measurements.
We leverage the integrated nature of the tool and its automation features to develop tests, execute scripts, and generate automatic reports in minutes.
The paper is organized as follows.
- The definition of jitter transfer and its relevance to high-speed standards is first presented.
- We then describe the measurement concept used in this paper and construct a very simple Introspect ESP Test Procedure for the automatic collection of PLL jitter transfer functions and loop
bandwidth parameters.
- We then describe advanced topics related to min-max VCO testing, time-domain testing, and linearity.
DESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCOVLSICS Design
In order to keep electronic world properly PLL plays a very important role. Designing of low
phase noise and less jittery PLL in generation of clock signals is an important task. Clock signals
are required for providing reference timing to electrical system and also to ICs. So in this paper
PLL is designed with improved Phase noise and also jitter. Where such types of design is
important when sophisticated timing requirements are needed to provide synchronization and
distribution of clocks like in ADC, DAC, high speed networking, medical imaging systems. The
clock signal’s quality depends upon jitter and phase noise. An ideal clock source has zero phase
noise and jitter but in reality it has some modulated phase noise. This modulated phase noise
spreads the power to the adjacent frequencies, hence produces noise sidebands. The phase noise
is typically frequency domain analysis which is expressed in terms of dBc/Hz measured at offset
frequency with respect to ideal clock frequency. The low phase noise is important factor mainly
in RF and ADC applications. In RF wireless high speed applications, increased PN will leads to
channel to channel interference, attenuates quality of signal. In ADC, increased PN limits the
SNR and data converter’s equivalent no. of bits (ENOB). Jitter is time domain meas
DESIGN AND PERFORMANCE ANALYSIS OF NINE STAGES CMOS BASED RING OSCILLATORVLSICS Design
This paper deals with the design and performance analysis of a ring oscillator using CMOS 45nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS) very large scale integrated circuits (VLSI) is a challenging task for the integrated circuit(IC) designer. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose output oscillates between two voltage levels representing high and low. There are a number of challenges ahead while designing the CMOS Ring Oscillator which are delay, noise and glitches. CMOS is the technology of choice for many applications, CMOS oscillators with low power, phase noise and timing jitter are highly desired. In this paper, we have designed a CMOS ring oscillator with nine stages.Previously, the researchers were unable to reduce the phase noise in ring oscillators substantially with nine stages. We have successfully reduced the phase noise to -6.4kdBc/Hz at 2GHz center frequency of oscillation.
DESIGN OF LOW POWER PHASE LOCKED LOOP (PLL) USING 45NM VLSI TECHNOLOGYVLSICS Design
Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core of a microprocessor, which includes the largest power density on the microprocessor. In an effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. Lowering the supply voltage, however, also reduces the performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available in some application domains, is to replicate the circuit block whose supply voltage is being reduced in order to maintain the same throughput .This paper introduces a design aspects for low power phase locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. The main novelty related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD, practical experience in layout design
Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology VLSICS Design
Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core of a microprocessor, which includes the largest power density on the microprocessor. In an effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. Lowering the supply voltage, however, also reduces the performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available in some application domains, is to replicate the circuit block whose supply voltage is being reduced in order to maintain the same throughput .This paper introduces a design aspects for low power phase locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. The main novelty related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD, practical experience in layout design
DESIGN OF LOW POWER PHASE LOCKED LOOP (PLL) USING 45NM VLSI TECHNOLOGYVLSICS Design
Power has become one of the most important paradigms of design convergence for multi
gigahertz communication systems such as optical data links, wireless products, microprocessor &
ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core
of a microprocessor, which includes the largest power density on the microprocessor. In an effort to
reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of
dynamic and static power consumption. Lowering the supply voltage, however, also reduces the
performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available
in some application domains, is to replicate the circuit block whose supply voltage is being reduced in
order to maintain the same throughput .This paper introduces a design aspects for low power phase
locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process
technology parameters, which in turn offers high speed performance at low power. The main novelty
related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect
dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit
parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,
translation onto silicon, CAD, practical experience in layout design
A miniature tunable quadrature shadow oscillator with orthogonal control IJECEIAES
This article presents a new design of a quadrature shadow oscillator. The oscillator is realized using one input and two outputs of a second-order filter cell together with external amplifiers in a feedback configuration. The oscillation characteristics are controlled via the external gain without disturbing the internal filter cell, following the concept of the shadow oscillator. The proposed circuit configuration is simple with a small component-count. It consists of, two voltage-different transconductance amplifiers (VDTAs) along with a couple of passive elements. The frequency of oscillation (FO) and the condition of oscillation (CO) are controlled orthogonally via the dc bias current and external gain. Moreover, with the addition of the external gain, the frequency range of oscillation can be further extended. The proposed work is verified by computer simulation with the use of 180 nm complementary metal–oxide–semiconductor (CMOS) model parameters. The simulation gives satisfactory results of two sinusoidal output signals in quadrature with some small total harmonic distortions (THD). In addition, a circuit experiment is performed using the commercial operational transconductance amplifiers LM13700 as the active components. The circuit experiment also demonstrates satisfactory outcome which confirms the validity of the proposed circuit.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
CMOS ring oscillator delay cell performance: a comparative studyIJECEIAES
A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell.
Similar to A 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUIT (20)
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
A 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUIT
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
DOI : 10.5121/vlsic.2014.5401 1
A 20 Gb/s INJECTION-LOCKED CLOCK AND
DATA RECOVERY CIRCUIT
Sara Jafarbeiki1
, Dr Khosrow Hajsadeghi2
and Naeeme Modir3
1,2
Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran
3
School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
ABSTRACT
This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for burst mode
applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed CDR circuit leads to
higher speed operation and lower power consumption. In addition, to accommodate process, voltage, and
temperature (PVT) variations and to increase the lock range, a frequency locked loop is proposed to use in
this circuit. The circuit is designed in 0.18 µm CMOS and the simulations for 27
-1 pseudo random bit
sequence (PRBS) show that the circuit consumes 55.3 mW at 20 Gb/s, while the recovered clock rms jitter
is 1.1 ps.
KEYWORDS
Clock and data recovery, eye diagram, injection-locked, lock range, oscillator
1. INTRODUCTION
For the burst-mode applications such as passive optical network (PON) [1, 2], the CDR circuit in
the receiver must lock to each burst data packet very quickly. In a PON system, the optical line
termination (OLT) receives data packets from various optical network units (ONUs) and these
data packets have different phase and amplitude, so immediate clock extraction and data retiming
in the CDR circuit is necessary.
The conventional PLL-based CDR circuit requires a long sequence of bits to settle, hence is not
suitable for burst-mode applications. Fast locking capability of open-loop CDR circuits [3]-[8]
makes them attractive solutions for these applications. However, open loop CDRs suffer from
limited frequency tracking range and high jitter transfer [9]. Jitter transfer is not a serious issue
for applications where no repeater is required [3], hence, open-loop CDRs are appropriate for
such applications.
In open-loop CDR circuits, a gated voltage-controlled oscillator (GVCO) [3]-[5] or an injection-
locked oscillator (ILO) [6]-[8] can usually be used. GVCOs have higher phase noise than LC
VCOs because of their ring structure. So, using GVCO, in general, leads the recovered clock
showing larger jitter than using ILO. Also the operation speed of GVCOs is lower than ILOs [5].
An injection-locked oscillator uses an LC type VCO which has better phase noise and higher
operation speed in comparison with ring oscillator.
A CDR circuit using injection-locking technique is described in [6], in which using two cascaded
voltage-controlled LC oscillators as a full-rate CDR forces the use of an edge detector circuit.
Both VCOs are injection-locked to the input data and the edge detector design needs high speed
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
2
current mode logic (CML) XOR and delay buffer circuits. Also the reference PLL which is used
to overcome the process, supply voltage, and temperature (PVT) variations consists of a VCO
which must be an exact duplicate of the main VCOs, otherwise the PLL provides an inaccurate
control voltage which is not suitable to use for main VCOs. In this paper, a high speed injection-
locked CDR is proposed which has several advantages over current designs. Utilizing a novel
injection-locked oscillator structure and using an appropriate injection method in the proposed
CDR circuit leads to higher speed operation by eliminating the edge detector circuit and by
sampling the data with a half rate clock. In addition, a new approach instead of a reference PLL is
proposed to accommodate PVT variations which forces the free-running frequency of the ILO to
track the data rate by adding or removing some of the utilized capacitors to the ILO structure. A
20 Gb/s open-loop CDR circuit is designed and simulated in 0.18 µm CMOS technology for
burst-mode applications, which consumes less than 55.3 mW from a 1.8 V supply.
The rest of the paper is organized as follows. Section II describes the CDR topology and
architecture. Section III presents the building blocks utilized in the circuit. Section IV describes
the simulations and summarizes the results, and finally section V concludes the paper.
2. THE PROPOSED CDR
Figure. 1 shows the proposed CDR architecture. The circuit is composed of an injection-locked
LC oscillator, a clock buffer and two retiming flip flops. In addition, to track the frequency of
oscillator a divider chain, a frequency detector (FD), and a counter are used in this structure. Input
data is injected to the ILO to provide an aligned clock. The recovered clock is applied to a clock
buffer which in turn drives two flip flops in the decision circuit to recover the data.
As the injection locking technique has narrow locking range, the ILO may not lock to the
frequency of the incoming data stream if it is not properly controlled. Furthermore, the PVT
variations may also cause ILO to lose lock. In the proposed architecture a frequency locked loop
is used to compensate for these problems. The clock frequency is divided by 40 and then applied
to a frequency detector as shown in Fig. 1. In the frequency detector, this signal is compared to a
reference frequency of 250 MHz. The frequency detector produces an output based on whether
fref > fdivider or not. This signal is then applied to a counter as to determine up or down counting.
The frequency detector circuit also produces another signal whose frequency is dependent on the
difference between fref and fdivider. This signal is applied to the counter as its clock and it
determines the speed of counting. Thus, counter can count up or down depending on the
frequency of ILO in comparison to the reference frequency and then add some capacitors to ILO
or remove them from it. The counter does this through the control of a few switches which are
connected to the capacitors. By using this method the lock range of the circuit is increased
considerably.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
3
Figure. 1 The Proposed CDR Architecture
2.1. Frequency tracking
As locking range of the ILO is narrow, a frequency locked loop (FLL) is required to set the
oscillator frequency in the locking range. We propose a method to track the oscillator frequency
and bring it within the appropriate range. The proposed FLL uses a divider chain, a frequency
detector and an up/down counter. The output frequency of the oscillator is divided by 40 and then
is applied to a frequency detector. The frequency detector circuit is shown in Figure. 2 which is a
rotational frequency detector circuit [10]. It compares the divider output frequency with a
reference frequency of 250 MHz and produces an up/down signal and a clock for the counter. In
this circuit the ILO output clock which is composed of CKi and CKq, are sampled by the
reference clock, producing two outputs Q1 and Q2. Leading or lagging of Q1 from Q2 shows the
polarity of the frequency error (fig. 2(b)). The FD’s output, Q3, is applied to the counter and
forces the counter to count up or down depending on the frequency error’s polarity. Fig. 2(c)
shows the states of Q1 and Q2, where the sign of beat frequency is indicated by the rotating
direction.
(a)
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
4
(b)
(c)
Figure. 2 (a) Frequency detector circuit. (b) FD operation. (c) States of (Q1, Q2) [10]
3. BUILDING BLOCKS
3.1. ILO
Fig. 3 shows the designed super harmonic injection-locked LC oscillator which is used as a half
rate CDR circuit in this paper. In this structure the data is injected into the ILO directly, instead of
applying it to an edge detector. The M1 and M2 create an incident current at the rising and falling
edge of the data, respectively. As a result, at every edge of the data the differential output of the
oscillator will be shorted. The main advantages of this structure are low power consumption and
the reduction of the maximum operational frequency to half of the other state of the art structures
in the literature.
As mentioned before, capacitors with switches are incorporated in the ILO to overcome PVT
variations. By switching these capacitors in or out of the ILO structure, the ILO’s output
frequency is brought to its locking range. So, the ILO can lock to the injected input data.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
5
Figure. 3 Injection-locked LC oscillator with utilized capacitors
Since the lock range for this ILO is around 150MHz, the frequency shift in ILO’s output
frequency for each added or removed capacitor is designed to be 100 MHZ. The capacitor values
can be calculated from the following equation.
0
0
0
0 0
1 1 1 1
( )
(1 ) (1 )
out
eq
f f
LC L C C C C
LC
C C
= = = =
+ ∆ ∆ ∆
+ + (1)
Where fout is the ILO output frequency, f0 is the ILO free-running frequency, Ceq is the total
capacitance, C0 is parasitic capacitance of ILO, and C∆ is the capacitance value change for each
step of counting. For example, when the counter has the value of three, the transistors q0, q1 are
on and the capacitors C1, C2 are connected to the ILO. When the counter counts up and changes to
four, the transistors q0, and q1 turn off and q2 turns on hence, the capacitors C3 are connected to
the ILO. So, for this step of counting ∆C=C3-(C1+C2). The values of C1, C2, C3, C4 are chosen
such that the change in the value of capacitors connected to the ILO for each step of counting,
∆C, to be constant.
(2)
0 02
f C
f C
∆ ∆
⇒ = (3)
It is clear that the capacitors values can be calculated easily for a certain frequency shift and a
given free-running frequency of ILO.
3.2. Clock buffer
In order to isolate the capacitive loading of the next stage on the ILO, we use the clock buffer
which is shown in Fig. 4. The bandwidth limitation in conventional CML buffers with resistive
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
6
loads leads to limited output voltage swings. In order to increase signal swing and to solve the
bandwidth limitation problem, we can use the inductive peaking technique. We choose the
inductor and resistor values to adjust the buffer delay such that the phase difference between the
input data and the clock to be equal to 90 ̊ and, as a result the clock edges align with the center of
the input data eye.
Figure. 4 Clock buffer
3.3. Flipflop
We can classify flipflops into two categories: static and dynamic. Although the static latches can
operate in higher speeds, they consume more power in contrast to their dynamic counterparts. We
use the static flipflops only in situations that we need the fast operation, such as decision circuits
and first stages of divider. The dynamic flipflops are used in all other situations, such as next
stages of the divider and frequency detector circuit, to reduce the power consumption. The details
of these two types of flipflops are described as follows.
3.3.1. Static Flipflop
The CML topology is used in our design because it can speed up the operation to some extent.
The CML circuit operation is fast, because they have lower output voltage swing compared to the
static CMOS circuits. We also use inductive peaking technique similar to [11, 12] which
improves the speed of CML circuits by extending the bandwidth.
Fig.5 shows the designed CML latch circuit.
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
7
Figure. 5 The designed CML latch circuit
3.3.2. Dynamic Flipflop
As mentioned before, the dynamic flipflop shown in Fig. 6 is used to reduce the power
consumption in situations where we do not need fast operation speed [13].
CLK
CLK
CLK CLK
D
Q Q
Figure. 6 Dynamic latch circuit
We have also depicted a dynamic divider in Fig. 7 which is used in the next stages of the divider
chain. This dynamic divider consumes less power than CML ones. This structure is made of two
consecutive D flipflops which are dynamic latches that sample the data in every rising edge of the
clock.
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
8
Figure. 7 Dynamic divider
3.4. Counter circuit
For turning the switches, used in the injection locked oscillator, on and off, a 4-bit up/down
counter is utilized which is shown in Fig. 8 [14] This counter receives its clock and control inputs,
which determines the up or down counting state, from the frequency detector circuit.
Figure. 8 Up/Down Counter circuit [14]
4. SIMULATION RESULTS
The proposed circuit has been designed and simulated in a 0.18 µm CMOS technology. This
circuit consumes 55.3mW from a 1.8V supply voltage, where the most of it is consumed in the
CML circuits. The input data is shown in Fig. 9 and the recovered data in response to a 27
-1
continuous mode PRBS is shown in Fig. 10. The simulated jitter values for the recovered data are
6 ps, pp and 1.3 ps, rms. The recovered clock is shown in Fig. 11. The simulated peak-to-peak
and rms jitters for the recovered clock are 4.8 ps and 1.1ps, respectively. The ILO locking range
of 150MHz is achieved. By using the frequency locked loop, the locking range of the CDR circuit
is extended to 1.5 GHz. The CDR circuit recovers the data in less than 50 ps which is equal to 1
bit. Fig. 12 shows this fast locking time.
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
9
-0 20 40 60 80 100-20 120
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
-0.8
0.8
time, psec
Amplituade,V
Figure. 9 Data eye diagram at the CDR input
0
20
40
60
80
100
120
140
160
180
200
-20
220
-0.5
0.0
0.5
-1.0
1.0
time, psec
RecoveredData,V
Figure. 10 Data eye diagram at the receiver output
Figure. 11 Recovered clock with 27
-1 PRBS input data
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
10
1.1
0.6
1.6
InputData,V
1.2
0.5
1.9
OutputData1
1.2
0.5
1.9
OutputData2
5 6 74 8
1.0
0.0
1.6
time, nsec
RecoveredClock,V
Figure. 12 Simulated input and output waveforms
Fig.13 depicts the FD outputs, and it shows that when the ILO locks to the input data the FD does
not create any clock pulses for the counter. It means that after lock, the CLK becomes constant,
hence the counter does not count anymore and it shows that the CDR circuit is locked to the input
data.
0
1
-1
2
Up/Down
0.2 0.4 0.6 0.8 1.0 1.2 1.40.0 1.6
0
1
-1
2
time, usec
CLK
Figure. 13 FD output waveforms
The circuit is simulated in different process corners, temperatures and supply voltages. At the
slow/slow process corner, 70◦ C and 1.65V, the rms jitter of the recovered clock is 1.33 ps. The
consumed power in this situation is 47 mW and the circuit locks after 1 bit. At the fast/fast corner,
−20◦ C and 1.95 V, the rms jitter of the recovered clock is 1.12 ps and the consumed power is
70.2mW and the circuit locks after 1 bit.
11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
11
Table 1 summarizes and compares the performance of this work and some other burst mode
CDRs recently published. The operation range and the speed of the proposed circuit, while it uses
a technology of 0.18µm CMOS, have been improved over recently reported structures.
Table 1. The simulation result of the proposed CDR compared with similar work
5. CONCLUSIONS
This work proposes a 20 Gb/s CDR circuit for burst mode applications which is designed and
simulated in a 0.18µm CMOS process. The CDR employs a super harmonic injection-locked
oscillator, hence frequency of the oscillator is reduced to the half of the bit rate and two flip flops
are needed for sampling the data with the half rate clock. With the help of the proposed frequency
tracking technique, the circuit accommodates frequency deviations caused by PVT variations. In
fact, the simulation results demonstrate that the CDR circuit provides a truly wide operation range
(1.5GHz) with reasonably low power consumption.
[6] [15] [16] [17] [18] This
work
Data rate 20 Gb/s 10 Gb/s 71 Gb/s 1.3-5.2
Gb/s
30 Gb/s 20 Gb/s
Recovered
clock jitter
1.2 ps.rms
(with 27
-1
PRBS)
8.5 ps.rms
(with 27
-1
PRBS)
N/A 0.82 ps.rms
(with 27
-1
PRBS)
4 ps.rms 1.1 ps.rms
(with 27
-1
PRBS)
Operation
range
800 MHz 600 MHz N/A N/A N/A 1.5 GHz
Locking time 1 UI < 5 UI N/A < 20 UI N/A 1 UI
Supply
voltage
1.5 1.8 3.3 1.1 N/A 1.8
Power Diss. 175 mW 36 mW 0.5 W 12.4 mW 210 mW 55.3 mW
Technology 90 nm
CMOS
0.18 µm
CMOS
0.18 µm
SiGe
40 nm
CMOS
65 nm
CMOS
0.18 µm
CMOS
Simulation/
Measurement
12. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
12
REFERENCES
[1] ‘‘G.984.2 Gigabit-capable passive optical networks (GPON): Physical media dependent (PMD) layer
specification’’, ITU-T, 2003.
[2] C. Liang and S. Liu, “A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using
GVCO/Div2/DFF Tri-mode Cells,” ISSCC Dig. Tech. Papers, pp. 224-608, Feb., 2008.
[3] P. Han and W. Y. Choi, “1.25/2.5-Gb/s dual bit-rate burst-mode clock recovery circuits in 0.18-m
CMOS technology,” in IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 54, pp. 38-
42, Jan. 2007.
[4] M. Nogawa et al., “A 10 Gb/s burst-mode CDR IC in 0.13 µm CMOS,” in IEEE ISSCC Dig. Tech.
Papers, Feb. 2005, pp. 228–229.
[5] Kaeriyama, S. and Mizuno, M., "A 10Gb/s/ch 50mW 120×130µm clock and data recovery circuit", in
Proc. ISSCC, February 2003.
[6] J. Lee, M. Liu, “A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique”, ISSCC, pp
586, Feb 2007.
[7] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power
frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170–1174, Jul. 2004.
[8] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol.
39, no. 9, pp. 1415–1424, Sep. 2004.
[9] M. Hsieh and G. E. Sobelman, “Architectures for Multi-GigabitWire-Linked Clock and Data
Recovery,”IEEE Circuits and Systems Magazine, vol. 8, no. 4, pp. 45-57, Fourth Quarter 2008.
[10] Jri Lee and Ke-Chung Wu " A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With
Automatic Frequency Acquisition," IEEE Journal of Solid-State Circuits (December 2009), 44 (12),
pg. 3590-3602
[11] Terada J, Ohtomo Y, Nishimura K, Katsurai H, Kimura S, Yoshimoto N. Jitter-reduction and pulse-
width-distortion compensation circuits for a 10gb/s burst-mode cdr circuit. In: IEEE ISSCC Dig.
Tech. Papers. San Francisco; 2009, p. 104 –105,105a.
[12] Y. T. Chen, M. W. Li, T. H. Huang, and H. R. Chuang, “A V-band CMOS direct injection-locked
frequency divider using forward body bias technology,” IEEE Microw. Wireless Compon. Lett., vol.
20, no. 7, pp. 396-398, Jul. 2010.
[13] B. Razavi, et al., “Design of high-speed, low-power frequency dividers and phase locked loops in
deep submicron CMOS,” IEEE J. Solid-State Circuits, vol. 30, pp. 101–109, Feb. 1995.
[14] Mircea R. Stan, Alexandre F. Tenca and Milos D. Ercegovac, “Long and Fast Up/Down Counters,”
IEEE Transactions on Computers, vol., 47, no. 7, July, 1998.
[15] Che-Fu Liang, Hong-Lin Chu, and Shen-Iuan Liu, "10Gbps inductorless CDRs with digital frequency
calibration", IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 55, pp. 2514-2524, Oct. 2008.
[16] T. S. Mukherjee, M. Omer, J. Kim, Design and Optimization of a 71 Gb/s Injection-locked CDR.
ISCAS 2009: 177-180
[17] K. Maruko, T. Sugioka, H. Hayashi, Zhiwei Zhou, Y. Tsukuda, Y. Yagishita, H.Konishi, T. Ogata, H.
Owa, T. Niki, K. Konda, M. Sato, H. Shiroshita, T. Ogura, T.Aoki, H. Kihara, and S. Tanaka, “A
1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s)Burst Mode CDR Using Dual-Edge Injection-
Locked Oscillator,” ISSCCDig. Tech. Papers, pp. 364-365, Feb. 2010.
[18] Y. Take, N. Miura, and T. Kuroda, “A 30 Gb/s/link 2.2 Tb/s/mm2 inductively-coupled injection-
locking CDR for High-Speed DRAM Interface,” IEEE Journal of Solid-State Circuits (JSSC), vol. 46,
pp. 2552-2558, NOV. 2011.