This document discusses code generation in compilers. It covers:
- The code generator takes an intermediate representation and produces target code that is correct and efficient for the target machine.
- Symbol tables are used to track variable semantics, data types, scopes, and storage addresses. Common implementations are unordered lists and ordered linear lists.
- The target machine format can be absolute machine language, relocatable machine language, or assembly language. Memory management involves mapping names to runtime memory addresses.
- Basic blocks, control flow graphs, and structure-preserving transformations like common subexpression elimination are discussed for code optimization.
this slide is for to understand the conditions which are applied in C++ programming language. I hope u would understand better by viewing this presentation.
this slide is for to understand the conditions which are applied in C++ programming language. I hope u would understand better by viewing this presentation.
In this slide you will explore more about how to make derivations ,design parse tree ,what is ambiguity and how to remove ambiguity ,left recursion ,left factoring .
Lexical Analysis, Tokens, Patterns, Lexemes, Example pattern, Stages of a Lexical Analyzer, Regular expressions to the lexical analysis, Implementation of Lexical Analyzer, Lexical analyzer: use as generator.
In this slide you will explore more about how to make derivations ,design parse tree ,what is ambiguity and how to remove ambiguity ,left recursion ,left factoring .
Lexical Analysis, Tokens, Patterns, Lexemes, Example pattern, Stages of a Lexical Analyzer, Regular expressions to the lexical analysis, Implementation of Lexical Analyzer, Lexical analyzer: use as generator.
Penn
State
University
School
of
Electrical
Engineering
and
Computer
Science
Page
1
of
4
CMPEN
331
–
Computer
Organization
and
Design,
Lab
6
Due
Wednesday
April
26,
2017
at
7:00
am
(Drop
box
on
Canvas)
This lab introduces the idea of the pipelining technique for building a fast CPU. The students will obtain
experience with the design implementation and testing of the first four stages (Instruction Fetch, Instruction
Decode, Instruction Execute, Memory) of the five-stage pipelined CPU using the Xilinx design package for
FPGAs. It is assumed that students are familiar with the operation of the Xilinx design package for Field
Programmable Gate Arrays (FPGAs) through the Xilinix tutorial available in the class website.
1. Pipelining
As described in lab 4
2. Circuits of the Instruction Fetch Stage
As described in lab 4
3. Circuits of the Instruction Decode Stage
As described in lab 4
4. Circuits of the Execution Stage
As described in lab 5
5. Circuits of the Memory Access Stage
As described in lab 5
6. Circuits of the Write Back Stage
Referring to Figure 1, in the fifth cycle the first instruction entered the WB stage. The memory data is selected
and will be written into the register file at the end of the cycle. All the control signal have a prefix “w”. The
second instruction entered the MEM stage; the third instruction entered the EXE stage; the fourth instruction is
being decoded in the ID stage; and the fifth instruction is being fetched in the IF stage. All the six pipeline
registers are updated at the end of the cycle (the destination register is considered as the six pipeline register).
Then the first instruction is committed. In each of the forth coming clock cycles, an instruction will be commited
and a new instruction will enter the pipeline. We use the structure shown in Figure 1 as a baseline for the design
of our pipelined CPU.
Penn
State
University
School
of
Electrical
Engineering
and
Computer
Science
Page
2
of
4
Figure 1 Pipeline write back (WB) stage
7. Table 1 lists the names and usages of the 32 registers in the register file.
Table 1 MIPS general purpose register
$zero 0 Constant 0
$at 1 Reserved for assembler
$v0, $v1 2, 3 Function return values
$a0 - $a3 4 – 7 Function argument values
$t0 - $t7 8 – 15 Temporary (caller saved)
$s0 - $s7 16 – 23 Temporary (callee saved)
$t8, $t9 24, 25 Temporary (caller saved)
$k0, $k1 26, 27 Reserved for OS Kernel
$gp 28 Pointer to Global Area
$sp 29 Stack Pointer
$fp 30 Frame Pointer
$ra 31 Return Address
8. Table 2 lists some MIPS i.
CSCI 2121- Computer Organization and Assembly Language Labor.docxannettsparrow
CSCI 2121- Computer Organization and Assembly Language
Laboratory No. 5
Week of March 12th, 2018
Submission Instructions:
1. Save the files as shift.sv and vending.sv
2. Put all files into one folder.
3. Compress the folder into a .zip file.
4. Submit the zip file on Brightspace.
5. Submission Deadline: Sunday, April 15th, 2018, 11.55PM
SRC CHIP PROJECT
In order to proceed on the project for this course, there are several key Verilog concepts which are
necessary in the implementation of this code.
Part 0: More Verilog concepts.
Shared busses and tri-state buffers
Before we begin implementing the CPU, let's go over a few concepts which will be needed for the lab
assignment. The first is the concept of a shared bus. We've already seen busses in Verilog in terms of an
array of wires or registers, however in the context of our CPU, the word "bus" has another meaning. Our
CPU uses a shared "bus" which is a wire connected between the inputs and outputs of many different
registers, in order to share data:
This can be easily modelled in Verilog, using the inout keyword for a module. This defines a wire which
can act as both an input and an output to our module. However, there is one critically important design
concept which goes along with the usage of shared busses:
Only one signal can be written to a shared bus at any given time.
If two signals are written to the bus, the result is a bus collision, and the value is undefined. In the
simulation, this is represented as "X", but in real life this would cause garbage data to exist on the bus,
potentially corrupting any process which is running on the CPU. As Verilog programmers, it's our job to
ensure that a bus collision never happens. To facilitate this, we'll use a digital logic component called a
tri-state buffer:
The purpose of a tri-state buffer is to act as a switch. If B is 1, then the data can pass through the buffer,
but if not, it simply disconnects the wire, outputting a high-impedance state (in Verilog, denoted by Z).
hz943141
A B C
0 0 Z
0 1 0
1 0 Z
1 1 1
In Verilog, we can't directly write a tri-state buffer, but it can be easily synthesized using a ternary
operator as shown on line 11:
Line 11 shows the construction of a ternary operator to use as a tri-state buffer. If the input called
activate_out is set to 1, then the tri-state buffer is activated, and the circuit will put my_result on the
bus. Otherwise, it puts the value 32'bz on the bus, which will disconnect my_result from the bus, and
allow another circuit to write to the bus.
Note: It is important that during your lab assignment, any circuits which write to the bus have a tri-
state buffer implemented to prevent bus collisions.
Verilog Tasks:
Verilog tasks are like object functions in Java. Read more about them here. You may find that they are
useful in separating the code for instructions within a module, particularly for th.
Passes in the compilers are the essential part in any system as it works with Phases.
Two main types of compiler are:- One pass or single pass and Two pass or multi pass compilers.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
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Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
2. CONTENTS
(a) Issues in the design of code generator
(b) The target machine
(c) Runtime Storage management
(d) Basic Blocks and Flow Graphs
(e) Next-use Information – A simple Code generator – DAG representation of
Basic Blocks – Peephole Optimization.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 2
3. CODE GENERATION
The final phase in our compiler model is the code generator. It takes as input
an intermediate representation of the source program and produces as output
an equivalent target program.
The requirements traditionally imposed on a code generator are
severe. The output code must be correct and of high quality, meaning that it
should make effective use of the resources of the target machine. Moreover,
the code generator itself should run efficiently
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 3
4. • Symbol table: A data structure used by a compiler to keep
track of
semantics of variables.
• Data type.
• When is used: scope.
The effective context where a name is valid.
• Where it is stored: storage address.
• Possible implementations:
• Unordered list: for a very small set of variables.
• Ordered linear list: insertion is expensive, but
implementation is
• relatively easy
ANKUR SRIVASTAVA ASSISTANT PROFESSOR
JIT
4
5. Data structure for symbol tables
• Possible entries in a symbol table:
• Name: a string.
• Attribute:
Reserved word
Variable name
Type name
Procedure name
Constant name
• Data type.
• Scope information: where it can be used.
• Storage allocation, size
ANKUR SRIVASTAVA ASSISTANT PROFESSOR
JIT
5
7. THE TARGET MACHINE
The output of the code generator is the target program. The output may take on
a variety of forms: absolute machine language, relocatable machine language,
or assembly language.
Producing an absolute machine language program as output has the advantage
that it can be placed in a location in memory and immediately executed. A
small program can be compiled and executed quickly. A number of “student-
job” compilers, such as WATFIV and PL/C, produce absolute code.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 7
8. MEMORY MANAGEMENT
Mapping names in the source program to addresses of data objects in run time
memory is done cooperatively by the front end and the code generator. We
assume that a name in a three-address statement refers to a symbol table entry
for the name.
If machine code is being generated, labels in three address
statements have to be converted to addresses of instructions. This process is
analogous to the “back patching”. Suppose that labels refer to quadruple
numbers in a quadruple array. As we scan each quadruple in turn we can
deduce the location of the first machine instruction generated for that
quadruple, simply by maintaining a count of the number of words used for the
instructions generated so far
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 8
9. INSTRUCTION SELECTION
The nature of the instruction set of the target machine determines the difficulty
of instruction selection. The uniformity and completeness of the instruction set
are important factors. If the target machine does not support each data type in a
uniform manner, then each exception to the general rule requires special
handling.
Instruction speeds and machine idioms are other important factors. If we do
not care about the efficiency of the target program, instruction selection is
straightforward. For each type of three- address statement we can design a
code skeleton that outlines the target code to be generated for that construct.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 9
10. REGISTER ALLOCATION
Instructions involving register operands are usually shorter and faster than
those involving operands in memory. Therefore, efficient utilization of register
is particularly important in generating good code. The use of registers is often
subdivided into two sub-problems:
1. During register allocation, we select the set of variables that will
reside in registers at a point in the program.
2. During a subsequent register assignment phase, we pick the specific
register that a variable will reside in.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 10
11. APPROCHES TO CODE GENERATION
The most important criterion for a code generator is that it produce correct
code. Correctness takes on special significance because of the number of
special cases that code generator must face. Given the premium on correctness,
designing a code generator so it can be easily implemented, tested, and
maintained is an important design goal
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 11
12. BASIC BLOCKS
A basic block is a sequence of consecutive statements in which
flow of control enters at the beginning and leaves at the end without halt or
possibility of branching except at the end. The following sequence of three-
address statements forms a basic block:
t1 := a*a
t2 := a*b
t3 := 2*t2
t4 := t1+t3
t5 := b*b
t6 := t4+t5
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 12
13. A three-address statement x := y+z is said to define x and to use y or z. A name
in a basic block is said to live at a given point if its value is used after that
point in the program, perhaps in another basic block.
The following algorithm can be used to partition a sequence of three-address
statements into basic blocks.
Algorithm 1: Partition into basic blocks.
Input: A sequence of three-address statements.
Output: A list of basic blocks with each three-address statement in exactly one
block.
For each leader, its basic block consists of the leader and all statements up to
but not including the next leader or the end of the program.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 13
14. Example 3: Consider the fragment of source code shown it computes the dot
product of two vectors a and b of length 20. A list of three-address statements
performing this computation on our target machine is.
begin
prod := 0;
i := 1;
do begin
prod := prod + a[i] * b[i];
i := i+1;
end
while i<= 20
end
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 14
15. Let us apply Algorithm 1 to the three-address code in fig 8 to determine its
basic blocks. statement (1) is a leader by rule (I) and statement (3) is a leader
by rule (II), since the last statement can jump to it. By rule (III) the statement
following (12) is a leader. Therefore, statements (1) and (2) form a basic block.
The remainder of the program beginning with statement (3) forms a second
basic block.
(1) prod := 0
(2) i := 1
(3) t1 := 4*i
(4) t2 := a [ t1 ]
(5) t3 := 4*i
(6) t4 :=b [ t3 ]
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 15
17. STRUCTURE-PRESERVING TRANSFORMATIONS
The primary structure-preserving transformations on basic blocks are:
1. common sub-expression elimination
2. dead-code elimination
3. renaming of temporary variables
4. interchange of two independent adjacent statements
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 17
18. 1. Common sub-expression elimination
Consider the basic block
a:= b+c
b:= a-d
c:= b+c
d:= a-d
The second and fourth statements compute the same expression,
namely b+c-d, and hence this basic block may be transformed into the
equivalent block
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 18
19. a:= b+c
b:= a-d
c:= b+c
d:= b
Although the 1st and 3rd statements in both cases appear to have the same
expression on the right, the second statement redefines b. Therefore, the value
of b in the 3rd statement is different from the value of b in the 1st, and the 1st
and 3rd statements do not compute the same expression.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 19
20. 2. Dead-code elimination
Suppose x is dead, that is, never subsequently used, at the point where the
statement x:= y+z appears in a basic block. Then this statement may be safely
removed without changing the value of the basic block.
3. Renaming temporary variables
Suppose we have a statement t:= b+c, where t is a temporary. If we change this
statement to u:= b+c, where u is a new temporary variable, and change all uses
of this instance of t to u, then the value of the basic block is not changed. In
fact, we can always transform a basic block into an equivalent block in which
each statement that defines a temporary defines a new temporary. We call such
a basic block a normal-form block.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 20
21. Interchange of statements
Suppose we have a block with the two adjacent statements
t1:= b+c
t2:= x+y
Then we can interchange the two statements without affecting the value of the
block if and only if neither x nor y is t1 and neither b nor c is t2. A normal-
form basic block permits all statement interchanges that are possible.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 21
22. ACTIVATION RECORD?
Information needed by a single execution of procedure is managed using a
contiguous block of storage called an activation record or frame. It is
customary to push the activation record of a procedure on the run time stack
when the procedure is called and to pop the activation record off the stack
when control returns to the caller.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 22
23. ACTIVATION TREES
A program is a sequence of instructions combined into a number of
procedures. Instructions in a procedure is executed sequentially. A procedure
have a start and an end delimiter and everything inside it is called the body of
the procedure. The procedure identifier and the sequence of finite instructions
inside it make up the body of the procedure.
The execution of a procedure is called its activation. An activation record
contains all the necessary information required to call a procedure. An
activation record may contain the following units (depending upon the source
language used).
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 23
24. To know this idea, an example:
printf(“Enter Your Name: “);
scanf(“%s”, username);
show_data(username);
printf(“Press any key to continue…”
int show_data(char *user)
{
printf(“Your name is %s”, username);
return 0;
}
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 24
25. Storage Allocation
Runtime environment manages runtime memory requirements for the following
entities:
Code : It is known as the text part of a program that does not change at runtime. Its
memory requirements are known at the compile time.
Procedures : Their text part is static but they are called in a random manner. That is
why, stack storage is used to manage procedure calls and activations.
Variables : Variables are known at the runtime only, unless they are global or constant.
Heap memory allocation scheme is used for managing allocation and de-allocation of
memory for variables in runtime.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 25