SlideShare a Scribd company logo
COMPILER DESIGN
UNIT-IV
SYMBOL TABLE
ANKUR SRIVASTAVA
ASSISTANT PROF.(CSE)
JETGI
31-Dec-16 1ANKUR SRIVASTAVA(CSE) JETGI
CONTENTS
(a) Issues in the design of code generator
(b) The target machine
(c) Runtime Storage management
(d) Basic Blocks and Flow Graphs
(e) Next-use Information – A simple Code generator – DAG representation of
Basic Blocks – Peephole Optimization.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 2
CODE GENERATION
The final phase in our compiler model is the code generator. It takes as input
an intermediate representation of the source program and produces as output
an equivalent target program.
The requirements traditionally imposed on a code generator are
severe. The output code must be correct and of high quality, meaning that it
should make effective use of the resources of the target machine. Moreover,
the code generator itself should run efficiently
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 3
• Symbol table: A data structure used by a compiler to keep
track of
semantics of variables.
• Data type.
• When is used: scope.
 The effective context where a name is valid.
• Where it is stored: storage address.
• Possible implementations:
• Unordered list: for a very small set of variables.
• Ordered linear list: insertion is expensive, but
implementation is
• relatively easy
ANKUR SRIVASTAVA ASSISTANT PROFESSOR
JIT
4
Data structure for symbol tables
• Possible entries in a symbol table:
• Name: a string.
• Attribute:
Reserved word
Variable name
Type name
Procedure name
Constant name
• Data type.
• Scope information: where it can be used.
• Storage allocation, size
ANKUR SRIVASTAVA ASSISTANT PROFESSOR
JIT
5
DIAGRAM
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 6
THE TARGET MACHINE
The output of the code generator is the target program. The output may take on
a variety of forms: absolute machine language, relocatable machine language,
or assembly language.
Producing an absolute machine language program as output has the advantage
that it can be placed in a location in memory and immediately executed. A
small program can be compiled and executed quickly. A number of “student-
job” compilers, such as WATFIV and PL/C, produce absolute code.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 7
MEMORY MANAGEMENT
Mapping names in the source program to addresses of data objects in run time
memory is done cooperatively by the front end and the code generator. We
assume that a name in a three-address statement refers to a symbol table entry
for the name.
If machine code is being generated, labels in three address
statements have to be converted to addresses of instructions. This process is
analogous to the “back patching”. Suppose that labels refer to quadruple
numbers in a quadruple array. As we scan each quadruple in turn we can
deduce the location of the first machine instruction generated for that
quadruple, simply by maintaining a count of the number of words used for the
instructions generated so far
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 8
INSTRUCTION SELECTION
The nature of the instruction set of the target machine determines the difficulty
of instruction selection. The uniformity and completeness of the instruction set
are important factors. If the target machine does not support each data type in a
uniform manner, then each exception to the general rule requires special
handling.
Instruction speeds and machine idioms are other important factors. If we do
not care about the efficiency of the target program, instruction selection is
straightforward. For each type of three- address statement we can design a
code skeleton that outlines the target code to be generated for that construct.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 9
REGISTER ALLOCATION
Instructions involving register operands are usually shorter and faster than
those involving operands in memory. Therefore, efficient utilization of register
is particularly important in generating good code. The use of registers is often
subdivided into two sub-problems:
1. During register allocation, we select the set of variables that will
reside in registers at a point in the program.
2. During a subsequent register assignment phase, we pick the specific
register that a variable will reside in.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 10
APPROCHES TO CODE GENERATION
The most important criterion for a code generator is that it produce correct
code. Correctness takes on special significance because of the number of
special cases that code generator must face. Given the premium on correctness,
designing a code generator so it can be easily implemented, tested, and
maintained is an important design goal
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 11
BASIC BLOCKS
A basic block is a sequence of consecutive statements in which
flow of control enters at the beginning and leaves at the end without halt or
possibility of branching except at the end. The following sequence of three-
address statements forms a basic block:
t1 := a*a
t2 := a*b
t3 := 2*t2
t4 := t1+t3
t5 := b*b
t6 := t4+t5
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 12
A three-address statement x := y+z is said to define x and to use y or z. A name
in a basic block is said to live at a given point if its value is used after that
point in the program, perhaps in another basic block.
The following algorithm can be used to partition a sequence of three-address
statements into basic blocks.
Algorithm 1: Partition into basic blocks.
Input: A sequence of three-address statements.
Output: A list of basic blocks with each three-address statement in exactly one
block.
For each leader, its basic block consists of the leader and all statements up to
but not including the next leader or the end of the program.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 13
Example 3: Consider the fragment of source code shown it computes the dot
product of two vectors a and b of length 20. A list of three-address statements
performing this computation on our target machine is.
begin
prod := 0;
i := 1;
do begin
prod := prod + a[i] * b[i];
i := i+1;
end
while i<= 20
end
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 14
Let us apply Algorithm 1 to the three-address code in fig 8 to determine its
basic blocks. statement (1) is a leader by rule (I) and statement (3) is a leader
by rule (II), since the last statement can jump to it. By rule (III) the statement
following (12) is a leader. Therefore, statements (1) and (2) form a basic block.
The remainder of the program beginning with statement (3) forms a second
basic block.
(1) prod := 0
(2) i := 1
(3) t1 := 4*i
(4) t2 := a [ t1 ]
(5) t3 := 4*i
(6) t4 :=b [ t3 ]
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 15
(7) t5 := t2*t4
(8) t6 := prod +t5
(9) prod := t6
(10) t7 := i+1
(11) i := t7
(12) if i<=20 goto (3)
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 16
STRUCTURE-PRESERVING TRANSFORMATIONS
The primary structure-preserving transformations on basic blocks are:
1. common sub-expression elimination
2. dead-code elimination
3. renaming of temporary variables
4. interchange of two independent adjacent statements
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 17
1. Common sub-expression elimination
Consider the basic block
a:= b+c
b:= a-d
c:= b+c
d:= a-d
The second and fourth statements compute the same expression,
namely b+c-d, and hence this basic block may be transformed into the
equivalent block
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 18
a:= b+c
b:= a-d
c:= b+c
d:= b
Although the 1st and 3rd statements in both cases appear to have the same
expression on the right, the second statement redefines b. Therefore, the value
of b in the 3rd statement is different from the value of b in the 1st, and the 1st
and 3rd statements do not compute the same expression.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 19
2. Dead-code elimination
Suppose x is dead, that is, never subsequently used, at the point where the
statement x:= y+z appears in a basic block. Then this statement may be safely
removed without changing the value of the basic block.
3. Renaming temporary variables
Suppose we have a statement t:= b+c, where t is a temporary. If we change this
statement to u:= b+c, where u is a new temporary variable, and change all uses
of this instance of t to u, then the value of the basic block is not changed. In
fact, we can always transform a basic block into an equivalent block in which
each statement that defines a temporary defines a new temporary. We call such
a basic block a normal-form block.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 20
Interchange of statements
Suppose we have a block with the two adjacent statements
t1:= b+c
t2:= x+y
Then we can interchange the two statements without affecting the value of the
block if and only if neither x nor y is t1 and neither b nor c is t2. A normal-
form basic block permits all statement interchanges that are possible.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 21
ACTIVATION RECORD?
Information needed by a single execution of procedure is managed using a
contiguous block of storage called an activation record or frame. It is
customary to push the activation record of a procedure on the run time stack
when the procedure is called and to pop the activation record off the stack
when control returns to the caller.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 22
ACTIVATION TREES
A program is a sequence of instructions combined into a number of
procedures. Instructions in a procedure is executed sequentially. A procedure
have a start and an end delimiter and everything inside it is called the body of
the procedure. The procedure identifier and the sequence of finite instructions
inside it make up the body of the procedure.
The execution of a procedure is called its activation. An activation record
contains all the necessary information required to call a procedure. An
activation record may contain the following units (depending upon the source
language used).
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 23
To know this idea, an example:
printf(“Enter Your Name: “);
scanf(“%s”, username);
show_data(username);
printf(“Press any key to continue…”
int show_data(char *user)
{
printf(“Your name is %s”, username);
return 0;
}
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 24
Storage Allocation
Runtime environment manages runtime memory requirements for the following
entities:
Code : It is known as the text part of a program that does not change at runtime. Its
memory requirements are known at the compile time.
Procedures : Their text part is static but they are called in a random manner. That is
why, stack storage is used to manage procedure calls and activations.
Variables : Variables are known at the runtime only, unless they are global or constant.
Heap memory allocation scheme is used for managing allocation and de-allocation of
memory for variables in runtime.
31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 25

More Related Content

What's hot

Error Detection & Recovery
Error Detection & RecoveryError Detection & Recovery
Error Detection & Recovery
Akhil Kaushik
 
Asymptotic notation
Asymptotic notationAsymptotic notation
Asymptotic notation
Dr Shashikant Athawale
 
Intro automata theory
Intro automata theory Intro automata theory
Intro automata theory
Rajendran
 
Compiler design syntax analysis
Compiler design syntax analysisCompiler design syntax analysis
Compiler design syntax analysis
Richa Sharma
 
If statements in c programming
If statements in c programmingIf statements in c programming
If statements in c programming
Archana Gopinath
 
Chapter 3 -Syntax Analyzer.ppt
Chapter 3 -Syntax Analyzer.pptChapter 3 -Syntax Analyzer.ppt
Chapter 3 -Syntax Analyzer.ppt
FamiDan
 
Chomsky Hierarchy.ppt
Chomsky Hierarchy.pptChomsky Hierarchy.ppt
Chomsky Hierarchy.ppt
AayushSingh233965
 
Design and Analysis of Algorithms
Design and Analysis of AlgorithmsDesign and Analysis of Algorithms
Design and Analysis of Algorithms
Arvind Krishnaa
 
LR Parsing
LR ParsingLR Parsing
LR Parsing
Eelco Visser
 
Passes of compilers
Passes of compilersPasses of compilers
Passes of compilers
Vairavel C
 
Parsing
ParsingParsing
Parsing
khush_boo31
 
1.9. minimization of dfa
1.9. minimization of dfa1.9. minimization of dfa
1.9. minimization of dfa
Sampath Kumar S
 
Deterministic Finite Automata (DFA)
Deterministic Finite Automata (DFA)Deterministic Finite Automata (DFA)
Deterministic Finite Automata (DFA)
Animesh Chaturvedi
 
Code generation in Compiler Design
Code generation in Compiler DesignCode generation in Compiler Design
Code generation in Compiler Design
Kuppusamy P
 
Control and conditional statements
Control and conditional statementsControl and conditional statements
Control and conditional statements
rajshreemuthiah
 
Semantic analysis in Compiler Construction
Semantic analysis in Compiler ConstructionSemantic analysis in Compiler Construction
Semantic analysis in Compiler Construction
Muhammad Haroon
 
Type checking in compiler design
Type checking in compiler designType checking in compiler design
Type checking in compiler design
Sudip Singh
 
Dead Code Elimination
Dead Code EliminationDead Code Elimination
Dead Code Elimination
Samiul Ehsan
 
A Role of Lexical Analyzer
A Role of Lexical AnalyzerA Role of Lexical Analyzer
A Role of Lexical Analyzer
Archana Gopinath
 
C program
C programC program
C program
AJAL A J
 

What's hot (20)

Error Detection & Recovery
Error Detection & RecoveryError Detection & Recovery
Error Detection & Recovery
 
Asymptotic notation
Asymptotic notationAsymptotic notation
Asymptotic notation
 
Intro automata theory
Intro automata theory Intro automata theory
Intro automata theory
 
Compiler design syntax analysis
Compiler design syntax analysisCompiler design syntax analysis
Compiler design syntax analysis
 
If statements in c programming
If statements in c programmingIf statements in c programming
If statements in c programming
 
Chapter 3 -Syntax Analyzer.ppt
Chapter 3 -Syntax Analyzer.pptChapter 3 -Syntax Analyzer.ppt
Chapter 3 -Syntax Analyzer.ppt
 
Chomsky Hierarchy.ppt
Chomsky Hierarchy.pptChomsky Hierarchy.ppt
Chomsky Hierarchy.ppt
 
Design and Analysis of Algorithms
Design and Analysis of AlgorithmsDesign and Analysis of Algorithms
Design and Analysis of Algorithms
 
LR Parsing
LR ParsingLR Parsing
LR Parsing
 
Passes of compilers
Passes of compilersPasses of compilers
Passes of compilers
 
Parsing
ParsingParsing
Parsing
 
1.9. minimization of dfa
1.9. minimization of dfa1.9. minimization of dfa
1.9. minimization of dfa
 
Deterministic Finite Automata (DFA)
Deterministic Finite Automata (DFA)Deterministic Finite Automata (DFA)
Deterministic Finite Automata (DFA)
 
Code generation in Compiler Design
Code generation in Compiler DesignCode generation in Compiler Design
Code generation in Compiler Design
 
Control and conditional statements
Control and conditional statementsControl and conditional statements
Control and conditional statements
 
Semantic analysis in Compiler Construction
Semantic analysis in Compiler ConstructionSemantic analysis in Compiler Construction
Semantic analysis in Compiler Construction
 
Type checking in compiler design
Type checking in compiler designType checking in compiler design
Type checking in compiler design
 
Dead Code Elimination
Dead Code EliminationDead Code Elimination
Dead Code Elimination
 
A Role of Lexical Analyzer
A Role of Lexical AnalyzerA Role of Lexical Analyzer
A Role of Lexical Analyzer
 
C program
C programC program
C program
 

Viewers also liked

Peephole optimization techniques in compiler design
Peephole optimization techniques in compiler designPeephole optimization techniques in compiler design
Peephole optimization techniques in compiler design
Anul Chaudhary
 
Code generation
Code generationCode generation
Code generation
Aparna Nayak
 
Compiler unit 5
Compiler  unit 5Compiler  unit 5
Compiler unit 5
BBDITM LUCKNOW
 
Chapter Seven(2)
Chapter Seven(2)Chapter Seven(2)
Chapter Seven(2)bolovv
 
The dag representation of basic blocks
The dag representation of basic blocksThe dag representation of basic blocks
The dag representation of basic blocks
Shabeen Taj
 
Compiler Optimization Presentation
Compiler Optimization PresentationCompiler Optimization Presentation
Compiler Optimization Presentation
19magnet
 
Compiler unit 1
Compiler unit 1Compiler unit 1
Compiler unit 1
BBDITM LUCKNOW
 
Run time administration
Run time administrationRun time administration
Run time administration
Arjun Srivastava
 
Chapter 6 intermediate code generation
Chapter 6   intermediate code generationChapter 6   intermediate code generation
Chapter 6 intermediate code generation
Vipul Naik
 
Query processing-and-optimization
Query processing-and-optimizationQuery processing-and-optimization
Query processing-and-optimization
WBUTTUTORIALS
 
Control Flow Analysis
Control Flow AnalysisControl Flow Analysis
Control Flow Analysis
Edgar Barbosa
 
Basic Blocks and Flow Graphs
Basic Blocks and Flow GraphsBasic Blocks and Flow Graphs
Basic Blocks and Flow Graphs
Jenny Galino
 
Intermediate code- generation
Intermediate code- generationIntermediate code- generation
Intermediate code- generationrawan_z
 
Three address code In Compiler Design
Three address code In Compiler DesignThree address code In Compiler Design
Three address code In Compiler Design
Shine Raj
 
Compiler Chapter 1
Compiler Chapter 1Compiler Chapter 1
Compiler Chapter 1
Huawei Technologies
 
Run time storage
Run time storageRun time storage
Run time storage
Rasineni Madhan Mohan Naidu
 
Assignment statements
Assignment statementsAssignment statements
Assignment statements
Divya Devan
 
Back patching
Back patchingBack patching
Back patching
santhiya thavanthi
 
Lecture 16 17 code-generation
Lecture 16 17 code-generationLecture 16 17 code-generation
Lecture 16 17 code-generation
Iffat Anjum
 

Viewers also liked (20)

Peephole optimization techniques in compiler design
Peephole optimization techniques in compiler designPeephole optimization techniques in compiler design
Peephole optimization techniques in compiler design
 
Code generation
Code generationCode generation
Code generation
 
Compiler unit 5
Compiler  unit 5Compiler  unit 5
Compiler unit 5
 
Chapter Seven(2)
Chapter Seven(2)Chapter Seven(2)
Chapter Seven(2)
 
The dag representation of basic blocks
The dag representation of basic blocksThe dag representation of basic blocks
The dag representation of basic blocks
 
Compiler Optimization Presentation
Compiler Optimization PresentationCompiler Optimization Presentation
Compiler Optimization Presentation
 
Compiler unit 1
Compiler unit 1Compiler unit 1
Compiler unit 1
 
Run time administration
Run time administrationRun time administration
Run time administration
 
Chapter 6 intermediate code generation
Chapter 6   intermediate code generationChapter 6   intermediate code generation
Chapter 6 intermediate code generation
 
Query processing-and-optimization
Query processing-and-optimizationQuery processing-and-optimization
Query processing-and-optimization
 
Control Flow Analysis
Control Flow AnalysisControl Flow Analysis
Control Flow Analysis
 
Unit 1 cd
Unit 1 cdUnit 1 cd
Unit 1 cd
 
Basic Blocks and Flow Graphs
Basic Blocks and Flow GraphsBasic Blocks and Flow Graphs
Basic Blocks and Flow Graphs
 
Intermediate code- generation
Intermediate code- generationIntermediate code- generation
Intermediate code- generation
 
Three address code In Compiler Design
Three address code In Compiler DesignThree address code In Compiler Design
Three address code In Compiler Design
 
Compiler Chapter 1
Compiler Chapter 1Compiler Chapter 1
Compiler Chapter 1
 
Run time storage
Run time storageRun time storage
Run time storage
 
Assignment statements
Assignment statementsAssignment statements
Assignment statements
 
Back patching
Back patchingBack patching
Back patching
 
Lecture 16 17 code-generation
Lecture 16 17 code-generationLecture 16 17 code-generation
Lecture 16 17 code-generation
 

Similar to Compiler unit 4

1588147798Begining_ABUAD1.pdf
1588147798Begining_ABUAD1.pdf1588147798Begining_ABUAD1.pdf
1588147798Begining_ABUAD1.pdf
SemsemSameer1
 
Programming with c language practical manual
Programming with c language practical manualProgramming with c language practical manual
Programming with c language practical manual
Anil Bishnoi
 
cscript_controller.pdf
cscript_controller.pdfcscript_controller.pdf
cscript_controller.pdf
VcTrn1
 
Micro Processor And Micro controller
Micro Processor And Micro controller Micro Processor And Micro controller
Micro Processor And Micro controller
Raja pirian
 
Principal Sources of Optimization in compiler design
Principal Sources of Optimization in compiler design Principal Sources of Optimization in compiler design
Principal Sources of Optimization in compiler design
LogsAk
 
Dsp lab manual 15 11-2016
Dsp lab manual 15 11-2016Dsp lab manual 15 11-2016
Dsp lab manual 15 11-2016
Gopinath.B.L Naidu
 
Computer Science(083) Python Pre Board Exam 1 Sample Paper Class 12
Computer Science(083) Python Pre Board Exam 1 Sample Paper Class 12Computer Science(083) Python Pre Board Exam 1 Sample Paper Class 12
Computer Science(083) Python Pre Board Exam 1 Sample Paper Class 12
chinthala Vijaya Kumar
 
Primilimnary round questions with answers
Primilimnary round questions with answersPrimilimnary round questions with answers
Primilimnary round questions with answersDr. C.V. Suresh Babu
 
Data structure week 1
Data structure week 1Data structure week 1
Data structure week 1
karmuhtam
 
Static Energy Prediction in Software: A Worst-Case Scenario Approach
Static Energy Prediction in Software: A Worst-Case Scenario ApproachStatic Energy Prediction in Software: A Worst-Case Scenario Approach
Static Energy Prediction in Software: A Worst-Case Scenario Approach
GreenLabAtDI
 
Penn  State  University          School  of.docx
Penn  State  University            School  of.docxPenn  State  University            School  of.docx
Penn  State  University          School  of.docx
danhaley45372
 
Short.course.introduction.to.vhdl
Short.course.introduction.to.vhdlShort.course.introduction.to.vhdl
Short.course.introduction.to.vhdl
Ravi Sony
 
Vlsiexpt 11 12
Vlsiexpt 11 12Vlsiexpt 11 12
Vlsiexpt 11 12JINCY Soju
 
CSCI 2121- Computer Organization and Assembly Language Labor.docx
CSCI 2121- Computer Organization and Assembly Language Labor.docxCSCI 2121- Computer Organization and Assembly Language Labor.docx
CSCI 2121- Computer Organization and Assembly Language Labor.docx
annettsparrow
 
Control Flow Graphs
Control Flow GraphsControl Flow Graphs
Control Flow Graphs
daimk2020
 
Control Flow Graphs
Control Flow GraphsControl Flow Graphs
Control Flow Graphs
daimk2020
 
Instruction_Set.pdf
Instruction_Set.pdfInstruction_Set.pdf
Instruction_Set.pdf
boukomra
 
viva q&a for mp lab
viva q&a for mp labviva q&a for mp lab
viva q&a for mp lab
g yugandhar srinivas
 

Similar to Compiler unit 4 (20)

1588147798Begining_ABUAD1.pdf
1588147798Begining_ABUAD1.pdf1588147798Begining_ABUAD1.pdf
1588147798Begining_ABUAD1.pdf
 
Programming with c language practical manual
Programming with c language practical manualProgramming with c language practical manual
Programming with c language practical manual
 
cscript_controller.pdf
cscript_controller.pdfcscript_controller.pdf
cscript_controller.pdf
 
Micro Processor And Micro controller
Micro Processor And Micro controller Micro Processor And Micro controller
Micro Processor And Micro controller
 
Csd01
Csd01Csd01
Csd01
 
Principal Sources of Optimization in compiler design
Principal Sources of Optimization in compiler design Principal Sources of Optimization in compiler design
Principal Sources of Optimization in compiler design
 
Dsp lab manual 15 11-2016
Dsp lab manual 15 11-2016Dsp lab manual 15 11-2016
Dsp lab manual 15 11-2016
 
Computer Science(083) Python Pre Board Exam 1 Sample Paper Class 12
Computer Science(083) Python Pre Board Exam 1 Sample Paper Class 12Computer Science(083) Python Pre Board Exam 1 Sample Paper Class 12
Computer Science(083) Python Pre Board Exam 1 Sample Paper Class 12
 
6th Semester CS / IS (2013-June) Question Papers
6th Semester CS / IS (2013-June) Question Papers6th Semester CS / IS (2013-June) Question Papers
6th Semester CS / IS (2013-June) Question Papers
 
Primilimnary round questions with answers
Primilimnary round questions with answersPrimilimnary round questions with answers
Primilimnary round questions with answers
 
Data structure week 1
Data structure week 1Data structure week 1
Data structure week 1
 
Static Energy Prediction in Software: A Worst-Case Scenario Approach
Static Energy Prediction in Software: A Worst-Case Scenario ApproachStatic Energy Prediction in Software: A Worst-Case Scenario Approach
Static Energy Prediction in Software: A Worst-Case Scenario Approach
 
Penn  State  University          School  of.docx
Penn  State  University            School  of.docxPenn  State  University            School  of.docx
Penn  State  University          School  of.docx
 
Short.course.introduction.to.vhdl
Short.course.introduction.to.vhdlShort.course.introduction.to.vhdl
Short.course.introduction.to.vhdl
 
Vlsiexpt 11 12
Vlsiexpt 11 12Vlsiexpt 11 12
Vlsiexpt 11 12
 
CSCI 2121- Computer Organization and Assembly Language Labor.docx
CSCI 2121- Computer Organization and Assembly Language Labor.docxCSCI 2121- Computer Organization and Assembly Language Labor.docx
CSCI 2121- Computer Organization and Assembly Language Labor.docx
 
Control Flow Graphs
Control Flow GraphsControl Flow Graphs
Control Flow Graphs
 
Control Flow Graphs
Control Flow GraphsControl Flow Graphs
Control Flow Graphs
 
Instruction_Set.pdf
Instruction_Set.pdfInstruction_Set.pdf
Instruction_Set.pdf
 
viva q&a for mp lab
viva q&a for mp labviva q&a for mp lab
viva q&a for mp lab
 

More from BBDITM LUCKNOW

Unit 5 cspc
Unit 5 cspcUnit 5 cspc
Unit 5 cspc
BBDITM LUCKNOW
 
Unit 4 cspc
Unit 4 cspcUnit 4 cspc
Unit 4 cspc
BBDITM LUCKNOW
 
Unit3 cspc
Unit3 cspcUnit3 cspc
Unit3 cspc
BBDITM LUCKNOW
 
Cse ppt 2018
Cse ppt 2018Cse ppt 2018
Cse ppt 2018
BBDITM LUCKNOW
 
Binary system ppt
Binary system pptBinary system ppt
Binary system ppt
BBDITM LUCKNOW
 
Unit 4 ca-input-output
Unit 4 ca-input-outputUnit 4 ca-input-output
Unit 4 ca-input-output
BBDITM LUCKNOW
 
Unit 3 ca-memory
Unit 3 ca-memoryUnit 3 ca-memory
Unit 3 ca-memory
BBDITM LUCKNOW
 
Unit 2 ca- control unit
Unit 2 ca- control unitUnit 2 ca- control unit
Unit 2 ca- control unit
BBDITM LUCKNOW
 
Unit 1 ca-introduction
Unit 1 ca-introductionUnit 1 ca-introduction
Unit 1 ca-introduction
BBDITM LUCKNOW
 
Bnf and ambiquity
Bnf and ambiquityBnf and ambiquity
Bnf and ambiquity
BBDITM LUCKNOW
 
Minimization of dfa
Minimization of dfaMinimization of dfa
Minimization of dfa
BBDITM LUCKNOW
 
Passescd
PassescdPassescd
Passescd
BBDITM LUCKNOW
 
Cspc final
Cspc finalCspc final
Cspc final
BBDITM LUCKNOW
 
Validation based protocol
Validation based protocolValidation based protocol
Validation based protocol
BBDITM LUCKNOW
 

More from BBDITM LUCKNOW (15)

Unit 5 cspc
Unit 5 cspcUnit 5 cspc
Unit 5 cspc
 
Unit 4 cspc
Unit 4 cspcUnit 4 cspc
Unit 4 cspc
 
Unit3 cspc
Unit3 cspcUnit3 cspc
Unit3 cspc
 
Cse ppt 2018
Cse ppt 2018Cse ppt 2018
Cse ppt 2018
 
Binary system ppt
Binary system pptBinary system ppt
Binary system ppt
 
Unit 4 ca-input-output
Unit 4 ca-input-outputUnit 4 ca-input-output
Unit 4 ca-input-output
 
Unit 3 ca-memory
Unit 3 ca-memoryUnit 3 ca-memory
Unit 3 ca-memory
 
Unit 2 ca- control unit
Unit 2 ca- control unitUnit 2 ca- control unit
Unit 2 ca- control unit
 
Unit 1 ca-introduction
Unit 1 ca-introductionUnit 1 ca-introduction
Unit 1 ca-introduction
 
Bnf and ambiquity
Bnf and ambiquityBnf and ambiquity
Bnf and ambiquity
 
Minimization of dfa
Minimization of dfaMinimization of dfa
Minimization of dfa
 
Passescd
PassescdPassescd
Passescd
 
Cspc final
Cspc finalCspc final
Cspc final
 
Cd2 [autosaved]
Cd2 [autosaved]Cd2 [autosaved]
Cd2 [autosaved]
 
Validation based protocol
Validation based protocolValidation based protocol
Validation based protocol
 

Recently uploaded

J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang,  ICLR 2024, MLILAB, KAIST AI.pdfJ.Yang,  ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
MLILAB
 
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
H.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdfH.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdf
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
MLILAB
 
Cosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdfCosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdf
Kamal Acharya
 
Planning Of Procurement o different goods and services
Planning Of Procurement o different goods and servicesPlanning Of Procurement o different goods and services
Planning Of Procurement o different goods and services
JoytuBarua2
 
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...
Dr.Costas Sachpazis
 
road safety engineering r s e unit 3.pdf
road safety engineering  r s e unit 3.pdfroad safety engineering  r s e unit 3.pdf
road safety engineering r s e unit 3.pdf
VENKATESHvenky89705
 
Governing Equations for Fundamental Aerodynamics_Anderson2010.pdf
Governing Equations for Fundamental Aerodynamics_Anderson2010.pdfGoverning Equations for Fundamental Aerodynamics_Anderson2010.pdf
Governing Equations for Fundamental Aerodynamics_Anderson2010.pdf
WENKENLI1
 
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...
Amil Baba Dawood bangali
 
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
bakpo1
 
CME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional ElectiveCME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional Elective
karthi keyan
 
Final project report on grocery store management system..pdf
Final project report on grocery store management system..pdfFinal project report on grocery store management system..pdf
Final project report on grocery store management system..pdf
Kamal Acharya
 
Standard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - NeometrixStandard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - Neometrix
Neometrix_Engineering_Pvt_Ltd
 
power quality voltage fluctuation UNIT - I.pptx
power quality voltage fluctuation UNIT - I.pptxpower quality voltage fluctuation UNIT - I.pptx
power quality voltage fluctuation UNIT - I.pptx
ViniHema
 
space technology lecture notes on satellite
space technology lecture notes on satellitespace technology lecture notes on satellite
space technology lecture notes on satellite
ongomchris
 
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdfTop 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Teleport Manpower Consultant
 
Water Industry Process Automation and Control Monthly - May 2024.pdf
Water Industry Process Automation and Control Monthly - May 2024.pdfWater Industry Process Automation and Control Monthly - May 2024.pdf
Water Industry Process Automation and Control Monthly - May 2024.pdf
Water Industry Process Automation & Control
 
Gen AI Study Jams _ For the GDSC Leads in India.pdf
Gen AI Study Jams _ For the GDSC Leads in India.pdfGen AI Study Jams _ For the GDSC Leads in India.pdf
Gen AI Study Jams _ For the GDSC Leads in India.pdf
gdsczhcet
 
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
obonagu
 
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
thanhdowork
 
Investor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptxInvestor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptx
AmarGB2
 

Recently uploaded (20)

J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang,  ICLR 2024, MLILAB, KAIST AI.pdfJ.Yang,  ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
 
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
H.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdfH.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdf
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
 
Cosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdfCosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdf
 
Planning Of Procurement o different goods and services
Planning Of Procurement o different goods and servicesPlanning Of Procurement o different goods and services
Planning Of Procurement o different goods and services
 
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...
 
road safety engineering r s e unit 3.pdf
road safety engineering  r s e unit 3.pdfroad safety engineering  r s e unit 3.pdf
road safety engineering r s e unit 3.pdf
 
Governing Equations for Fundamental Aerodynamics_Anderson2010.pdf
Governing Equations for Fundamental Aerodynamics_Anderson2010.pdfGoverning Equations for Fundamental Aerodynamics_Anderson2010.pdf
Governing Equations for Fundamental Aerodynamics_Anderson2010.pdf
 
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...
 
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
 
CME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional ElectiveCME397 Surface Engineering- Professional Elective
CME397 Surface Engineering- Professional Elective
 
Final project report on grocery store management system..pdf
Final project report on grocery store management system..pdfFinal project report on grocery store management system..pdf
Final project report on grocery store management system..pdf
 
Standard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - NeometrixStandard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - Neometrix
 
power quality voltage fluctuation UNIT - I.pptx
power quality voltage fluctuation UNIT - I.pptxpower quality voltage fluctuation UNIT - I.pptx
power quality voltage fluctuation UNIT - I.pptx
 
space technology lecture notes on satellite
space technology lecture notes on satellitespace technology lecture notes on satellite
space technology lecture notes on satellite
 
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdfTop 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
 
Water Industry Process Automation and Control Monthly - May 2024.pdf
Water Industry Process Automation and Control Monthly - May 2024.pdfWater Industry Process Automation and Control Monthly - May 2024.pdf
Water Industry Process Automation and Control Monthly - May 2024.pdf
 
Gen AI Study Jams _ For the GDSC Leads in India.pdf
Gen AI Study Jams _ For the GDSC Leads in India.pdfGen AI Study Jams _ For the GDSC Leads in India.pdf
Gen AI Study Jams _ For the GDSC Leads in India.pdf
 
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
 
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
 
Investor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptxInvestor-Presentation-Q1FY2024 investor presentation document.pptx
Investor-Presentation-Q1FY2024 investor presentation document.pptx
 

Compiler unit 4

  • 1. COMPILER DESIGN UNIT-IV SYMBOL TABLE ANKUR SRIVASTAVA ASSISTANT PROF.(CSE) JETGI 31-Dec-16 1ANKUR SRIVASTAVA(CSE) JETGI
  • 2. CONTENTS (a) Issues in the design of code generator (b) The target machine (c) Runtime Storage management (d) Basic Blocks and Flow Graphs (e) Next-use Information – A simple Code generator – DAG representation of Basic Blocks – Peephole Optimization. 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 2
  • 3. CODE GENERATION The final phase in our compiler model is the code generator. It takes as input an intermediate representation of the source program and produces as output an equivalent target program. The requirements traditionally imposed on a code generator are severe. The output code must be correct and of high quality, meaning that it should make effective use of the resources of the target machine. Moreover, the code generator itself should run efficiently 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 3
  • 4. • Symbol table: A data structure used by a compiler to keep track of semantics of variables. • Data type. • When is used: scope.  The effective context where a name is valid. • Where it is stored: storage address. • Possible implementations: • Unordered list: for a very small set of variables. • Ordered linear list: insertion is expensive, but implementation is • relatively easy ANKUR SRIVASTAVA ASSISTANT PROFESSOR JIT 4
  • 5. Data structure for symbol tables • Possible entries in a symbol table: • Name: a string. • Attribute: Reserved word Variable name Type name Procedure name Constant name • Data type. • Scope information: where it can be used. • Storage allocation, size ANKUR SRIVASTAVA ASSISTANT PROFESSOR JIT 5
  • 7. THE TARGET MACHINE The output of the code generator is the target program. The output may take on a variety of forms: absolute machine language, relocatable machine language, or assembly language. Producing an absolute machine language program as output has the advantage that it can be placed in a location in memory and immediately executed. A small program can be compiled and executed quickly. A number of “student- job” compilers, such as WATFIV and PL/C, produce absolute code. 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 7
  • 8. MEMORY MANAGEMENT Mapping names in the source program to addresses of data objects in run time memory is done cooperatively by the front end and the code generator. We assume that a name in a three-address statement refers to a symbol table entry for the name. If machine code is being generated, labels in three address statements have to be converted to addresses of instructions. This process is analogous to the “back patching”. Suppose that labels refer to quadruple numbers in a quadruple array. As we scan each quadruple in turn we can deduce the location of the first machine instruction generated for that quadruple, simply by maintaining a count of the number of words used for the instructions generated so far 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 8
  • 9. INSTRUCTION SELECTION The nature of the instruction set of the target machine determines the difficulty of instruction selection. The uniformity and completeness of the instruction set are important factors. If the target machine does not support each data type in a uniform manner, then each exception to the general rule requires special handling. Instruction speeds and machine idioms are other important factors. If we do not care about the efficiency of the target program, instruction selection is straightforward. For each type of three- address statement we can design a code skeleton that outlines the target code to be generated for that construct. 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 9
  • 10. REGISTER ALLOCATION Instructions involving register operands are usually shorter and faster than those involving operands in memory. Therefore, efficient utilization of register is particularly important in generating good code. The use of registers is often subdivided into two sub-problems: 1. During register allocation, we select the set of variables that will reside in registers at a point in the program. 2. During a subsequent register assignment phase, we pick the specific register that a variable will reside in. 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 10
  • 11. APPROCHES TO CODE GENERATION The most important criterion for a code generator is that it produce correct code. Correctness takes on special significance because of the number of special cases that code generator must face. Given the premium on correctness, designing a code generator so it can be easily implemented, tested, and maintained is an important design goal 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 11
  • 12. BASIC BLOCKS A basic block is a sequence of consecutive statements in which flow of control enters at the beginning and leaves at the end without halt or possibility of branching except at the end. The following sequence of three- address statements forms a basic block: t1 := a*a t2 := a*b t3 := 2*t2 t4 := t1+t3 t5 := b*b t6 := t4+t5 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 12
  • 13. A three-address statement x := y+z is said to define x and to use y or z. A name in a basic block is said to live at a given point if its value is used after that point in the program, perhaps in another basic block. The following algorithm can be used to partition a sequence of three-address statements into basic blocks. Algorithm 1: Partition into basic blocks. Input: A sequence of three-address statements. Output: A list of basic blocks with each three-address statement in exactly one block. For each leader, its basic block consists of the leader and all statements up to but not including the next leader or the end of the program. 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 13
  • 14. Example 3: Consider the fragment of source code shown it computes the dot product of two vectors a and b of length 20. A list of three-address statements performing this computation on our target machine is. begin prod := 0; i := 1; do begin prod := prod + a[i] * b[i]; i := i+1; end while i<= 20 end 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 14
  • 15. Let us apply Algorithm 1 to the three-address code in fig 8 to determine its basic blocks. statement (1) is a leader by rule (I) and statement (3) is a leader by rule (II), since the last statement can jump to it. By rule (III) the statement following (12) is a leader. Therefore, statements (1) and (2) form a basic block. The remainder of the program beginning with statement (3) forms a second basic block. (1) prod := 0 (2) i := 1 (3) t1 := 4*i (4) t2 := a [ t1 ] (5) t3 := 4*i (6) t4 :=b [ t3 ] 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 15
  • 16. (7) t5 := t2*t4 (8) t6 := prod +t5 (9) prod := t6 (10) t7 := i+1 (11) i := t7 (12) if i<=20 goto (3) 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 16
  • 17. STRUCTURE-PRESERVING TRANSFORMATIONS The primary structure-preserving transformations on basic blocks are: 1. common sub-expression elimination 2. dead-code elimination 3. renaming of temporary variables 4. interchange of two independent adjacent statements 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 17
  • 18. 1. Common sub-expression elimination Consider the basic block a:= b+c b:= a-d c:= b+c d:= a-d The second and fourth statements compute the same expression, namely b+c-d, and hence this basic block may be transformed into the equivalent block 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 18
  • 19. a:= b+c b:= a-d c:= b+c d:= b Although the 1st and 3rd statements in both cases appear to have the same expression on the right, the second statement redefines b. Therefore, the value of b in the 3rd statement is different from the value of b in the 1st, and the 1st and 3rd statements do not compute the same expression. 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 19
  • 20. 2. Dead-code elimination Suppose x is dead, that is, never subsequently used, at the point where the statement x:= y+z appears in a basic block. Then this statement may be safely removed without changing the value of the basic block. 3. Renaming temporary variables Suppose we have a statement t:= b+c, where t is a temporary. If we change this statement to u:= b+c, where u is a new temporary variable, and change all uses of this instance of t to u, then the value of the basic block is not changed. In fact, we can always transform a basic block into an equivalent block in which each statement that defines a temporary defines a new temporary. We call such a basic block a normal-form block. 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 20
  • 21. Interchange of statements Suppose we have a block with the two adjacent statements t1:= b+c t2:= x+y Then we can interchange the two statements without affecting the value of the block if and only if neither x nor y is t1 and neither b nor c is t2. A normal- form basic block permits all statement interchanges that are possible. 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 21
  • 22. ACTIVATION RECORD? Information needed by a single execution of procedure is managed using a contiguous block of storage called an activation record or frame. It is customary to push the activation record of a procedure on the run time stack when the procedure is called and to pop the activation record off the stack when control returns to the caller. 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 22
  • 23. ACTIVATION TREES A program is a sequence of instructions combined into a number of procedures. Instructions in a procedure is executed sequentially. A procedure have a start and an end delimiter and everything inside it is called the body of the procedure. The procedure identifier and the sequence of finite instructions inside it make up the body of the procedure. The execution of a procedure is called its activation. An activation record contains all the necessary information required to call a procedure. An activation record may contain the following units (depending upon the source language used). 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 23
  • 24. To know this idea, an example: printf(“Enter Your Name: “); scanf(“%s”, username); show_data(username); printf(“Press any key to continue…” int show_data(char *user) { printf(“Your name is %s”, username); return 0; } 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 24
  • 25. Storage Allocation Runtime environment manages runtime memory requirements for the following entities: Code : It is known as the text part of a program that does not change at runtime. Its memory requirements are known at the compile time. Procedures : Their text part is static but they are called in a random manner. That is why, stack storage is used to manage procedure calls and activations. Variables : Variables are known at the runtime only, unless they are global or constant. Heap memory allocation scheme is used for managing allocation and de-allocation of memory for variables in runtime. 31-Dec-16 ANKUR SRIVASTAVA(CSE) JETGI 25