This document describes a lab assignment for a computer organization and design course. The goal of the lab is for students to gain experience designing and testing the first four stages of a five-stage pipelined CPU using an FPGA design package. Specifically, students will implement circuits for the instruction fetch, instruction decode, execution, and memory stages. The document provides background on pipelining, describes the circuits for each stage, lists the MIPS registers and sample instructions, and provides instructions for students to design the stages in Verilog and write a report on their work.

1. Penn
State
University
School
of
Electrical
Engineering
and
Computer
Science
Page

2. 1
of
4
CMPEN
331
–
Computer
Organization
and
Design,
Lab
6
Due
Wednesday
April
26,
2017
at
7:00
am
(Drop
box
on
Canvas)

3. This lab introduces the idea of the pipelining technique for
building a fast CPU. The students will obtain
experience with the design implementation and testing of the
first four stages (Instruction Fetch, Instruction
Decode, Instruction Execute, Memory) of the five-stage
pipelined CPU using the Xilinx design package for
FPGAs. It is assumed that students are familiar with the
operation of the Xilinx design package for Field
Programmable Gate Arrays (FPGAs) through the Xilinix tutorial
available in the class website.
1. Pipelining
As described in lab 4
2. Circuits of the Instruction Fetch Stage
As described in lab 4
3. Circuits of the Instruction Decode Stage
As described in lab 4
4. Circuits of the Execution Stage
As described in lab 5
5. Circuits of the Memory Access Stage

4. As described in lab 5
6. Circuits of the Write Back Stage
Referring to Figure 1, in the fifth cycle the first instruction
entered the WB stage. The memory data is selected
and will be written into the register file at the end of the cycle.
All the control signal have a prefix “w”. The
second instruction entered the MEM stage; the third instruction
entered the EXE stage; the fourth instruction is
being decoded in the ID stage; and the fifth instruction is being
fetched in the IF stage. All the six pipeline
registers are updated at the end of the cycle (the destination
register is considered as the six pipeline register).
Then the first instruction is committed. In each of the forth
coming clock cycles, an instruction will be commited
and a new instruction will enter the pipeline. We use the
structure shown in Figure 1 as a baseline for the design
of our pipelined CPU.
Penn
State
University
School
of
Electrical

5. Engineering
and
Computer
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Figure 1 Pipeline write back (WB) stage
7. Table 1 lists the names and usages of the 32 registers in the
register file.

6. Table 1 MIPS general purpose register
$zero 0 Constant 0
$at 1 Reserved for assembler
$v0, $v1 2, 3 Function return values
$a0 - $a3 4 – 7 Function argument values
$t0 - $t7 8 – 15 Temporary (caller saved)
$s0 - $s7 16 – 23 Temporary (callee saved)
$t8, $t9 24, 25 Temporary (caller saved)
$k0, $k1 26, 27 Reserved for OS Kernel
$gp 28 Pointer to Global Area
$sp 29 Stack Pointer
$fp 30 Frame Pointer
$ra 31 Return Address
8. Table 2 lists some MIPS instructions that will be
implemented in our CPU
Table 2 MIPS integration instruction
Penn
State
University

7. School
of
Electrical
Engineering
and
Computer
Science
Page
3
of
4
9. Initialize the first 10 words of the Data memory with the

8. following HEX values:
A00000AA
10000011
20000022
30000033
40000044
50000055
60000066
70000077
80000088
90000099
10. Write a Verilog code that implement the following
instructions using the design shown in Figure 2. Write a
Verilog test bench to verify your code: (You have to show all
the signals written into and out from the MEM/WB
register and the inputs to the Regfile block in your simulation
outputs)
instruction comment
add $6, $2, $10
Assume that the register $1 has the value of 0

9. 11. Write a report that contains the following:
a. Your Verilog design code. Use:
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and
Computer
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10. Page
4
of
4
i. Device: XC7Z010- -1CLG400C
b. Your Verilog® Test Bench design code. Add “`timescale
1ns/1ps” as the first line of your test bench file.
c. The waveforms resulting from the verification of your
design with ModelSim showing all the signals
written in and out from the MEM/WB register and the inputs to
the Regfile block.
d. The design schematics from the Xilinx synthesis of your
design. Do not use any area constraints.
e. Snapshot of the I/O Planning and
f. Snapshot of the floor planning
12. REPORT FORMAT: Free form, but it must be:
g. One report per student.
h. Have a cover sheet with identification: Title, Class, Your
Name, etc.
i. Using Microsoft word and it should be uploaded in word
format not PDF. If you know LaTex, you should
upload the Tex file in addition to the PDF file.
j. Double spaced

11. 13. You have to upload the whole project design file zipped
with the word file.
Penn
State
University
School
of
Electrical
Engineering
and
Computer
Science

12. Page
1
of
4
CMPEN
331
–
Computer
Organization
and
Design,
Lab
5
Due
Monday
April
17,
2017
at
7:00
am
(Drop
box

13. on
Canvas)
This lab introduces the idea of the pipelining technique for
building a fast CPU. The students will obtain
experience with the design implementation and testing of the
first four stages (Instruction Fetch, Instruction
Decode, Instruction Execute, Memory) of the five-stage
pipelined CPU using the Xilinx design package for
FPGAs. It is assumed that students are familiar with the
operation of the Xilinx design package for Field
Programmable Gate Arrays (FPGAs) through the Xilinix tutorial
available in the class website.
1. Pipelining
As described in lab 4
2. Circuits of the Instruction Fetch Stage
As described in lab 4
3. Circuits of the Instruction Decode Stage
As described in lab 4
4. Circuits of the Execution Stage
Referring to Figure 1, (8.5) in the third cycle the first

14. instruction entered the EXE stage. The ALU performs
addition, and the multiplexer selects the immediate. A letter “e”
is prefixed to each control signal in order to
distinguish it from that in the ID stage. The second instruction
is being decoded in the ID stage and the third
instruction is being fetched in the IF stage. All the four pipeline
registers are updated at the end of the cycle.
5. Circuits of the Memory Access Stage
Referring to Figure 2, (8.6) in the fourth cycle of the first
instruction entered the MEM stage. The only task in this
stage is to read data memory. All the control signals have a
prefix “m”. The second instruction entered the EXE
stage; the third instruction is being decoded in the ID stage; and
the fourth instruction is being fetched in the IF
stage. All the five pipeline registers are updated at the end of
the cycle.
Penn
State
University
School
of
Electrical
Engineering

15. and
Computer
Science
Page
2
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Figure 1 Pipeline execution (EXE) stage
Figure 2 Pipeline memory access (MEM) stage

16. Penn
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University
School
of
Electrical
Engineering
and
Computer
Science

17. Page
3
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4
6. Table 1 lists the names and usages of the 32 registers in the
register file.
Table 1 MIPS general purpose register
$zero 0 Constant 0
$at 1 Reserved for assembler
$v0, $v1 2, 3 Function return values
$a0 - $a3 4 – 7 Function argument values
$t0 - $t7 8 – 15 Temporary (caller saved)
$s0 - $s7 16 – 23 Temporary (callee saved)
$t8, $t9 24, 25 Temporary (caller saved)
$k0, $k1 26, 27 Reserved for OS Kernel
$gp 28 Pointer to Global Area
$sp 29 Stack Pointer
$fp 30 Frame Pointer
$ra 31 Return Address
7. Table 2 lists some MIPS instructions that will be
implemented in our CPU
Table 2 MIPS integration instruction

18. 8. Initialize the first 10 words of the Data memory with the
following HEX values:
A00000AA
10000011
20000022
30000033
40000044
50000055
Penn
State
University
School
of
Electrical
Engineering
and
Computer
Science

19. Page
4
of
4
60000066
70000077
80000088
90000099
9. Write a Verilog code that implement the following
instructions using the design shown in Figure 2. Write a
Verilog test bench to verify your code: (You have to show all
the signals written into the MEM/WB register and
output from EX/MEM register in your simulation outputs)
instruction comment
oad x[0]

20. Assume that the register $1 has the value of 0
10. Write a report that contains the following:
a. Your Verilog design code. Use:
i. Device: XC7Z010- -1CLG400C
b. Your Verilog® Test Bench design code. Add “`timescale
1ns/1ps” as the first line of your test bench file.
c. The waveforms resulting from the verification of your
design with ModelSim showing all the signals
written into the MEM/WB register and output from EX/MEM
register.
d. The design schematics from the Xilinx synthesis of your
design. Do not use any area constraints.
e. Snapshot of the I/O Planning and
f. Snapshot of the floor planning
11. REPORT FORMAT: Free form, but it must be:
g. One report per student.
h. Have a cover sheet with identification: Title, Class, Your
Name, etc.
i. Using Microsoft word and it should be uploaded in word
format not PDF. If you know LaTex, you should

21. upload the Tex file in addition to the PDF file.
j. Double spaced
12. You have to upload the whole project design file zipped
with the word file.
Penn
State
University
School
of
Electrical
Engineering
and
Computer
Science

22. Page
1
of
5
CMPEN
331
–
Computer
Organization
and
Design,
Lab
4
Due
Wednesday
April
5,
2017
at

23. 7:0
am
(Drop
box
on
Canvas)
This lab introduces the idea of the pipelining technique for
building a fast CPU. The students will obtain
experience with the design implementation and testing of the
first two stages (Instruction Fetch, Instruction
Decode) of the five-stage pipelined CPU using the Xilinx design
package for FPGAs. It is assumed that students
are familiar with the operation of the Xilinx design package for
Field Programmable Gate Arrays (FPGAs)
through the Xilinix tutorial available in the class website.
1. Pipelining
Pipelining is an implementation technique in which multiple
instructions are overlapped in execution. The five-
stage pipelined CPU allows overlapping execution of multiple
instructions. Although an instruction takes five
clock cycle to pass through the pipeline, a new instruction can
enter the pipeline during every clock cycle. Under
ideal circumstances, the pipelined CPU can produce a result in
every clock cycle. Because in a pipelined CPU
there are multiple operations in each clock cycle, we must save
the temporary results in each pipeline stage into
pipeline registers for use in the follow-up stages. We have five
stages: IF, ID, EXE, MEM, and WB. The PC can
be considered as the first pipeline register at the beginning of

24. the first stage. We name the other pipeline registers
as IF/ID, ID/EXE, EXE/MEM, and MEM/WB in sequence. In
order to understand in depth how the pipelined
CPU works, we will show the circuits that are required in each
pipeline stage of a baseline CPU.
2. Circuits of the Instruction Fetch Stage
The circuit in the IF stage are shown in Figure 2. Also, looking
at the first clock cycle in Figure 1(b), the first lw
instruction is being fetched. In the IF stage, there is an
instruction memory module and an adder between two
pipeline registers. The left most pipeline register is the PC; it
holds 100. In the end of the first cycle (at the rising
edge of clk), the instruction fetched from instruction memory is
written into the IF/ID register. Meanwhile, the
output of the adder (PC + 4, the next PC) is written into PC.
3. Circuits of the Instruction Decode Stage
Referring to Figure 3, in the second cycle, the first instruction
entered the ID stage. There are two jobs in the
second cycle: to decode the first instruction in the ID stage, and
to fetch the second instruction in the IF stage. The
two instructions are shown on the top of the figures: the first
instruction is in the ID stage, and the second
instruction is in the IF stage. The first instruction in the ID
stage comes from the IF/ID register. Two operands are
read from the register file (Regfile in the figure) based on rs
and rt, although the lw instruction does not use the
operand in the register rt. The immediate (imm) is sign-
extended into 32 bits. The regrt signal is used in the ID
stage that selects the destination register number; all others
must be written into the ID/EXE register for later use.

25. At the end of the second cycle, all the data and control signals,
except for regrt, in the ID stage are written into the
ID/EXE register. At the same time, the PC and the IF/ID
register are also updated.
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and
Computer
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26. Page
2
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Figure 1 Timing chart comparison between two types of CPUs
Figure 2 Pipeline instruction fetch (IF) stage
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27. School
of
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Engineering
and
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Science
Page
3
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5
Figure 2 Pipeline instruction decode (ID) stage

28. 4. Table 1 lists the names and usages of the 32 registers in the
register file.
Table 1 MIPS general purpose register
$zero 0 Constant 0
$at 1 Reserved for assembler
$v0, $v1 2, 3 Function return values
$a0 - $a3 4 – 7 Function argument values
$t0 - $t7 8 – 15 Temporary (caller saved)
$s0 - $s7 16 – 23 Temporary (callee saved)
$t8, $t9 24, 25 Temporary (caller saved)
$k0, $k1 26, 27 Reserved for OS Kernel
$gp 28 Pointer to Global Area
$sp 29 Stack Pointer
$fp 30 Frame Pointer
$ra 31 Return Address
5. Table 2 lists some MIPS instructions that will be
implemented in our CPU
Table 2 MIPS integration instruction
Penn
State

29. University
School
of
Electrical
Engineering
and
Computer
Science
Page
4
of
5

30. 6. Initialize the first 10 words of the Data memory with the
following HEX values:
A00000AA
10000011
20000022
30000033
40000044
50000055
60000066
70000077
80000088
90000099
7. Write a Verilog code that implement the following
instructions using the design shown in Figure 2 and Figure 3.
Write a Verilog test bench to verify your code: (You have to
show all the signals written into the IF/ID register
and the ID/EXE register in your simulation outputs)
# address instruction comment
load x[0]
Assume that the register $at has the value of 0
8. Write a report that contains the following:
a. Your Verilog design code. Use:

31. i. Device: XC7Z010- -1CLG400C
b. Your Verilog® Test Bench design code. Add “`timescale
1ns/1ps” as the first line of your test bench file.
Penn
State
University
School
of
Electrical
Engineering
and
Computer
Science

32. Page
5
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5
c. The waveforms resulting from the verification of your
design with ModelSim showing all the signals
written into the IF/ID register and the ID/EXE register.
d. The design schematics from the Xilinx synthesis of your
design. Do not use any area constraints.
e. Snapshot of the I/O Planning and
f. Snapshot of the floor planning
9. REPORT FORMAT: Free form, but it must be:
g. One report per student.
h. Have a cover sheet with identification: Title, Class, Your
Name, etc.
i. Using Microsoft word and it should be uploaded in word
format not PDF. If you know LaTex, you should
upload the Tex file in addition to the PDF file.
j. Double spaced
10. You have to upload the whole project design file zipped
with the word file.