Computer arithmetic: Integer addition and subtraction, ripple carry adder, carry look-ahead adder, etc. multiplication – shift-and-add, Booth multiplier, carry save multiplier, etc. Division restoring and non-restoring techniques, floating point arithmetic

1. Mala B M
Assistant Professor
School of Computer Science and Engineering
REVA University

2. UNIT-2
Chapter 2
Arithmetic Unit
Integer addition and subtraction, ripple carry adder, carry look-
ahead adder, etc. multiplication – shift-and-add, Booth
multiplier, carry save multiplier, etc. Division restoring and
non-restoring techniques, floating point arithmetic, IEEE 754
format

3. Addition/Subtraction Logic
Unit
• Logic specification for a
stage of binary addition

5. Logic for addition of binary
numbers

6. Logic for addition of binary numbers

7. Binary addition/subtraction logic circuit
To detect the overflow condition cn ⊕ cn−1.

8. DESIGN OF FAST ADDERS
Carry-Look ahead Addition
The logic expressions for si (sum) and ci+1 (carry-out) of stage i are
The expressions Gi and Pi are called the generate and propagate
functions for stage i

9. Pi = xi ⊕ yi , which differs from Pi = xi + yi only when xi = yi = 1 But,
in this case Gi = 1, so it does not matter whether Pi is 0 or 1.
Using a cascade of two 2-input XOR gates to realize the 3-input XOR
function for si , the basic B cell in Figure can be used in each bit stage.
Expanding ci in terms of i − 1 subscripted variables and substituting
into the ci+1 expression, we obtain

11. A 16-bit adder built from four 4-bit adder blocks. These blocks provide
new output functions defined as GI
k and PI
k, where k = 0 for the first 4-
bit block, k = 1 for the second 4-bit block, In the first block,
The first-level Gi and Pi functions determine whether bit stage i
generates or propagates a carry. The second-level Gi
k and Pi
k
functions determine whether block k generates or propagates a
carry.

12. With these new functions available, it is not necessary to wait for
carries to ripple through the 4-bit blocks. Carry c16 is formed by
one of the carry-look ahead circuits in Figure as

13. Multiplication of Unsigned Numbers
Array Multiplier:

15. Sequential Circuit Binary Multiplier

17. Multiplication of Signed Numbers
Sign extension of negative multiplicand

18. The Booth Algorithm
Normal and Booth multiplication schemes

19. Booth recoding of a multiplier
Booth multiplication with a negative multiplier

20. Booth multiplier recoding table.
The Booth technique for recoding multipliers is summarized in Figure
The transformation 011 . . . 110⇒+1 0 0. . . 0 −1 0 is called
skipping over 1s.

21. A 16-bit worst-case multiplier, an ordinary multiplier, and a good
multiplier are shown in Figure
Booth recoded multipliers

22. Booth Multiplication Algorithm
 A procedure for multiplying binary integers in signed-2's complement
representation.
 Booth algorithm works for positive or negative multipliers in 2's
complement representation
22

23. Hardware for Booth algorithm
 Qn designates the least significant bit of the multiplier in register QR.
 An extra flip-flop Qn+1 is appended to QR to facilitate a double bit
inspection of the multiplier
23

24. Booth algorithm for multiplication of signed-2's
complement numbers
24

25. Booth algorithm for multiplication of signed-2's complement numbers
25

26. Example of Multiplication with Booth Algorithm
26

27. Carry-Save Addition of Summands:
Multiplication requires the addition of several summands.
 A technique called carry-save addition (CSA) can be used to speed
up the process

29. Schematic representation of the carry-save addition operations
Example:

30. The multiplication example performed using carry-save addition.

31. Division Algorithms
Example of binary division

33. Example:
Mantissa(m) = 53725 and Exponent(e) = 3
Floating-Point Arithmetic

34. Floating-Point Arithmetic Operations
Registers for floating-point arithmetic operations

35. Addition and Subtraction
During addition or subtraction, the two floating-point operands
are in AC and BR .
The sum or difference is formed in the AC . The algorithm can be
divided into four consecutive parts:
1. Check for zeros.
2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.

36. Addition and subtraction of floating-point numbers

37. Multiplication
The multiplication algorithm can be subdivided into four parts:
1. Check for zeros.
2. Add the exponents.
3. Multiply the mantissas.
4. Normalize the product

38. Multiplication of
floating-point
numbers

39. Division
The division algorithm can be subdivided into five parts:
1. Check for zeros.
2. Initialize registers and evaluate the sign.
3. Align the dividend.
4. Subtract the exponents.
5. Divide the mantissas

40. Division of
floating-point
numbers