This document appears to be slides from a lecture on pipelining. It discusses various types of pipeline hazards including structural hazards where the same hardware is needed for multiple instructions, data hazards where an instruction depends on the result of a prior instruction, and control hazards caused by delays in determining branch outcomes. It provides examples of each hazard type and describes techniques for resolving the hazards such as stalling the pipeline, forwarding results between stages, and predicting branch outcomes earlier. The document emphasizes that pipelining can improve processor throughput but hazards may reduce its effectiveness if not addressed properly.

1. Dr. Shadrokh Samavi 1
Advanced Computer
Architecture
Pipelining

2. Dr. Shadrokh Samavi 2

3. Dr. Shadrokh Samavi 3
Some slides are from the instructors’ resources which
accompany the 5th and previous editions.
Some slides are from David Patterson, David Culler
and Krste Asanovic of UC Berkeley; Israel Koren
of UM Amherst, and Milos Prvulovic of Georgia
Tech.
Sources of some slides are mentioned at the bottom
of the page.
Please inform me if I am missing a name in the above
list.
3

4. Dr. Shadrokh Samavi 4
C.1. What Is Pipelining?

5. Dr. Shadrokh Samavi 5
• An implementation technique whereby multiple
instructions are overlapped in execution.
• pipe stage
• throughput
• machine cycle

6. Dr. Shadrokh Samavi 6
IF ID EXE MEM WB

7. Dr. Shadrokh Samavi 7
IF

8. Dr. Shadrokh Samavi 8
ID

9. Dr. Shadrokh Samavi 9
EXE

10. Dr. Shadrokh Samavi 10
MEM

11. Dr. Shadrokh Samavi 11
WB

12. Dr. Shadrokh Samavi 12
Pipelined

13. Dr. Shadrokh Samavi 13
Simple RISC Pipeline
Clock number
Instruction number 1 2 3 4 5 6 7 8 9
Instruction i IF ID EX MEM WB
Instruction i + 1 IF ID EX MEM WB
Instruction i + 2 IF ID EX MEM WB
Instruction i + 3 IF ID EX MEM WB
Instruction i + 4 IF ID EX MEM WB

14. Dr. Shadrokh Samavi 14
Review: Visualizing Pipelining
I
n
s
t
r.
O
r
d
e
r
Time (clock cycles)
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 6 Cycle 7
Cycle 5
Adapted from Patterson, Katz and Kubiatowicz © UCB

15. Dr. Shadrokh Samavi 15

16. Dr. Shadrokh Samavi 16
C.2. Pipeline Hazards

17. Dr. Shadrokh Samavi 17
• Hazards: circumstances that would cause incorrect
execution if next instruction were launched
– Structural hazards: Attempting to use the same
hardware to do two different things at the
same time
– Data hazards: Instruction depends on result of
prior instruction still in the pipeline
– Control hazards: Caused by delay between the
fetching of instructions and decisions about
changes in control flow (branches and jumps).

18. Dr. Shadrokh Samavi 18
Speedup from pipelining
Average instruction time unpipelined
Average instruction time pipelined
-----------------------------------------
-
=
CPI unpipelined Clock cycle unpipelined
×
CPI pipelined Clock cycle pipelined
----------------- -
=
CPI unpipelined
CPI pipelined
----------------- Clock cycle unpipelined
Clock cycle pipelined
--------------------------
-
=
CPI pipelined Ideal CPI Pipeline stall clock cycles per instruction
+
=
1 Pipeline stall clock cycles per instruction
+
=
Speedup
CPI unpipelined
1 Pipeline stall cycles per instruction
+
------------------------------------------
-
=
Speedup Pipeline depth
1 Pipeline stall cycles per instruction
+
------------------------------------------
=
Speedup from pipelining
CPI unpipelined
CPI pipelined
-----------------
-
Clock cycle unpipelined
Clock cycle pipelined
-------------------------
-
=
1
1 Pipeline stall cycles per instruction
+
-----------------------------------------
Clock cycle unpipelined
Clock cycle pipelined
------------------------
-
=
--------------------------
Assuming
same Clock
cycle for
pipelined &
unpipelined
×
×
×

19. Dr. Shadrokh Samavi 19
Example: Structural Hazard
I
n
s
t
r.
O
r
d
e
r
Time (clock cycles)
Load
Instr 1
Instr 2
Instr 3
Instr 4
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 6 Cycle 7
Cycle 5
DMem
Structural Hazard

20. Dr. Shadrokh Samavi 20
Resolving structural hazards
• Definition of structural hazard: attempt to
use same hardware for two different things
at the same time
• Solution 1: Wait (stall)
must detect the hazard
must have mechanism to stall
• Solution 2: Use more hardware

21. Dr. Shadrokh Samavi 21
Detecting and Resolving Structural Hazard
I
n
s
t
r.
O
r
d
e
r
Time (clock cycles)
Load
Instr 1
Instr 2
Stall
Instr 3
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 6 Cycle 7
Cycle 5
Reg
ALU
DMem
Ifetch Reg
Bubble Bubble Bubble Bubble
Bubble
Adapted from Patterson, Katz and Kubiatowicz © UCB

22. Dr. Shadrokh Samavi 22
Eliminating Structural Hazards at Design
Time
ALU
Instr
Cache
Reg
File
MUX
MUX
Data
Cache
MUX
Sign
Extend
Zero?
IF/ID
ID/EX
MEM/WB
EX/MEM
4
Adder Next SEQ PC Next SEQ PC
RD RD RD
WB
Data
Next PC
Address
RS1
RS2
Imm
MUX
Datapath
Control Path

23. Dr. Shadrokh Samavi 23
WB
M
EX
WB
M WB
Control
IF/ID ID/EX EX/MEM MEM/WB
Instruction
RegDst
ALUOp
ALUSrc
Branch
MemRead
MemWrite
MemtoReg
RegWrite
strip off signals for
execution phase
strip off signals for
write-back phase
strip off signals for
memory phase
Genera-
tion
CSE 60321 University of Notre Dame

24. Dr. Shadrokh Samavi 24
Role of ISA in Structural Hazard Resolution
• Simple to determine the sequence of
resources used by an instruction
– opcode tells it all
• Uniformity in the resource usage
• Compare MIPS to IA32?
• MIPS approach => all instructions flow
through same 5-stage pipelining

25. Dr. Shadrokh Samavi 25
Data Hazards
I
n
s
t
r.
O
r
d
e
r
add r1,r2,r3
sub r4,r1,r3
and r6,r1,r7
or r8,r1,r9
xor r10,r1,r11
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Time (clock cycles)
IF ID/RF EX MEM WB
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Adapted from Patterson, Katz and Kubiatowicz © UCB

26. Dr. Shadrokh Samavi 26
Program
execution
order
(in
instructions)
Time (in clock cycles)
CC1 CC2 CC3 CC4 CC5 CC6
ADD R1, R2, R3 DM
DM
DM
Reg
Reg
Reg
IM
IM
IM
Reg
Reg
ALU
ALU
ALU
LW R4, 0(R1)
SW 12(R1), R4
Stores require an operand during MEM, and forwarding of
that operand is shown here

27. Dr. Shadrokh Samavi 27
Data Hazards Classification
Resource Objects (R.O.): all addressable locations
Data Objects (D.O.): content of resource objects
D(I): Domain of instruction I = all R.O. that their
D.O. effect the operation of I.
R(I): Range of instruction I = all R.O. that their
D.O. are effected by the execution of I.

28. Dr. Shadrokh Samavi 28
A RAW hazard exists on register 
if   R ( i )  D( j )  
A WAW hazard exists on register 
if   R( i )  R(j )  
A WAR hazard exists on register 
if   D( i )  R (j )  

29. Dr. Shadrokh Samavi 29
D(I) R(I)
D(J) D(J)
I
write
Read
J
D(J) R(J)
D(I) D(I)
J
write
Read
I
D(I)
R(I)
D(J) R(J)
I
write
write
J
RAW
WAW
WAR

30. Dr. Shadrokh Samavi 30
• Read After Write (RAW)
InstrJ tries to read operand before InstrI writes it
• Caused by a “Data Dependence” (in compiler
nomenclature). This hazard results from an actual
need for communication.
Three Generic Data Hazards
I: add r1,r2,r3
J: sub r4,r1,r3

31. Dr. Shadrokh Samavi 31
• Write After Read (WAR)
InstrJ writes operand before InstrI reads it
• Called an “anti-dependence” by compiler writers.
This results from reuse of the name “r1”.
• Can’t happen in MIPS 5 stage pipeline because:
– All instructions take 5 stages, and
– Reads are always in stage 2, and
– Writes are always in stage 5
I: sub r4,r1,r3
J: add r1,r2,r3
K: mul r6,r1,r7
Three Generic Data Hazards

32. Dr. Shadrokh Samavi 32
• Write After Write (WAW)
InstrJ writes operand before InstrI writes it.
• Called an “output dependence” by compiler writers
This also results from the reuse of name “r1”.
• Can’t happen in MIPS 5 stage pipeline because:
– All instructions take 5 stages, and
– Writes are always in stage 5
• Will see WAR and WAW in later more complicated
pipes
I: sub r1,r4,r3
J: add r1,r2,r3
K: mul r6,r1,r7
Three Generic Data Hazards

33. Dr. Shadrokh Samavi 33
Time (clock cycles)
Forwarding to Avoid Data Hazard
I
n
s
t
r.
O
r
d
e
r
add r1,r2,r3
sub r4,r1,r3
and r6,r1,r7
or r8,r1,r9
xor r10,r1,r11
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg

34. Dr. Shadrokh Samavi 34
Time (clock cycles)
I
n
s
t
r.
O
r
d
e
r
lw r1, 0(r2)
sub r4,r1,r6
and r6,r1,r7
or r8,r1,r9
Data Hazard Even with Forwarding
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Adapted from Patterson, Katz and Kubiatowicz © UCB

35. Dr. Shadrokh Samavi 35
Resolving this load hazard
• Adding hardware? ... not
• Detection?
• Compilation techniques?
• What is the cost of load delays?

36. Dr. Shadrokh Samavi 36
Resolving the Load Data Hazard
Time (clock cycles)
or r8,r1,r9
I
n
s
t
r.
O
r
d
e
r
lw r1, 0(r2)
sub r4,r1,r6
and r6,r1,r7
Reg
ALU
DMem
Ifetch Reg
Reg
Ifetch
ALU
DMem Reg
Bubble
Ifetch
ALU
DMem Reg
Bubble Reg
Ifetch
ALU
DMem
Bubble Reg
How is this different from the instruction issue stall?

37. Dr. Shadrokh Samavi 37
Try producing fast code for
a = b + c;
d = e – f;
assuming a, b, c, d ,e, and f in memory.
Slow code:
LW Rb,b
LW Rc,c
ADD Ra,Rb,Rc
SW a,Ra
LW Re,e
LW Rf,f
SUB Rd,Re,Rf
SW d,Rd
Software Scheduling to Avoid Load Hazards
Fast code:
LW Rb, b
LW Rc, c
LW Re,e
ADD Ra, Rb, Rc
LW Rf, f
SW a,Ra
SUB Rd, Re, Rf
SW d,Rd

38. Dr. Shadrokh Samavi 38
Instruction Set Connection
• What is exposed about this organizational
hazard in the instruction set?
• k cycle delay?
– bad, CPI is not part of ISA
• k instruction slot delay
– load should not be followed by use of the value in the
next k instructions
• Nothing, but code can reduce run-time
delays
• MIPS did the transformation in the
assembler

39. Dr. Shadrokh Samavi 39
Fraction of loads that cause a stall
Benchmark
compress
eqntott
espresso
gcc
li
doduc
ear
hydro2d
mdljdp
su2cor
24%
41%
12%
23%
24%
20% 20%
10% 10%
4%
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%

40. Dr. Shadrokh Samavi 40
Control Hazard on Branches
=> Three Stage Stall
10: beq r1,r3,36
14: and r2,r3,r5
18: or r6,r1,r7
22: add r8,r1,r9
36: xor r10,r1,r11
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg
Reg
ALU
DMem
Ifetch Reg

41. Dr. Shadrokh Samavi 41
Example: Branch Stall Impact
• If 30% branch, Stall 3 cycles significant
• Two part solution:
– Determine branch taken or not sooner, AND
– Compute taken branch address earlier
• MIPS branch tests if register = 0 or  0
• MIPS Solution:
– Move Zero test to ID/RF stage
– Adder to calculate new PC in ID/RF stage
– 1 clock cycle penalty for branch versus 3

42. Dr. Shadrokh Samavi 42
The frequency of
instructions
that may change
the PC
Percentage of instructions executed
0% 25%
5% 10% 15% 20%
10%
0%
0%
2%
1%
2%
6%
4%
4%
6%
2%
2%
11%
8%
4%
12%
4%
3%
11%
1%
4%
22%
2%
2%
11%
3%
3%
9%
0%
1%
Forward conditional
branches
Unconditional branches
Backward conditional
branches
Benchmark
compress
eqntott
espresso
gcc
li
doduc
ear
hydro2d
mdljdp
su2cor

43. Dr. Shadrokh Samavi 43
Four Branch Hazard Alternatives
#1: Stall until branch direction is clear
#2: Predict Branch Not Taken
– Execute successor instructions in sequence
– “Squash” instructions in pipeline if branch actually taken
– Advantage of late pipeline state update
– 47% MIPS branches not taken on average
– PC+4 already calculated, so use it to get next instruction
#3: Predict Branch Taken
– 53% MIPS branches taken on average
– But haven’t calculated branch target address in MIPS
» MIPS still incurs 1 cycle branch penalty
» Other machines: branch target known before outcome

44. Dr. Shadrokh Samavi 44
#4: Delayed Branch
– Define branch to take place AFTER a following instruction
branch instruction
sequential successor1
sequential successor2
........
sequential successorn
........
branch target if taken
– 1 slot delay allows proper decision and branch target
address in 5 stage pipeline
– MIPS uses this
Branch delay of length n
Four Branch Hazard Alternatives

45. Dr. Shadrokh Samavi 45
• Where to get instructions to fill branch delay slot?
– Before branch instruction
– From the target address: only valuable when branch taken
– From fall through: only valuable when branch not taken
– Canceling branches allow more slots to be filled
• Compiler effectiveness for single branch delay slot:
– Fills about 60% of branch delay slots
– About 80% of instructions executed in branch delay slots useful in
computation
– About 50% (60% x 80%) of slots usefully filled
• Delayed Branch downside: 7-8 stage pipelines,
multiple instructions issued per clock (superscalar)
Delayed Branch

46. Dr. Shadrokh Samavi 46
(a) From before (b) From target (c) From fall through
SUB R4, R5, R6
ADD R1, R2, R3
if R1 = 0 then
ADD R1, R2, R3
if R1 = 0 then
SUB R4, R5, R6
SUB R4, R5, R6
ADD R1, R2, R3
if R1 = 0 then
OR R7, R8, R9
ADD R1, R2, R3
if R1 = 0 then
SUB R4, R5, R6
ADD R1, R2, R3
if R2 = 0 then
if R2 = 0 then
ADD R1, R2, R3
Becomes
Becomes
Becomes
Delay slot
Delay slot
Delay slot
OR R7, R8, R9
SUB R4, R5, R6

47. Dr. Shadrokh Samavi 47
Canceling or Nullifying Branch.
In a canceling branch, the instruction includes the
direction that the branch was predicted. When the
branch behaves as predicted, the instruction in the
branch-delay slot is simply executed as it would
normally be with a delayed branch. When the branch
is incorrectly predicted, the instruction in the
branch-delay slot is simply turned into a no-op.

48. Dr. Shadrokh Samavi 48
Delayed-branch scheduling schemes
Scheduling strategy
(a) From before.
(b) From target
(c) From fall
through
Improves performance when?
Always.
When branch is taken. May
enlarge program if
instructions are duplicated.
When branch is not taken.
Requirements
•Branch must not depend
on the rescheduled
instructions
•Must be OK to execute
rescheduled instructions
if branch is not taken.
May need to duplicate
instructions.
•Must be OK to execute
instructions if branch is
taken.

49. Dr. Shadrokh Samavi 49
The behavior of a predicted-taken canceling branch
depends on whether the branch is taken or not.
Branch is NOT TAKEN (wrong prediction)
Branch is TAKEN ( predicted correctly)

50. Dr. Shadrokh Samavi 50
Delayed and Canceling Delay Branches

51. Dr. Shadrokh Samavi 51
Overall costs of a variety of branch schemes

52. Dr. Shadrokh Samavi 52
For an R4000-style pipeline, it takes 3 pipeline stages before the
branch target address is known & 1 more cycle to evaluate branch
condition. This leads to the following branch penalties:
Find the effective addition to the CPI arising from branches given
that the relative frequency of unconditional, conditional untaken, and
conditional taken branches are 4%, 6%, and 10%, respectively.

53. Dr. Shadrokh Samavi 53
Control Hazards
1. Find out whether the branch is taken or not taken
earlier in the pipeline.
2. Compute the taken PC (i.e., the address of the branch
target) earlier.
Branch instruction IF ID EX MEM WB
Branch successor IF stall stall IF ID EX MEM WB
Branch successor + 1 IF ID EX MEM WB
Branch successor + 2 IF ID EX MEM
Branch successor + 3 IF ID EX
Branch successor + 4 IF ID
Branch successor + 5 IF

54. Dr. Shadrokh Samavi 54
C.3.Implementation of
Pipelining

55. Dr. Shadrokh Samavi 55
Instruction fetch
Instruction decode/
register fetch
Execute/
Address
calculation
Memory
access
Write
back

56. Dr. Shadrokh Samavi 56
IF/ID
ID/EX
MEM/WB
EX/MEM
IF
IF ID EX M
E
M
WB
INST
1
INST
2

57. Dr. Shadrokh Samavi 57
Events on every pipe stage of the MIPS pipeline.

58. Dr. Shadrokh Samavi 58
5 Steps of MIPS Datapath
Memory
Access
Write
Back
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
ALU
Memory
Reg
File
MUX
MUX
Memory
MUX
Sign
Extend
Zero?
IF/ID
ID/EX
MEM/WB
EX/MEM
4
Adder Next SEQ PC Next SEQ PC
RD RD RD
WB
Data
Next PC
Address
RS1
RS2
Imm
MUX
Datapath
Control Path
Inst
1

59. Dr. Shadrokh Samavi 59
5 Steps of MIPS Datapath
Memory
Access
Write
Back
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
ALU
Memory
Reg
File
MUX
MUX
Memory
MUX
Sign
Extend
Zero?
IF/ID
ID/EX
MEM/WB
EX/MEM
4
Adder Next SEQ PC Next SEQ PC
RD RD RD
WB
Data
Next PC
Address
RS1
RS2
Imm
MUX
Datapath
Control Path
Inst
1
Inst
2

60. Dr. Shadrokh Samavi 60
5 Steps of MIPS Datapath
Memory
Access
Write
Back
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
ALU
Memory
Reg
File
MUX
MUX
Memory
MUX
Sign
Extend
Zero?
IF/ID
ID/EX
MEM/WB
EX/MEM
4
Adder Next SEQ PC Next SEQ PC
RD RD RD
WB
Data
Next PC
Address
RS1
RS2
Imm
MUX
Datapath
Control Path
Inst
1
Inst
2
Inst
3

61. Dr. Shadrokh Samavi 61

62. Dr. Shadrokh Samavi 62
Situation
Example code
sequence Action
No dependence LWR1,45(R2)
ADD R5,R6,R7
SUB R8,R6,R7
OR R9,R6,R7
No hazard possible because no dependence
exists on R1 in the immediately following
three instructions
.
Dependence
requiring stall
LWR1,45(R2)
ADD R5,
R1,R7
SUB R8,R6,R7
OR R9,R6,R7
Comparators detect the use of R1 in the
ADD and stall the ADD (and SUB and OR)
before the ADD begins EX.
Dependence
overcome by
forwarding
LWR1,45(R2)
ADD R5,R6,R7
SUB R8,R1,R7
OR R9,R6,R7
Comparators detect use of R1 in SUB
and forward result of load to ALU in
time for SUB to begin EX.
Dependence
with accesses
in order
LWR1,45(R2)
ADD R5,R6,R7
SUB R8,R6,R7
OR R9,R1,R7
No action required because the read of R1
by OR occurs in the second half of the ID
phase, while the write of the loaded data
occurred in the first half.
No action required because the read of R1
by OR occurs in the second half of the ID
phase, while the write of the loaded data
occurred in the first half.
Situations that the pipeline hazard detection hardware can see by
comparing the destination and sources of adjacent instructions.

63. Dr. Shadrokh Samavi 63
Forwarding of data
Pipeline
register
containing
source
instruction
Opcode
of source
instruction
Pipeline
register
containing
destination
instruction
Opcode of
destination
instruction
Destination
of the
forwarded
result
Comparison
(if equal then
forward)
EX/MEM ID/EX
ALU immediate, load,
store, branch
Top ALU
input
EX/MEM.IR 16..20 ==
ID/EX.IR 6..10
EX/MEM ID/EX Bottom ALU
input
EX/MEM.IR 16..20 ==
ID/EX.IR 11..15
MEM/WB ID/EX Register-register ALU,
ALU immediate, load,
store, branch
MEM/WB.IR 16..20 ==
ID/EX.IR 6..10
MEM/WB ID/EX Register-register ALU MEM/WB.IR 16..20 ==
ID/EX.IR 11..15
EX/MEM ALU
immediate
ID/EX
ALU immediate, load,
store, branch
EX/MEM.IR 11..15 ==
ID/EX.IR 6..10
EX/MEM ALU
immediate
ID/EX EX/MEM.IR 11..15 ==
ID/EX.IR 11..15
MEM/WB ALU
immediate
ID/EX
ALU immediate, load,
store, branch
MEM/WB.IR 11..15 ==
ID/EX.IR 6..10
MEM/WB ALU
immediate
ID/EX MEM/WB.IR 11..15 ==
ID/EX.IR 11..15
MEM/WB Load ID/EX
ALU immediate, load,
store, branch
MEM/WB.IR 11..15 ==
ID/EX.IR 6..10
MEM/WB Load ID/EX MEM/WB.IR 11..15 ==
ID/EX.IR 11..15
Register-register ALU
Register-register ALU
Register-register ALU
Register-register ALU
Register-register ALU
Register-register ALU
Register-register ALU,
Register-register ALU,
Register-
register ALU,
Register-
register ALU,
Register-
register ALU,
Register-
register ALU,
Top ALU
input
Bottom ALU
input
Top ALU
input
Bottom ALU
input
Top ALU
input
Bottom ALU
input
Top ALU
input
Bottom ALU
input

64. Dr. Shadrokh Samavi 64
HW Change for Forwarding
MEM/WR
ID/EX
EX/MEM
Data
Memory
ALU
mux
mux
Registers
NextPC
Immediate
mux

65. Dr. Shadrokh Samavi 65
Memory
Access
Write
Back
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
ALU
Memory
Reg
File
MUX
MUX
Memory
MUX
Sign
Extend
Zero?
IF/ID
ID/EX
MEM/WB
EX/MEM
4
Adder
Next SEQ PC Next SEQ PC
RD RD RD
WB
Data
Next PC
Address
RS1
RS2
Imm
MUX
Datapath

66. Dr. Shadrokh Samavi 66
Adder
IF/ID
Pipelined MIPS Datapath
Memory
Access
Write
Back
Instruction
Fetch
Instr. Decode
Reg. Fetch
Execute
Addr. Calc
ALU
Memory
Reg
File
MUX
Data
Memory
MUX
Sign
Extend
Zero?
MEM/WB
EX/MEM
4
Adder
Next
SEQ PC
RD RD RD
WB
Data
• Data stationary control
– local decode for each instruction phase / pipeline stage
Next PC
Address
RS1
RS2
Imm
MUX
ID/EX

67. Dr. Shadrokh Samavi 67
C.5. Multicycle Operations

68. Dr. Shadrokh Samavi 68
The MIPS pipeline with three
additional unpipelined, floating-point,
functional units.

69. Dr. Shadrokh Samavi 69
Latency : the number of intervening cycles between an
instruction that produces a result and an instruction
that uses the result.
The initiation or repeat interval: the number of cycles
that must elapse between issuing two operations of a
given type.

70. Dr. Shadrokh Samavi 70

71. Dr. Shadrokh Samavi 71
The pipeline timing of a set of independent FP operations.
A typical FP code sequence showing the stalls arising from RAW hazards.

72. Dr. Shadrokh Samavi 72
Three instructions want to perform a write back to the
FP register file simultaneously, as shown in clock cycle
11.

73. Dr. Shadrokh Samavi 73

74. Dr. Shadrokh Samavi 74
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