Abstract: In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 3-input LUT-based structure of FPGAs. The implementation of FIR filters on FPGA based on traditional arithmetic method costs considerable hardware resources, which goes against the decrease of circuit scale and the increase of system speed. This paper presents the realization of area efficient architectures using Distributed Arithmetic (DA) for implementation of Finite Impulse Response (FIR) filter. The performance of the bit-serial and bit parallel DA along with pipelining architecture with different quantized versions are analyzed for FIR filter Design. Distributed Arithmetic structure is used to increase the resource usage while pipeline structure is also used to increase the system speed. In addition, the divided LUT method is also used to decrease the required memory units. However, according to Distributed Arithmetic, we can make a Look-Up-Table (LUT) to conserve the MAC values and callout the values according to the input data if necessary. Therefore, LUT can be created to take the place of MAC units so as to save the hardware resources. The simulation results indicate that FIR filters using Distributed Arithmetic can work stable with high speed and can save almost 50 percent hardware resources to decrease the circuit scale, and can be applied to a variety of areas for its great flexibility and high reliability. This method not only reduces the LUT size, but also modifies the structure of the filter to achieve high speed performance. Keywords: DSP, Digital Filters, FIR , FPGA, MAC, Distributed Arithmetic(DA),Divided LUT, pipeline
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Interpolators and decimators are utilized to increase or decrease the sampling rate. In this paper an efficient method has been presented to implement high speed and area efficient interpolator for wireless communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate operations with look up table (LUT) accesses. Interpolator has been implemented using Partitioned distributed arithmetic look up table (DALUT) technique. This technique has been used to take an optimal advantage of embedded LUTs of the target FPGA. This method is useful to enhance the system performance in terms of speed and area. The proposed interpolator has been designed using half band poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The proposed LUT based multiplier less approach has shown a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by consuming considerably less resources to provide cost effective solution for wireless communication systems.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
AN EFFICIENT DSP ARCHITECTURE DESIGN IN FPGA USING LOOP BACK ALGORITHMIJARIDEA Journal
Abstract— Advanced flag processors assume a noteworthy part in electronic gadgets, bio restorative applications, correspondence conventions. Effective IC configuration is a key variable to accomplish low power and high throughput IP center improvement for convenient gadgets. Computerized flag processors assume a huge parts progressively figuring and preparing yet region overhead and power utilization are real disadvantages to accomplish productive outline requirements. Adaptable DSP engineering utilizing circle back calculation is a proposed way to deal with beat existing outline limitations. For instance, plan of 8 point FFT engineering requires 3 phases for butterfly calculation unit that 48 adders and 12 multipliers prompts high power and territory utilization. To lessen range and power, Loop back calculation is proposed and it requires 16 adders and 4 multipliers for general outline. Likewise outline of various DSP layouts like FFT, First request FIR channel and Second request FIR channel is acquainted and mapping in with the design as preparing component and applying the circle back calculation. In the outline of FFT,FIR formats adders, for example, parallel prefix viper, move and include multiplier, baugh-wooley multiplier are utilized to break down effective plan of DSP engineering. Recreation and examination of inactivity, territory, control productivity with the current structures are happens utilizing model sim 6.4a and combine utilizing Xilinx 14.3 ISE.
Keywords— Baugh-UWooley Multiplier, Loop Back Algorithm, Parallel Prefix Adders.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
“FIELD PROGRAMMABLE DSP ARRAYS” - A NOVEL RECONFIGURABLE ARCHITECTURE FOR EFF...sipij
Digital Signal Processing functions are widely used in real time high speed applications. Those functions
are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively
smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is
redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtractors, multipliers,
scaling units, shifters) instead of CLBs. This paper introduces the development of a reconfigurable DSP
processor that integrates different filter and transform functions. The switching between DSP functions is
occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable
architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility,
parallelism and scalability.
Optimized implementation of an innovative digital audio equalizera3labdsp
Digital audio equalization is one of the most common operations in the acoustic field, but its performance
depends on computational complexity and filter design techniques. Starting from a previous FIR
implementation based on multirate systems and filterbanks theory, an optimized digital audio equalizer
is derived. The proposed approach employs IIR filters to improve the filterbanks structure developed to
avoid ripple between adjacent bands. The effectiveness of the optimized implementation is shown comparing
it with the previous approach. The solution presented here has several advantages increasing
the equalization performance in terms of low computational complexity, low delay, and uniform frequency
response.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Interpolators and decimators are utilized to increase or decrease the sampling rate. In this paper an efficient method has been presented to implement high speed and area efficient interpolator for wireless communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate operations with look up table (LUT) accesses. Interpolator has been implemented using Partitioned distributed arithmetic look up table (DALUT) technique. This technique has been used to take an optimal advantage of embedded LUTs of the target FPGA. This method is useful to enhance the system performance in terms of speed and area. The proposed interpolator has been designed using half band poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The proposed LUT based multiplier less approach has shown a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by consuming considerably less resources to provide cost effective solution for wireless communication systems.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
AN EFFICIENT DSP ARCHITECTURE DESIGN IN FPGA USING LOOP BACK ALGORITHMIJARIDEA Journal
Abstract— Advanced flag processors assume a noteworthy part in electronic gadgets, bio restorative applications, correspondence conventions. Effective IC configuration is a key variable to accomplish low power and high throughput IP center improvement for convenient gadgets. Computerized flag processors assume a huge parts progressively figuring and preparing yet region overhead and power utilization are real disadvantages to accomplish productive outline requirements. Adaptable DSP engineering utilizing circle back calculation is a proposed way to deal with beat existing outline limitations. For instance, plan of 8 point FFT engineering requires 3 phases for butterfly calculation unit that 48 adders and 12 multipliers prompts high power and territory utilization. To lessen range and power, Loop back calculation is proposed and it requires 16 adders and 4 multipliers for general outline. Likewise outline of various DSP layouts like FFT, First request FIR channel and Second request FIR channel is acquainted and mapping in with the design as preparing component and applying the circle back calculation. In the outline of FFT,FIR formats adders, for example, parallel prefix viper, move and include multiplier, baugh-wooley multiplier are utilized to break down effective plan of DSP engineering. Recreation and examination of inactivity, territory, control productivity with the current structures are happens utilizing model sim 6.4a and combine utilizing Xilinx 14.3 ISE.
Keywords— Baugh-UWooley Multiplier, Loop Back Algorithm, Parallel Prefix Adders.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
“FIELD PROGRAMMABLE DSP ARRAYS” - A NOVEL RECONFIGURABLE ARCHITECTURE FOR EFF...sipij
Digital Signal Processing functions are widely used in real time high speed applications. Those functions
are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively
smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is
redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtractors, multipliers,
scaling units, shifters) instead of CLBs. This paper introduces the development of a reconfigurable DSP
processor that integrates different filter and transform functions. The switching between DSP functions is
occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable
architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility,
parallelism and scalability.
Optimized implementation of an innovative digital audio equalizera3labdsp
Digital audio equalization is one of the most common operations in the acoustic field, but its performance
depends on computational complexity and filter design techniques. Starting from a previous FIR
implementation based on multirate systems and filterbanks theory, an optimized digital audio equalizer
is derived. The proposed approach employs IIR filters to improve the filterbanks structure developed to
avoid ripple between adjacent bands. The effectiveness of the optimized implementation is shown comparing
it with the previous approach. The solution presented here has several advantages increasing
the equalization performance in terms of low computational complexity, low delay, and uniform frequency
response.
FOLDED ARCHITECTURE FOR NON CANONICAL LEAST MEAN SQUARE ADAPTIVE DIGITAL FILT...VLSICS Design
Power consumption reduction is transpiring drift in area of VLSI digital signal processing. This gives rise
to need of minimization of silicon area which is done by folding algorithm. As silicon area decreases power
consumption of a circuit decreases. Folding is an algorithm which reduces silicon chip area by combining
various arithmetic operations into one operation by time scheduling technique. It is applied on iterative
data flow graph with appropriate folding set. Least mean square algorithm alters coefficients of Adaptive
filter in order to achieve desired output. Proposed work is focused on design of efficient VLSI architecture
for LMS adaptive filter aims at reducing mainly area which results in power consumption reduction and
hardware complexity. LMS filter structure used here is called non-canonical as transpose FIR structure is
used. Results show that numbers of adders are reduced by 37.5 % and multipliers by 33.33% without
changing characteristics of filter.
A Review of Different Methods for Booth MultiplierIJERA Editor
In this review paper, different type of implementation of Booth multiplier has been studied. Multipliers has great importance in digital signal processor, so designing a high-speed multiplier is the need of the hour. Advantages of using modified booth multiplier algorithm is that the number of partial product is reduced. Different types of addition algorithms are also discussed which are used for addition operation of multiplier.
Design of Optimized FIR Filter Using FCSD Representation IJEEE
This paper presents the design and implementation of an eight order efficient FIR filter for wireless communication system. In this work, factored canonical signed digit representation (FCSD) is used for representing the filter coefficients in order to reduce the design complexity, area and delay of the FIR filter. Complexity of the system has been reduced by replacing binary coefficients with FCSD representation. Further area and delay has been improved by replacing multiplication operation with add and shift method where carry save adder (CSA) is used for addition of two numbers and barrel shifter is used for shifting the data words. Representation of coefficient in the FCSD format along with fastest adder and shifter improves the performance of the system. FIR filter has been designed using an equiripple method in MATLAB and further synthesized on Spartan 3E XC3S500E target FPGA device. Simulation results show that optimized FCSD based FIR filter offers a less number of slices, look up tables (LUTs) and flip-flops as compared to CSD and conventional FCSD based FIR filter, in addition to enhanced performance.
37 9144 new technique based peasant multiplication (edit lafi)IAESIJEECS
The Direct Form FIR channel is utilized for DSP application where the channel request is settled. For the most part this channel devours more range and power. To defeat this issue Multiplier Control Signal Decision window (MCSD) plans is joined into Direct Form FIR channel to powerfully change the channel arrange. MCSD structures comprise of Control flag Generator (CG) and Amplitude Detection (AD) rationale circuits. Advertisement rationale is utilized to disavow the correct duplication process and screen the amplitudes of information tests. CG is utilized to control the channel operation through inside counter. Traditional reconfigurable FIR channel is planned utilizing Vedic Multiplier that devours more territory and deferral. In this paper, changed reconfigurable FIR filer is intended to additionally decrease the APT (Area, Power and Timing) item. The proposed Reconfigurable FIR filer, Vedic Multiplier is supplanted by Russian Peasant Multiplication procedure. Subsequently adjusted Reconfigurable FIR channel with Russian Peasant Multiplier expends less region, postponement and power than all analyzed techniques.
Low Memory Low Complexity Image Compression Using HSSPIHT EncoderIJERA Editor
Due to the large requirement for memory and the high complexity of computation, JPEG2000 cannot be used in
many conditions especially in the memory constraint equipment. The line-based W avelet transform was
proposed and accepted because lower memory is required without affecting the result of W avelet transform, In
this paper, the improved lifting schem e is introduced to perform W avelet transform to replace Mallat method
that is used in the original line-based wavelet transform. In this a three-adder unit is adopted to realize lifting
scheme. It can perform wavelet transform with less computation and reduce memory than Mallat algorithm. The
corresponding HS_SPIHT coding is designed here so that the proposed algorithm is more suitable for
equipment. W e proposed a highly scale image compression scheme based on the Set Partitioning in
Hierarchical Trees (SPIHT) algorithm. Our algorithm, called Highly Scalable SPIHT (HS_SPIHT), supports
High Compression efficiency, spatial and SNR scalability and provides l bit stream that can be easily adapted to
give bandwidth and resolution requirements by a simple transcoder (parse). The HS_SPIHT algorithm adds
the spatial scalability feature without sacrificing the S NR embeddedness property as found in the original
SPIHT bit stream. Highly scalable image compression scheme based on the SPIHT algorithm the proposed
algorithm used, highly scalable SPIHT (HS_SPIHT) Algorithm, adds the spatial scalability feature to the SPIHT
algorithm through the introduction of multiple resolution dependent lists and a resolution-dependent sorting
pass. SPIHT keeps the import features of the original SPIHT algorithm such as compression efficiency, full
SNR Scalability and low complexity.
High performance nb-ldpc decoder with reduction of message exchange Ieee Xpert
High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange
Review on Implementation of Fir Adaptive Filter Using Distributed Arithmatic...IJMER
Adaptive filters play very important role in signal processing application. There are several
algorithms for implementation of filters such as Least mean square (LMS), Recursive least square (RLS),
etc. The LMS algorithm is the most efficient algorithm for implementation of FIR adaptive filters. RLS
algorithm gives faster convergence as compared to LMS but the computational complexity is high in case
of RLS. An effective distributed arithmetic can be used to implement the block least mean square
algorithm (BLMS). The DA based structure uses a LUT sharing scheme to calculate the filter output and
weight increment terms of BLMS algorithm. The structure can save a number of adders. This paper
presents a literature review on the different algorithms used for implementation of FIR adaptive filters
and implementation of filters using distributed arithmetic and block LMS algorithm.
Performance Analysis of OFDM Transceiver with Folded FFT and LMS Filteridescitation
This paper presents an Orthogonal Frequency Division Multiplexing (OFDM)
transceiver that makes use of a low power Fast Fourier Transform (FFT) along with a Least
Mean Square (LMS) filter. The folded FFT is developed via folding transformation and
register minimization techniques with real values as inputs which leads to reduction in
hardware complexity by exploiting the redundancy present in computing the FFT samples
and also the amount of power consumed. A LMS filter is also designed for the purpose of
noise removal. The OFDM transceiver with the folded FFT and LMS filter is analyzed in
terms of error performance to validate the advantages of less power consumption and
hardware utilization when compared to the traditional OFDM system with conventional
FFT. The individual components and the entire OFDM system that has been proposed are
modeled using Verilog HDL and functionally verified using Xilinx ISIM simulator.
Inventory Management System and Performance of Food and Beverages Companies i...IOSR Journals
Inventory management decisions are an integral aspect of organisations. Inventory postponement as
argued by Bucklin (1965) is where a firm deliberately delays the purchase and the physical possession of
inventory items until demand or usage requirements are known with certainty. This is an effective supply chain
strategy adopted by most manufacturing organisations by reducing the inventory, and in turn reducing the cost
of obsolete stock. This study explores the relationship between inventory management and control and
performance and Food and Beverages companies in Nigeria. Secondary data were obtained from annual
financial reports and accounts of Food and Beverages companies listed on the Nigerian Stock Exchange. The
data obtained were analyzed using simple and multiple regression models. The results show that there
significant relationship between inventory management and control and the performance of Food and
Beverages companies in Nigeria. The multiple regression correlation coefficient (R) =0.996, R2=0.990 and pvalue
=0;00<0.05 The results also show the relative importance of the inventory management decisions made
by the organisation, and the implications these decisions have on the consumer. The findings show that the three
key qualities that are essential in inventory management decisions for manufacturing organisation from the
perspective of the third party logistics provider are customer satisfaction, on time delivery and order fulfillment
Gravitational Blue Shift Confirms the New Phenomenon of the Vertical Aether F...IOSR Journals
In fact, the vertical position of Michelson-Morley experiment is not the only possible explanation for the new phenomenon of the vertical Aether flow into any mass or any fundamental building block. This paper shows, for the first time, that the cosmic blue shift due to a gravitational field is a direct consequence of the vertical Aether flow into any mass. The vertical Aether speeds of different stellar objects have been given, which suggest reclassifying the categories of black holes. To confirm the theory presented, new formulas for Doppler Effect in a gravitational field and its correlation with the time dilation, as derived from the General Relativity, has also been derived. The theoretical expressions corresponding to the two experimental results have been given. Also, a new prediction has been proposed, for the first time, to confirm the theories presented in this paper.
FOLDED ARCHITECTURE FOR NON CANONICAL LEAST MEAN SQUARE ADAPTIVE DIGITAL FILT...VLSICS Design
Power consumption reduction is transpiring drift in area of VLSI digital signal processing. This gives rise
to need of minimization of silicon area which is done by folding algorithm. As silicon area decreases power
consumption of a circuit decreases. Folding is an algorithm which reduces silicon chip area by combining
various arithmetic operations into one operation by time scheduling technique. It is applied on iterative
data flow graph with appropriate folding set. Least mean square algorithm alters coefficients of Adaptive
filter in order to achieve desired output. Proposed work is focused on design of efficient VLSI architecture
for LMS adaptive filter aims at reducing mainly area which results in power consumption reduction and
hardware complexity. LMS filter structure used here is called non-canonical as transpose FIR structure is
used. Results show that numbers of adders are reduced by 37.5 % and multipliers by 33.33% without
changing characteristics of filter.
A Review of Different Methods for Booth MultiplierIJERA Editor
In this review paper, different type of implementation of Booth multiplier has been studied. Multipliers has great importance in digital signal processor, so designing a high-speed multiplier is the need of the hour. Advantages of using modified booth multiplier algorithm is that the number of partial product is reduced. Different types of addition algorithms are also discussed which are used for addition operation of multiplier.
Design of Optimized FIR Filter Using FCSD Representation IJEEE
This paper presents the design and implementation of an eight order efficient FIR filter for wireless communication system. In this work, factored canonical signed digit representation (FCSD) is used for representing the filter coefficients in order to reduce the design complexity, area and delay of the FIR filter. Complexity of the system has been reduced by replacing binary coefficients with FCSD representation. Further area and delay has been improved by replacing multiplication operation with add and shift method where carry save adder (CSA) is used for addition of two numbers and barrel shifter is used for shifting the data words. Representation of coefficient in the FCSD format along with fastest adder and shifter improves the performance of the system. FIR filter has been designed using an equiripple method in MATLAB and further synthesized on Spartan 3E XC3S500E target FPGA device. Simulation results show that optimized FCSD based FIR filter offers a less number of slices, look up tables (LUTs) and flip-flops as compared to CSD and conventional FCSD based FIR filter, in addition to enhanced performance.
37 9144 new technique based peasant multiplication (edit lafi)IAESIJEECS
The Direct Form FIR channel is utilized for DSP application where the channel request is settled. For the most part this channel devours more range and power. To defeat this issue Multiplier Control Signal Decision window (MCSD) plans is joined into Direct Form FIR channel to powerfully change the channel arrange. MCSD structures comprise of Control flag Generator (CG) and Amplitude Detection (AD) rationale circuits. Advertisement rationale is utilized to disavow the correct duplication process and screen the amplitudes of information tests. CG is utilized to control the channel operation through inside counter. Traditional reconfigurable FIR channel is planned utilizing Vedic Multiplier that devours more territory and deferral. In this paper, changed reconfigurable FIR filer is intended to additionally decrease the APT (Area, Power and Timing) item. The proposed Reconfigurable FIR filer, Vedic Multiplier is supplanted by Russian Peasant Multiplication procedure. Subsequently adjusted Reconfigurable FIR channel with Russian Peasant Multiplier expends less region, postponement and power than all analyzed techniques.
Low Memory Low Complexity Image Compression Using HSSPIHT EncoderIJERA Editor
Due to the large requirement for memory and the high complexity of computation, JPEG2000 cannot be used in
many conditions especially in the memory constraint equipment. The line-based W avelet transform was
proposed and accepted because lower memory is required without affecting the result of W avelet transform, In
this paper, the improved lifting schem e is introduced to perform W avelet transform to replace Mallat method
that is used in the original line-based wavelet transform. In this a three-adder unit is adopted to realize lifting
scheme. It can perform wavelet transform with less computation and reduce memory than Mallat algorithm. The
corresponding HS_SPIHT coding is designed here so that the proposed algorithm is more suitable for
equipment. W e proposed a highly scale image compression scheme based on the Set Partitioning in
Hierarchical Trees (SPIHT) algorithm. Our algorithm, called Highly Scalable SPIHT (HS_SPIHT), supports
High Compression efficiency, spatial and SNR scalability and provides l bit stream that can be easily adapted to
give bandwidth and resolution requirements by a simple transcoder (parse). The HS_SPIHT algorithm adds
the spatial scalability feature without sacrificing the S NR embeddedness property as found in the original
SPIHT bit stream. Highly scalable image compression scheme based on the SPIHT algorithm the proposed
algorithm used, highly scalable SPIHT (HS_SPIHT) Algorithm, adds the spatial scalability feature to the SPIHT
algorithm through the introduction of multiple resolution dependent lists and a resolution-dependent sorting
pass. SPIHT keeps the import features of the original SPIHT algorithm such as compression efficiency, full
SNR Scalability and low complexity.
High performance nb-ldpc decoder with reduction of message exchange Ieee Xpert
High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange High performance nb-ldpc decoder with reduction of message exchange
Review on Implementation of Fir Adaptive Filter Using Distributed Arithmatic...IJMER
Adaptive filters play very important role in signal processing application. There are several
algorithms for implementation of filters such as Least mean square (LMS), Recursive least square (RLS),
etc. The LMS algorithm is the most efficient algorithm for implementation of FIR adaptive filters. RLS
algorithm gives faster convergence as compared to LMS but the computational complexity is high in case
of RLS. An effective distributed arithmetic can be used to implement the block least mean square
algorithm (BLMS). The DA based structure uses a LUT sharing scheme to calculate the filter output and
weight increment terms of BLMS algorithm. The structure can save a number of adders. This paper
presents a literature review on the different algorithms used for implementation of FIR adaptive filters
and implementation of filters using distributed arithmetic and block LMS algorithm.
Performance Analysis of OFDM Transceiver with Folded FFT and LMS Filteridescitation
This paper presents an Orthogonal Frequency Division Multiplexing (OFDM)
transceiver that makes use of a low power Fast Fourier Transform (FFT) along with a Least
Mean Square (LMS) filter. The folded FFT is developed via folding transformation and
register minimization techniques with real values as inputs which leads to reduction in
hardware complexity by exploiting the redundancy present in computing the FFT samples
and also the amount of power consumed. A LMS filter is also designed for the purpose of
noise removal. The OFDM transceiver with the folded FFT and LMS filter is analyzed in
terms of error performance to validate the advantages of less power consumption and
hardware utilization when compared to the traditional OFDM system with conventional
FFT. The individual components and the entire OFDM system that has been proposed are
modeled using Verilog HDL and functionally verified using Xilinx ISIM simulator.
Inventory Management System and Performance of Food and Beverages Companies i...IOSR Journals
Inventory management decisions are an integral aspect of organisations. Inventory postponement as
argued by Bucklin (1965) is where a firm deliberately delays the purchase and the physical possession of
inventory items until demand or usage requirements are known with certainty. This is an effective supply chain
strategy adopted by most manufacturing organisations by reducing the inventory, and in turn reducing the cost
of obsolete stock. This study explores the relationship between inventory management and control and
performance and Food and Beverages companies in Nigeria. Secondary data were obtained from annual
financial reports and accounts of Food and Beverages companies listed on the Nigerian Stock Exchange. The
data obtained were analyzed using simple and multiple regression models. The results show that there
significant relationship between inventory management and control and the performance of Food and
Beverages companies in Nigeria. The multiple regression correlation coefficient (R) =0.996, R2=0.990 and pvalue
=0;00<0.05 The results also show the relative importance of the inventory management decisions made
by the organisation, and the implications these decisions have on the consumer. The findings show that the three
key qualities that are essential in inventory management decisions for manufacturing organisation from the
perspective of the third party logistics provider are customer satisfaction, on time delivery and order fulfillment
Gravitational Blue Shift Confirms the New Phenomenon of the Vertical Aether F...IOSR Journals
In fact, the vertical position of Michelson-Morley experiment is not the only possible explanation for the new phenomenon of the vertical Aether flow into any mass or any fundamental building block. This paper shows, for the first time, that the cosmic blue shift due to a gravitational field is a direct consequence of the vertical Aether flow into any mass. The vertical Aether speeds of different stellar objects have been given, which suggest reclassifying the categories of black holes. To confirm the theory presented, new formulas for Doppler Effect in a gravitational field and its correlation with the time dilation, as derived from the General Relativity, has also been derived. The theoretical expressions corresponding to the two experimental results have been given. Also, a new prediction has been proposed, for the first time, to confirm the theories presented in this paper.
AM Fungal Status in Ketaka: Pandanus fascicularis From Coastal Region of Konk...IOSR Journals
Present paper deals with assessment of Arbuscular mycorrhizal fungi (AM) associated with different populations of Pandanus fascicularis found in coastal region of Konkan Maharashtra. All samples of P. fascicularis roots were colonized by AM fungi. The mean percentage of root length colonization ranged from 39% to 74%. Amongst the thirteen AM fungal morphospecies Kuklospora colombiana was the most widely distributed species. Species richness of AM fungi ranged from 3 to 6. Based on spore density and relative abundance, three species were dominant viz., Acaulospora bireticulata, A. scrobiculata, and K. colombiana. Details of AM fungal status in P. fascicularis are discussed in present paper.
To Study The Viscometric Measurement Of Substituted-2-Diphenylbutanamide And ...IOSR Journals
Recently in this laboratory the viscometric measurement of 4-[4-(4-chlorophenyl]-4-hydroxy piperidin-1-yl]-N, N-dimethyl-2, 2-diphenylbutanamide[CPHDD] and (2S, 6R)-7-chloro -2, 4, 6-trimethoxy-6'-methyl-3H, 4'H-spiro[1-benzofuran 2, 1’-] cychohex-2-ene]-3,4'-dione[CTMBCD] were carried out at different percentage compositions of solvent to investigate the solute-solvent interactions of drugs with solvent and the effect of dilution of the solvent. The effects of various substituents were also investigated. The results obtained during this investigation gave detail information about pharmacokinetics and pharmacodynamics of these drugs.
Modeling Of Flat Plate Collector by Using Hybrid TechniqueIOSR Journals
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system speed. The implementation of FIR filters on FPGA based on traditional method costs considerable
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resources through using LUT to take the place of MAC units
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This Paper is a review study of FPGA implementation of Finite Impulse response (FIR) with low cost and high performance. The key observation of this paper is an elaborate analysis about hardware implementations of FIR filters using different algorithm i.e., Distributed Arithmetic (DA), DA-Offset Binary Coding (DA-OBC), Common Sub-expression Elimination (CSE) and sum-of-power-of-two (SOPOT) with less resources and without affecting the performance of the original FIR Filter.
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A Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithmetic with Decomposed LUT
1. IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)
e-ISSN: 2278-2834,p- ISSN: 2278-8735.Volume 7, Issue 2 (Jul. - Aug. 2013), PP 13-18
www.iosrjournals.org
www.iosrjournals.org 13 | Page
A Novel Approach of Area-Efficient FIR Filter Design Using
Distributed Arithmetic with Decomposed LUT
1
P.Sravanthi, 2
CH.Srinivasa Rao, 3
S.Madhava Rao,
1
M.TECH student, MLE College of Engineering, S.Konda, prakasam(DT), A.P,
2,3
ASSOC.Professor, MLECollege, singarayakonda, prakasam, A.P, INDIA,
Abstract: In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic
(DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking
optimal advantage of the 3-input LUT-based structure of FPGAs. The implementation of FIR filters on FPGA
based on traditional arithmetic method costs considerable hardware resources, which goes against the decrease
of circuit scale and the increase of system speed. This paper presents the realization of area efficient
architectures using Distributed Arithmetic (DA) for implementation of Finite Impulse Response (FIR) filter. The
performance of the bit-serial and bit parallel DA along with pipelining architecture with different quantized
versions are analyzed for FIR filter Design. Distributed Arithmetic structure is used to increase the resource
usage while pipeline structure is also used to increase the system speed. In addition, the divided LUT method is
also used to decrease the required memory units. However, according to Distributed Arithmetic, we can make a
Look-Up-Table (LUT) to conserve the MAC values and callout the values according to the input data if
necessary. Therefore, LUT can be created to take the place of MAC units so as to save the hardware resources.
The simulation results indicate that FIR filters using Distributed Arithmetic can work stable with high speed and
can save almost 50 percent hardware resources to decrease the circuit scale, and can be applied to a variety of
areas for its great flexibility and high reliability. This method not only reduces the LUT size, but also modifies
the structure of the filter to achieve high speed performance.
Keywords: DSP, Digital Filters, FIR , FPGA, MAC, Distributed Arithmetic(DA),Divided LUT, pipeline
I. Introduction
In the recent years, there has been a growing trend to implement digital signal processing functions in
Field Programmable Gate Array (FPGA). In this sense, we need to put great effort in designing efficient
architectures for digital signal processing functions such as FIR filters, which are widely used in video and
audio signal processing, telecommunications and etc.
Traditionally, direct implementation of a K-tap FIR filter requires K multiply-and-accumulate (MAC)
blocks, which are expensive to implement in FPGA due to logic complexity and resource usage. To resolve this
issue, we first present DA, which is a multiplier-less architecture.
Implementing multipliers using the logic fabric of the FPGA is costly due to logic complexity and area
usage, especially when the filter size is large. Modern FPGAs have dedicated DSP blocks that alleviate this
problem, however for very large filter sizes the challenge of reducing area and complexity still remains. An
alternative to computing the multiplication is to decompose the MAC operations into a series of lookup table
(LUT) accesses and summations. This approach is termed distributed arithmetic (DA), a bit serial method of
computing the inner product of two vectors with a fixed number of cycles.
The original DA architecture stores all the possible binary combinations of the coefficients w[k] of
equation (1) in a memory or lookup table[5,7,9]. It is evident that for large values of L, the size of the memory
containing the pre computed terms grows exponentially too large to be practical. The memory size can be
reduced by dividing the single large memory (2Lwords) into m multiple smaller sized memories each of size 2k
where L = m × k. The memory size can be further reduced to 2L−1 and 2L−2 by applying offset binary
coding and exploiting resultant symmetries found in the contents of the memories[8,9].
This technique is based on using 2's complement binary representation of data, and the data can be pre-
computed and stored in LUT. As DA is a very efficient solution especially suited for LUT-based FPGA
architectures, many researchers put great effort in using DA to implement FIR filters in FPGA. Patrick Longa
introduced the structure of the FIR filter using DA algorithm and the functions of each part. Sangyun Hwang
analyzed the power consumption of the filter using DA algorithm[3,7]. Heejong Yoo proposed a modified DA
architecture that gradually replaces LUT requirements with multiplexer/adder pairs. But the main problem of
DA is that the requirement of LUT capacity increases exponentially with the order of the filter, given that DA
implementations need 2Kwords (K is the number of taps of the filter)[4,5,10]. And if K is a prime, the hardware
resource consumption will cost even higher. To overcome these problems, this paper presents a hardware-
efficient DA architecture.
2. A Novel Approch Of Area-Efficient Fir Filter Design Using Distributed Arithmetic With Decomposed
www.iosrjournals.org 14 | Page
This method not only reduces the LUT size, but also modifies the structure of the filter to achieve high
speed performance. The proposed filter has been designed and synthesized with ISE 7.1, and implemented with
a 4VLX40FF668 FPGA device. [2] Our results show that the proposed DA architecture can implement
FIR filters with high speed and smaller resource usage in comparison to the previous DA architecture.
II. Design Methodology
2.1 Distributed Arithmetic FIR filter architecture
Distributed Arithmetic is one of the most well-known methods of implementing FIR filters. The DA
solves the computation of the inner product equation when the coefficients are pre knowledge, as happens in
FIR filters.
An FIR filter of length K is described as:
1
0
][][][
K
k
knxkhny --(1)
Where h[k] is the filter coefficient and x[k] is the input data. For the convenience of analysis, x'[k] =x
[n - k] is used for modifying the equation (1) and we have:
1
0
'
][].[
K
k
kxkhy ........(2)
Then we use B-bit two's complement binary numbers to represent the input data:
1
0
'
2][][2][
B
b
b
bB
B
kxkxkx -(3)
Where ][kxb denotes the b’th bit of x[k], ][kxb {0, 1}.Substitution of (3) into (2) yields:
1
0
1
0
)2][][2(][
K
k
B
b
b
bB
B
kxkxkhy
1
0
1
0
1
0
][][2][][2
K
k
B
b
K
k
b
b
B
B
kxkhkxkh
])[],[(2])[],[(2
1
0
kxkhfkxkhf b
B
b
b
B
B
- (4)
We have
][][])[],[(
1
0
kxkhkxkhf b
K
k
b
In equation (4), we observe that the filter coefficients can be pre-stored in LUT, and addressed by xb =
[ ]0[bx , ]1[bx ,... ]1[ Kxb ].This way, the MAC blocks of FIR filters are reduced to access and summation
with LUT.
The implementation of digital filters using this arithmetic is done by using registers, memory resources
and a scaling accumulator.
Original LUT-based DA implementation of a 4-tap (K=4) FIR filter is shown in Figure 2.1. The DA
architecture includes three units: the shift register unit, the DA-LUT unit, and the adder/shifter unit.
Figure 2.1: Original LUT-based DA implementation of a 4-tap filter
3. A Novel Approch Of Area-Efficient Fir Filter Design Using Distributed Arithmetic With Decomposed
www.iosrjournals.org 15 | Page
2.2 Distributed Arithmetic Architecture With Out Lut:
In Fig. 2.1, we can see that the lower half of LUT (locations where 3b =1) is the same with the sum of
the upper half of LUT (locations where 3b =0) and h [3]. Hence, LUT size can be reduced 1/2 with an additional
2x1 multiplexer and a full adder, as shown in Figure 2.2.2(a).
By the same LUT reduction procedure, we can have the final LUT-less DA architectures, as shown in
Figure 2.2.2(b). On other side, for the use of combination logic circuit, the filter performance will be affected.
But when the taps of the filter is a prime, we can use 4-input LUT units with additional multiplexers and full
adders to get the trade off between filter performance and small resource usage.
Figure 2.2.2(a): Proposed DA architecture for a 4-tap filter (
3
2 word LUT implementation of DA)
Figure 2.2.2(b): LUT-less DA architectures
III. Distributed Arithmetic With
4-Input Look Up Table Architecture
The main advantage of FIR filters is their linear-phase response. It is only achieved with symmetrical
or ant symmetrical structures which, furthermore, offer hardware reductions.
As the filter order K increases, the LUT size (
K
2 words) grows exponentially. With this it is difficult
to implement the architecture using lut less method as more and more combinational logic is needed. This
resulted in a new architecture which is explained below.
3.1 Four input look up table architecture:
As the filter order K increases, the LUT size (
K
2 words) grows exponentially. We can divide the K-
tap FIR filter into L groups of smaller filters (K = L *M). Hence the LUT size is reduced to
M
L 2 words,
and then we have:
1
0
1
0
1
0
][][][][
LM
k
L
l
M
m
mlMxmlMhkxkhy
4. A Novel Approch Of Area-Efficient Fir Filter Design Using Distributed Arithmetic With Decomposed
www.iosrjournals.org 16 | Page
We would better set M=4, because only under this condition can we take optimal advantage based on
the 4-input LUT structure of FPGA, as shown in Fig 3.1. If we can not obtain M=4 after the calculation, we can
use both the proposed DA-LUT unit and the original 4-input DA-LUT unit to achieve our goal.
Xb[0] …. .x1[0] x0[0]
LUT
LUT
LUT
LUT
ACC+/-
+
+
+
Xb[M-1] .. .x1[M-1] x0[M-1]
Xb[M] …. x1[M] x0[M]
Xb[2M-1] … x1[2M-1] x0[2M-1]
Xb[2M] … x1[2M] x0[2M]
Xb[3M-1] .... x1[3M-1] x0[3M-1]
Xb[3M] .. x1[3M] x0[3M]
Xb[4M-1] .. x1[4M-1] x0[4M-1]
t
2
Figure 3.1 DISTRIBUTED ARITHMETIC WITH 4-INPUT LOOK UP TABLE
IV. Simulation Results:
Matlab and Modelsim are used as the simulation platforms. We can analysis the changes between the
input wave and the output wave to observe the permanence of the designed filter through Matlab , while
observing the real-time implementation performance of FPGA through Modelsim.
To observe the performance of the designed filter, a square signal of 1.6MHz is generated as the input
by Matlab, and the sampling frequency is 32MHz. The data is changed into the two's complement form and
stored in the file named fir_in.txt. And the data is called out later as the input of the FPGA filter through
testbench language in Modelsim, the output data is shown in the waveform workstation and also stored into the
file, which can be read by Matlab to make a contrast to analysis.
Original LUT-based DA implementation of a
4-tap filter
4-tap LUT-less DA architectures for a 4-tap FIR filter
5. A Novel Approch Of Area-Efficient Fir Filter Design Using Distributed Arithmetic With Decomposed
www.iosrjournals.org 17 | Page
4-input look up table architecture for high order filters Without pipelining
4-input look up table architecture with pipelining
Fully parallel DA architecture FIR filter without pipelining
Fully parallel DA architecture FIR filter with pipelining
V. Conclusion And Future Scope
This paper presents the proposed DA architectures for high-order filters. The architectures reduce the
memory usage by half at every iteration of LUT reduction at the cost of the limited decrease of the system
frequency. We also divide the high-order filters into several groups of small filters; hence we can reduce the
LUT size also. As to get the high speed implementation of FIR filters, a full-parallel version of the DA
architecture is adopted.
We have successfully implemented a high-efficient 70-tap full-parallel DA filter, using both an original
DA architecture and a modified DA architecture on a 4VLX40FF668 FPGA device. It shows that the proposed
DA architectures are hardware efficient for FPGA implementation. The limitation of this project is that by the
use of pipelining speed is increased however, the resource usage increase more than B times of the bit-serial
one's, since we need to use pipeline registers and additional adders. Also the number of LUT’s required would
be enormous. The future scope of this project is to improve the architecture of the Distributed arithmetic FIR
filter such that it uses the hardware resources of the latest FPGA families. In vertex-5 and Vertex-6 family
FPGA’s, 6-input LUT’s were introduced. Future work includes changing the architecture which uses 6-input
6. A Novel Approch Of Area-Efficient Fir Filter Design Using Distributed Arithmetic With Decomposed
www.iosrjournals.org 18 | Page
LUT’s for storing coefficient sums and SRL(Shift register logic) macros to implement shift operations such that
total number of slices used will be reduced.
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