This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DAfinite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
The document describes the design and implementation of an efficient interpolator for wireless communication systems using FPGA. It proposes a multiplier-less technique using distributed arithmetic look-up tables (DALUT) that replaces multiply-accumulate operations with LUT accesses. A 66th-order half-band polyphase FIR structure is implemented using the DALUT approach on Spartan-3E and Virtex2Pro FPGAs. Results show the proposed design achieves maximum frequencies of 92.859MHz on Virtex Pro and 61.6MHz on Spartan 3E while consuming fewer resources than a traditional MAC-based design.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
This document summarizes a research paper on hardware efficient reconfigurable FIR filters. It discusses two new architectures proposed: the constant shifts method (CSM) and programmable shifts method (PSM). CSM partitions coefficients into fixed groups and stores them directly in a lookup table. PSM eliminates redundancy in coefficients using a binary common subexpression algorithm before storing in a coded format. Both methods use a shift-and-add unit and multiplexers to efficiently implement coefficient multiplication and allow reconfiguration for different standards. The architectures aim to integrate reconfigurability with low complexity for FIR filters used in wireless communications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
This document discusses the design and analysis of multirate filters for WiMAX applications. It proposes a programmable multirate filter architecture that can be implemented using software-defined radio technology and multirate signal processing principles. The filters are designed using MATLAB's filter design and analysis tool to meet WiMAX specifications. A digital upconverter is presented that uses three cascaded FIR filters with interpolation factors of 1, 2, and 4 to achieve an overall interpolation factor of 8 as required by WiMAX. The filters are analyzed and simulated in MATLAB to verify they satisfy WiMAX's spectral mask requirements.
Design of Area Efficient Digital FIR Filter using MACIRJET Journal
This document describes the design of an area efficient digital FIR filter using a single MAC (multiply-accumulate) unit. It begins with an introduction to digital filters and FIR filters. It then discusses related work on optimizing FIR filter design through techniques like coefficient quantization and constant multiplication. The proposed methodology involves specifying the FIR filter, generating coefficients by rounding to integers, and designing the filter architecture using a single MAC unit, multiplexers, and other components. This approach aims to reduce area by avoiding two's complement circuits and using a single MAC unit instead of multiple parallel multipliers. The document concludes the proposed work provides a good direction for optimizing the area of digital filters.
IRJET- A Digital Down Converter on Zynq SoCIRJET Journal
This document describes the design and implementation of a digital down converter (DDC) on a Zynq System on Chip (SoC). Key points:
- The DDC is designed for airborne radar receivers to downconvert high sample rate digitized signals to a lower frequency for easier processing.
- The DDC implementation includes a direct digital synthesizer to generate input signals, complex multiplication for mixing, and a two-stage decimation and filtering process.
- The design is implemented on a Zynq SoC which provides the flexibility of a processor and programmability of an FPGA.
- Results show the DDC design achieves significant improvements in resource utilization compared to a full
Power efficient and high throughput of fir filter using block least mean squa...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
The document describes the design and implementation of an efficient interpolator for wireless communication systems using FPGA. It proposes a multiplier-less technique using distributed arithmetic look-up tables (DALUT) that replaces multiply-accumulate operations with LUT accesses. A 66th-order half-band polyphase FIR structure is implemented using the DALUT approach on Spartan-3E and Virtex2Pro FPGAs. Results show the proposed design achieves maximum frequencies of 92.859MHz on Virtex Pro and 61.6MHz on Spartan 3E while consuming fewer resources than a traditional MAC-based design.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
This document summarizes a research paper on hardware efficient reconfigurable FIR filters. It discusses two new architectures proposed: the constant shifts method (CSM) and programmable shifts method (PSM). CSM partitions coefficients into fixed groups and stores them directly in a lookup table. PSM eliminates redundancy in coefficients using a binary common subexpression algorithm before storing in a coded format. Both methods use a shift-and-add unit and multiplexers to efficiently implement coefficient multiplication and allow reconfiguration for different standards. The architectures aim to integrate reconfigurability with low complexity for FIR filters used in wireless communications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
This document discusses the design and analysis of multirate filters for WiMAX applications. It proposes a programmable multirate filter architecture that can be implemented using software-defined radio technology and multirate signal processing principles. The filters are designed using MATLAB's filter design and analysis tool to meet WiMAX specifications. A digital upconverter is presented that uses three cascaded FIR filters with interpolation factors of 1, 2, and 4 to achieve an overall interpolation factor of 8 as required by WiMAX. The filters are analyzed and simulated in MATLAB to verify they satisfy WiMAX's spectral mask requirements.
Design of Area Efficient Digital FIR Filter using MACIRJET Journal
This document describes the design of an area efficient digital FIR filter using a single MAC (multiply-accumulate) unit. It begins with an introduction to digital filters and FIR filters. It then discusses related work on optimizing FIR filter design through techniques like coefficient quantization and constant multiplication. The proposed methodology involves specifying the FIR filter, generating coefficients by rounding to integers, and designing the filter architecture using a single MAC unit, multiplexers, and other components. This approach aims to reduce area by avoiding two's complement circuits and using a single MAC unit instead of multiple parallel multipliers. The document concludes the proposed work provides a good direction for optimizing the area of digital filters.
IRJET- A Digital Down Converter on Zynq SoCIRJET Journal
This document describes the design and implementation of a digital down converter (DDC) on a Zynq System on Chip (SoC). Key points:
- The DDC is designed for airborne radar receivers to downconvert high sample rate digitized signals to a lower frequency for easier processing.
- The DDC implementation includes a direct digital synthesizer to generate input signals, complex multiplication for mixing, and a two-stage decimation and filtering process.
- The design is implemented on a Zynq SoC which provides the flexibility of a processor and programmability of an FPGA.
- Results show the DDC design achieves significant improvements in resource utilization compared to a full
Power efficient and high throughput of fir filter using block least mean squa...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
The document describes an efficient hardware co-simulation approach for designing a digital down converter (DDC) for software defined radios. The proposed DDC uses optimal equiripple techniques to reduce resource requirements. It employs a computationally efficient polyphase decomposition structure to improve hardware complexity. The DDC is implemented using embedded multipliers, lookup tables, and block RAMs of a Virtex-II Pro FPGA. Simulation results show the DDC can operate at 160 MHz while consuming 0.34004W. It utilizes few FPGA resources, providing a cost-effective solution for software defined radio applications.
FPGA Implementation of Optimized CIC Filter for Sample Rate Conversion in Sof...idescitation
A software radio receiver is one which is tuned to
receive a transmitted signal on multiple communication
standards through software rather than hardware. To
incorporate multi-standard radio communications an
intermediate frequency of high ranges is used. Such high
intermediate frequencies when sampled with Nyquist rate
gets oversampled due to the phenomenon of Band Pass
sampling depending on the radio communication standard.
Hence a digital down converter (DDC) capable of reducing
the sampling rate in accordance with the radio communication
standard is required. Cascaded Integrated Comb (CIC) filters
are used for large sample rate conversion factors. In this paper
an optimized architecture for DDC employing CORDIC in
the mixer stage and the reconfigurable decimation factors for
CIC filters has been implemented. Optimized implementation
of CIC filter for sample rate conversion of multi-standard
radio communications reduces the hardware resources by more
than twenty percent when compared with the non-optimized
architecture.
This document summarizes a research paper on designing low power digit serial finite impulse response (FIR) filters using multiple constant multiplication (MCM) techniques. It proposes an architecture that optimizes the area of digit serial MCM operations at the gate level by considering the implementation costs of digit serial addition, subtraction and shift operations. An algorithm is presented to design digit serial FIR filters under a shift-adds architecture to reduce area compared to designs using generic digit serial multipliers. Experimental results show the technique leads to lower complexity digit serial MCM designs.
IRJET- Low Complexity and Critical Path Based VLSI Architecture for LMS A...IRJET Journal
This document proposes a low complexity and critical path based VLSI architecture for an LMS adaptive filter. It presents a Booth multiplier based FIR filter with fixed coefficients to reduce complexity. A variable coefficient FIR filter is then proposed that applies the LMS algorithm to adapt filter coefficients and minimize error. Design considerations including hardware resources and power consumption are discussed. Simulation results show the proposed filter removes noise from an input signal while using less logic than other FIR filter designs through Booth recoding and selective multiplication techniques.
Design of Optimized FIR Filter Using FCSD Representation IJEEE
This paper presents the design and implementation of an eight order efficient FIR filter for wireless communication system. In this work, factored canonical signed digit representation (FCSD) is used for representing the filter coefficients in order to reduce the design complexity, area and delay of the FIR filter. Complexity of the system has been reduced by replacing binary coefficients with FCSD representation. Further area and delay has been improved by replacing multiplication operation with add and shift method where carry save adder (CSA) is used for addition of two numbers and barrel shifter is used for shifting the data words. Representation of coefficient in the FCSD format along with fastest adder and shifter improves the performance of the system. FIR filter has been designed using an equiripple method in MATLAB and further synthesized on Spartan 3E XC3S500E target FPGA device. Simulation results show that optimized FCSD based FIR filter offers a less number of slices, look up tables (LUTs) and flip-flops as compared to CSD and conventional FCSD based FIR filter, in addition to enhanced performance.
IRJET- Decimator Filter for Hearing Aid Application Based on FPGAIRJET Journal
This document describes a proposed decimation filter design for hearing aid applications using FPGAs. The filter uses a cascaded integrator comb (CIC) filter to downsample the signal, followed by a half-band FIR filter and corrector FIR filter. The design is simulated in MATLAB and implemented on an FPGA using VHDL. Decimation filters can help hearing aid users by amplifying sounds and reducing the sampling frequency in a way that matches the individual's audiogram. The proposed filter structure aims to reduce complexity, power consumption, and improve performance for digital hearing aids.
Survey of Optimization of FFT processor for OFDM Receiversijsrd.com
This document summarizes research on optimizing FFT processors for OFDM receivers. It discusses how FFT/IFFT algorithms are critical components of OFDM systems that require optimization for throughput, area, and power. The document reviews different FFT processor architectures like pipelined and parallel. It proposes a FFT processor with a pipelined architecture and a CORDIC-based ROM-free twiddle factor generator to reduce complexity. Simulation results using MATLAB show the performance of an OFDM receiver with a 512-point FFT. The conclusion is that a pipelined architecture with CORDIC twiddle factor generation optimizes FFT processor performance for OFDM receivers.
IRJET- The RTL Model of a Reconfigurable Pipelined MCMIRJET Journal
This document presents two Register Transfer Level (RTL) models for a reconfigurable pipelined multiple constant multiplier (MCM) architecture. The first model uses a ripple carry adder, while the second model replaces it with a carry lookahead adder. Both models are constructed using Verilog and simulated using ModelSim. Simulation results show the second model has a 3.53% higher maximum clock frequency and throughput due to the faster carry lookahead adder. It also has 3.53% lower latency but uses 1.65% more power. The second model provides faster performance with moderate increases in resource usage and power consumption.
Area Efficient and high-speed fir filter implementation using divided LUT methodIJMER
Traditional method of implementing FIR filters costs considerable hardware resourses,
which goes against the decrease of circuit scale and the increase of system speed. A new design and
implementation of FIR filters using Distributed Arithmetic is provided in this paper to slove this
problem. Distributed Arithmetic structure is used to increase the resourse useage while pipeline
structure is also used to increase the system speed. In addition, the devided LUT method is also used to
decrease the required memory units. The simulation results indicate that FIR filters using Distributed
Arithmetic can work stable with high speed and can save almost 50 percent hardware resourses to
decrease the circuit scale, and can be applied to a variety of areas for its great flexibility and high
reliability
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
This document compares the complexity and cost-effectiveness of different types of filters, including IIR, FIR, polyphase, and linear phase filters. It analyzes two cases with different filter parameters and calculates the number of multiplications per input sample (MPIS) for each filter type. The results show that polyphase filters significantly reduce the MPIS compared to traditional FIR or IIR filters, making them more cost-effective for implementation. Polyphase and multistage IIR polyphase filters in particular achieve a very low number of multiplications.
Design of Multiplier Less 32 Tap FIR Filter using VHDLIJMER
This Paper provide the principles of Distributed Arithmetic, and introduce it into the FIR
filters design, and then presents a 32-Tap FIR low-pass filter using Distributed Arithmetic, which save
considerable MAC blocks to decrease the circuit scale and pipeline structure is also used to increase the
system speed. The implementation of FIR filters on FPGA based on traditional method costs considerable
hardware resources, which goes against the decrease of circuit scale and the increase of system speed.
It is very well known that the FIR filter consists of Delay elements, Multipliers and Adders. Because of
usage of Multipliers in early design gives rise to 2 demerits that are:
(i) Increase in Area and
(ii) Increase in the Delay which ultimately results in low performance (Less speed).
So the Distributed Arithmetic for FIR Filter design and Implementation is provided in this work to solve
this problem. Distributed Arithmetic structure is used to increase the recourse usage and pipeline
structure is used to increase the system speed. Distributed Arithmetic can save considerable hardware
resources through using LUT to take the place of MAC units
Implementation Cost Analysis of the Interpolator for the Wimax Technologyiosrjce
The design of the multirate filter (programmable) has been proposed which can be used in digital
transceivers that meets 802.16d/e (wimax) standard in the wireless communication system. Wimax is a
technology emerging in the wireless communication system in order to increase the broadband wireless internet
access. As there is wide spread need of the digital representation of the signal for the transmission and storage
which create the challenges in DSP [1]. In this paper, analysis of the implementation cost of interpolator for the
wimax technology, and cost of interpolator is analyzed on the basis of number of adders and multiplier. The
Filters are designed using the FDA (filters design and analysis) tool in MATLAB.
DSM Based low oversampling using SDR transmitterIJTET Journal
The oversampling recruitment is a limiting factor in high frequency application such as software defined radio. This project is a high frequency processing and low oversampling ratio. A single bit semi parallel processing is proposed in this paper. Using this single bit PDSM Architecture, high speed, high complexity computations are executed in parallel. The single bit DSM is to build an RF transmitter that includes a one bit quantifier with two level switching power amplifier for high linearity and high efficiency. Performance analysis by using the MATLAB simulations by reducing the oversampling ratio by same signal to noise ratio. The DSM implemented on field programmable gate array and using a signal code division multiple access signal. This project will give bandwidth of the low oversampled signal increased four times without increasing frequency. Finally they can be achieved signal to noise ratio is very low and also oversampling ratio is small.
This document analyzes the performance of digital audio broadcasting (DAB) systems using orthogonal frequency division multiplexing (OFDM) and Reed Solomon coding. It discusses the components of a DAB system including source coding, channel coding using Reed Solomon codes, transmission frame structure, and coded OFDM. Simulation results show the bit error rate versus signal-to-noise ratio for DAB modes I and II, demonstrating lower bit error rates at higher signal-to-noise ratios when using Reed Solomon coding compared to previous work. The document concludes the analysis and discusses limitations and potential future work.
Comparison study of 8-PPM, 8-DPIM, and 8-RDH-PIM modulator FPGA hardware desi...journalBEEI
In this paper, a performance study of 8-Pulse-Position Modulation (PPM), 8-Digital Pulse Interval Modulation (DPIM), and 8-Reverse Dual Header-Pulse Interval Modulation (RDH-PIM) implementation in Verilog hardware design language is presented. The hardware design is chosen over software design since it could provide much more flexibility in term of transmission rate and reduce the workload of the processor in the complete system. Using 50 MHz clock as the reference data clock speeds, the transmission rate recorded are 11.11 Msymbol/second or 33.33 Mbps, 9.09 Msymbol/s or 27.27 Mbps, and 6.25 Msymbol/s or 18.75 Mbps for 8-RDH-PIM, 8-DPIM, and 8-PPM respectively. We conclude that 8-RDH-PIM modulator design provides better performance in term of bandwidth utilization and transmission rate as compared to 8-PPM and 8-DPIM.
BER Performance Improvement for 4 X 4 MIMO Single Carrier FDMA System Using M...IRJET Journal
This document describes a system that aims to improve the bit error rate (BER) performance of 4x4 MIMO single-carrier frequency-division multiple access (SC-FDMA) uplink transmission. It investigates using minimum mean square error (MMSE) equalization at the receiver to better detect MIMO data over Rayleigh fading channels. Simulation results using MATLAB show that the proposed MMSE detection scheme decreases BER as signal-to-noise ratio increases for 16-QAM modulation. The BER performance is also compared to orthogonal frequency-division multiple access (OFDMA) MIMO systems, showing improved results for SC-FDMA.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to
provide signal processing in wireless communication system. There are many
applications in which sampling rate must be changed. Interpolators and decimators are
utilized to increase or decrease the sampling rate. In this paper an efficient method has
been presented to implement high speed and area efficient interpolator for wireless
communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate
operations with look up table (LUT) accesses. Interpolator has been
implemented using Partitioned distributed arithmetic look up table (DALUT)
technique. This technique has been used to take an optimal advantage of embedded
LUTs of the target FPGA. This method is useful to enhance the system performance in
terms of speed and area. The proposed interpolator has been designed using half band
poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx
Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The
proposed LUT based multiplier less approach has shown a maximum operating
frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by
consuming considerably less resources to provide cost effective solution for wireless
communication systems.
FPGA Implementation of Higher Order FIR Filter IJECEIAES
The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.
This document discusses the design and analysis of a digital down converter (DDC) for WiMAX applications using MATLAB. It contains the following key points:
1. It describes the functional blocks and design of a DDC, including a mixer, numerically controlled oscillator (NCO), and FIR filter chain.
2. It discusses WiMAX standards and requirements for DDC design in WiMAX systems.
3. It presents the windowing technique for designing FIR filters and compares different window functions to determine the best filter specifications.
Matlab Based Decimeter Design Analysis Wimax Appliacationiosrjce
The document discusses the design and analysis of a digital down converter (DDC) for WIMAX applications using MATLAB. It contains the following key points:
1. It describes the functional blocks and design of a DDC including a mixer, numerically controlled oscillator (NCO), and FIR filter chain.
2. It analyzes different window functions that can be used for FIR filter design including Kaiser, Blackman-Harris, and presents the magnitude response, phase response, and step response of filters designed using Kaiser and Blackman windows.
3. It compares the implementation cost of the filters designed using different windows by calculating the number of multipliers and adders used.
A Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithm...IOSR Journals
Abstract: In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 3-input LUT-based structure of FPGAs. The implementation of FIR filters on FPGA based on traditional arithmetic method costs considerable hardware resources, which goes against the decrease of circuit scale and the increase of system speed. This paper presents the realization of area efficient architectures using Distributed Arithmetic (DA) for implementation of Finite Impulse Response (FIR) filter. The performance of the bit-serial and bit parallel DA along with pipelining architecture with different quantized versions are analyzed for FIR filter Design. Distributed Arithmetic structure is used to increase the resource usage while pipeline structure is also used to increase the system speed. In addition, the divided LUT method is also used to decrease the required memory units. However, according to Distributed Arithmetic, we can make a Look-Up-Table (LUT) to conserve the MAC values and callout the values according to the input data if necessary. Therefore, LUT can be created to take the place of MAC units so as to save the hardware resources. The simulation results indicate that FIR filters using Distributed Arithmetic can work stable with high speed and can save almost 50 percent hardware resources to decrease the circuit scale, and can be applied to a variety of areas for its great flexibility and high reliability. This method not only reduces the LUT size, but also modifies the structure of the filter to achieve high speed performance. Keywords: DSP, Digital Filters, FIR , FPGA, MAC, Distributed Arithmetic(DA),Divided LUT, pipeline
EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
The document describes an efficient hardware co-simulation approach for designing a digital down converter (DDC) for software defined radios. The proposed DDC uses optimal equiripple techniques to reduce resource requirements. It employs a computationally efficient polyphase decomposition structure to improve hardware complexity. The DDC is implemented using embedded multipliers, lookup tables, and block RAMs of a Virtex-II Pro FPGA. Simulation results show the DDC can operate at 160 MHz while consuming 0.34004W. It utilizes few FPGA resources, providing a cost-effective solution for software defined radio applications.
FPGA Implementation of Optimized CIC Filter for Sample Rate Conversion in Sof...idescitation
A software radio receiver is one which is tuned to
receive a transmitted signal on multiple communication
standards through software rather than hardware. To
incorporate multi-standard radio communications an
intermediate frequency of high ranges is used. Such high
intermediate frequencies when sampled with Nyquist rate
gets oversampled due to the phenomenon of Band Pass
sampling depending on the radio communication standard.
Hence a digital down converter (DDC) capable of reducing
the sampling rate in accordance with the radio communication
standard is required. Cascaded Integrated Comb (CIC) filters
are used for large sample rate conversion factors. In this paper
an optimized architecture for DDC employing CORDIC in
the mixer stage and the reconfigurable decimation factors for
CIC filters has been implemented. Optimized implementation
of CIC filter for sample rate conversion of multi-standard
radio communications reduces the hardware resources by more
than twenty percent when compared with the non-optimized
architecture.
This document summarizes a research paper on designing low power digit serial finite impulse response (FIR) filters using multiple constant multiplication (MCM) techniques. It proposes an architecture that optimizes the area of digit serial MCM operations at the gate level by considering the implementation costs of digit serial addition, subtraction and shift operations. An algorithm is presented to design digit serial FIR filters under a shift-adds architecture to reduce area compared to designs using generic digit serial multipliers. Experimental results show the technique leads to lower complexity digit serial MCM designs.
IRJET- Low Complexity and Critical Path Based VLSI Architecture for LMS A...IRJET Journal
This document proposes a low complexity and critical path based VLSI architecture for an LMS adaptive filter. It presents a Booth multiplier based FIR filter with fixed coefficients to reduce complexity. A variable coefficient FIR filter is then proposed that applies the LMS algorithm to adapt filter coefficients and minimize error. Design considerations including hardware resources and power consumption are discussed. Simulation results show the proposed filter removes noise from an input signal while using less logic than other FIR filter designs through Booth recoding and selective multiplication techniques.
Design of Optimized FIR Filter Using FCSD Representation IJEEE
This paper presents the design and implementation of an eight order efficient FIR filter for wireless communication system. In this work, factored canonical signed digit representation (FCSD) is used for representing the filter coefficients in order to reduce the design complexity, area and delay of the FIR filter. Complexity of the system has been reduced by replacing binary coefficients with FCSD representation. Further area and delay has been improved by replacing multiplication operation with add and shift method where carry save adder (CSA) is used for addition of two numbers and barrel shifter is used for shifting the data words. Representation of coefficient in the FCSD format along with fastest adder and shifter improves the performance of the system. FIR filter has been designed using an equiripple method in MATLAB and further synthesized on Spartan 3E XC3S500E target FPGA device. Simulation results show that optimized FCSD based FIR filter offers a less number of slices, look up tables (LUTs) and flip-flops as compared to CSD and conventional FCSD based FIR filter, in addition to enhanced performance.
IRJET- Decimator Filter for Hearing Aid Application Based on FPGAIRJET Journal
This document describes a proposed decimation filter design for hearing aid applications using FPGAs. The filter uses a cascaded integrator comb (CIC) filter to downsample the signal, followed by a half-band FIR filter and corrector FIR filter. The design is simulated in MATLAB and implemented on an FPGA using VHDL. Decimation filters can help hearing aid users by amplifying sounds and reducing the sampling frequency in a way that matches the individual's audiogram. The proposed filter structure aims to reduce complexity, power consumption, and improve performance for digital hearing aids.
Survey of Optimization of FFT processor for OFDM Receiversijsrd.com
This document summarizes research on optimizing FFT processors for OFDM receivers. It discusses how FFT/IFFT algorithms are critical components of OFDM systems that require optimization for throughput, area, and power. The document reviews different FFT processor architectures like pipelined and parallel. It proposes a FFT processor with a pipelined architecture and a CORDIC-based ROM-free twiddle factor generator to reduce complexity. Simulation results using MATLAB show the performance of an OFDM receiver with a 512-point FFT. The conclusion is that a pipelined architecture with CORDIC twiddle factor generation optimizes FFT processor performance for OFDM receivers.
IRJET- The RTL Model of a Reconfigurable Pipelined MCMIRJET Journal
This document presents two Register Transfer Level (RTL) models for a reconfigurable pipelined multiple constant multiplier (MCM) architecture. The first model uses a ripple carry adder, while the second model replaces it with a carry lookahead adder. Both models are constructed using Verilog and simulated using ModelSim. Simulation results show the second model has a 3.53% higher maximum clock frequency and throughput due to the faster carry lookahead adder. It also has 3.53% lower latency but uses 1.65% more power. The second model provides faster performance with moderate increases in resource usage and power consumption.
Area Efficient and high-speed fir filter implementation using divided LUT methodIJMER
Traditional method of implementing FIR filters costs considerable hardware resourses,
which goes against the decrease of circuit scale and the increase of system speed. A new design and
implementation of FIR filters using Distributed Arithmetic is provided in this paper to slove this
problem. Distributed Arithmetic structure is used to increase the resourse useage while pipeline
structure is also used to increase the system speed. In addition, the devided LUT method is also used to
decrease the required memory units. The simulation results indicate that FIR filters using Distributed
Arithmetic can work stable with high speed and can save almost 50 percent hardware resourses to
decrease the circuit scale, and can be applied to a variety of areas for its great flexibility and high
reliability
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
This document compares the complexity and cost-effectiveness of different types of filters, including IIR, FIR, polyphase, and linear phase filters. It analyzes two cases with different filter parameters and calculates the number of multiplications per input sample (MPIS) for each filter type. The results show that polyphase filters significantly reduce the MPIS compared to traditional FIR or IIR filters, making them more cost-effective for implementation. Polyphase and multistage IIR polyphase filters in particular achieve a very low number of multiplications.
Design of Multiplier Less 32 Tap FIR Filter using VHDLIJMER
This Paper provide the principles of Distributed Arithmetic, and introduce it into the FIR
filters design, and then presents a 32-Tap FIR low-pass filter using Distributed Arithmetic, which save
considerable MAC blocks to decrease the circuit scale and pipeline structure is also used to increase the
system speed. The implementation of FIR filters on FPGA based on traditional method costs considerable
hardware resources, which goes against the decrease of circuit scale and the increase of system speed.
It is very well known that the FIR filter consists of Delay elements, Multipliers and Adders. Because of
usage of Multipliers in early design gives rise to 2 demerits that are:
(i) Increase in Area and
(ii) Increase in the Delay which ultimately results in low performance (Less speed).
So the Distributed Arithmetic for FIR Filter design and Implementation is provided in this work to solve
this problem. Distributed Arithmetic structure is used to increase the recourse usage and pipeline
structure is used to increase the system speed. Distributed Arithmetic can save considerable hardware
resources through using LUT to take the place of MAC units
Implementation Cost Analysis of the Interpolator for the Wimax Technologyiosrjce
The design of the multirate filter (programmable) has been proposed which can be used in digital
transceivers that meets 802.16d/e (wimax) standard in the wireless communication system. Wimax is a
technology emerging in the wireless communication system in order to increase the broadband wireless internet
access. As there is wide spread need of the digital representation of the signal for the transmission and storage
which create the challenges in DSP [1]. In this paper, analysis of the implementation cost of interpolator for the
wimax technology, and cost of interpolator is analyzed on the basis of number of adders and multiplier. The
Filters are designed using the FDA (filters design and analysis) tool in MATLAB.
DSM Based low oversampling using SDR transmitterIJTET Journal
The oversampling recruitment is a limiting factor in high frequency application such as software defined radio. This project is a high frequency processing and low oversampling ratio. A single bit semi parallel processing is proposed in this paper. Using this single bit PDSM Architecture, high speed, high complexity computations are executed in parallel. The single bit DSM is to build an RF transmitter that includes a one bit quantifier with two level switching power amplifier for high linearity and high efficiency. Performance analysis by using the MATLAB simulations by reducing the oversampling ratio by same signal to noise ratio. The DSM implemented on field programmable gate array and using a signal code division multiple access signal. This project will give bandwidth of the low oversampled signal increased four times without increasing frequency. Finally they can be achieved signal to noise ratio is very low and also oversampling ratio is small.
This document analyzes the performance of digital audio broadcasting (DAB) systems using orthogonal frequency division multiplexing (OFDM) and Reed Solomon coding. It discusses the components of a DAB system including source coding, channel coding using Reed Solomon codes, transmission frame structure, and coded OFDM. Simulation results show the bit error rate versus signal-to-noise ratio for DAB modes I and II, demonstrating lower bit error rates at higher signal-to-noise ratios when using Reed Solomon coding compared to previous work. The document concludes the analysis and discusses limitations and potential future work.
Comparison study of 8-PPM, 8-DPIM, and 8-RDH-PIM modulator FPGA hardware desi...journalBEEI
In this paper, a performance study of 8-Pulse-Position Modulation (PPM), 8-Digital Pulse Interval Modulation (DPIM), and 8-Reverse Dual Header-Pulse Interval Modulation (RDH-PIM) implementation in Verilog hardware design language is presented. The hardware design is chosen over software design since it could provide much more flexibility in term of transmission rate and reduce the workload of the processor in the complete system. Using 50 MHz clock as the reference data clock speeds, the transmission rate recorded are 11.11 Msymbol/second or 33.33 Mbps, 9.09 Msymbol/s or 27.27 Mbps, and 6.25 Msymbol/s or 18.75 Mbps for 8-RDH-PIM, 8-DPIM, and 8-PPM respectively. We conclude that 8-RDH-PIM modulator design provides better performance in term of bandwidth utilization and transmission rate as compared to 8-PPM and 8-DPIM.
BER Performance Improvement for 4 X 4 MIMO Single Carrier FDMA System Using M...IRJET Journal
This document describes a system that aims to improve the bit error rate (BER) performance of 4x4 MIMO single-carrier frequency-division multiple access (SC-FDMA) uplink transmission. It investigates using minimum mean square error (MMSE) equalization at the receiver to better detect MIMO data over Rayleigh fading channels. Simulation results using MATLAB show that the proposed MMSE detection scheme decreases BER as signal-to-noise ratio increases for 16-QAM modulation. The BER performance is also compared to orthogonal frequency-division multiple access (OFDMA) MIMO systems, showing improved results for SC-FDMA.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to
provide signal processing in wireless communication system. There are many
applications in which sampling rate must be changed. Interpolators and decimators are
utilized to increase or decrease the sampling rate. In this paper an efficient method has
been presented to implement high speed and area efficient interpolator for wireless
communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate
operations with look up table (LUT) accesses. Interpolator has been
implemented using Partitioned distributed arithmetic look up table (DALUT)
technique. This technique has been used to take an optimal advantage of embedded
LUTs of the target FPGA. This method is useful to enhance the system performance in
terms of speed and area. The proposed interpolator has been designed using half band
poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx
Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The
proposed LUT based multiplier less approach has shown a maximum operating
frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by
consuming considerably less resources to provide cost effective solution for wireless
communication systems.
FPGA Implementation of Higher Order FIR Filter IJECEIAES
The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.
This document discusses the design and analysis of a digital down converter (DDC) for WiMAX applications using MATLAB. It contains the following key points:
1. It describes the functional blocks and design of a DDC, including a mixer, numerically controlled oscillator (NCO), and FIR filter chain.
2. It discusses WiMAX standards and requirements for DDC design in WiMAX systems.
3. It presents the windowing technique for designing FIR filters and compares different window functions to determine the best filter specifications.
Matlab Based Decimeter Design Analysis Wimax Appliacationiosrjce
The document discusses the design and analysis of a digital down converter (DDC) for WIMAX applications using MATLAB. It contains the following key points:
1. It describes the functional blocks and design of a DDC including a mixer, numerically controlled oscillator (NCO), and FIR filter chain.
2. It analyzes different window functions that can be used for FIR filter design including Kaiser, Blackman-Harris, and presents the magnitude response, phase response, and step response of filters designed using Kaiser and Blackman windows.
3. It compares the implementation cost of the filters designed using different windows by calculating the number of multipliers and adders used.
A Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithm...IOSR Journals
Abstract: In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 3-input LUT-based structure of FPGAs. The implementation of FIR filters on FPGA based on traditional arithmetic method costs considerable hardware resources, which goes against the decrease of circuit scale and the increase of system speed. This paper presents the realization of area efficient architectures using Distributed Arithmetic (DA) for implementation of Finite Impulse Response (FIR) filter. The performance of the bit-serial and bit parallel DA along with pipelining architecture with different quantized versions are analyzed for FIR filter Design. Distributed Arithmetic structure is used to increase the resource usage while pipeline structure is also used to increase the system speed. In addition, the divided LUT method is also used to decrease the required memory units. However, according to Distributed Arithmetic, we can make a Look-Up-Table (LUT) to conserve the MAC values and callout the values according to the input data if necessary. Therefore, LUT can be created to take the place of MAC units so as to save the hardware resources. The simulation results indicate that FIR filters using Distributed Arithmetic can work stable with high speed and can save almost 50 percent hardware resources to decrease the circuit scale, and can be applied to a variety of areas for its great flexibility and high reliability. This method not only reduces the LUT size, but also modifies the structure of the filter to achieve high speed performance. Keywords: DSP, Digital Filters, FIR , FPGA, MAC, Distributed Arithmetic(DA),Divided LUT, pipeline
International Journal of Engineering Research and DevelopmentIJERD Editor
This document describes a proposed VLSI architecture for an optimized low power digit serial finite impulse response (FIR) filter using multiple constant multiplications (MCM). It introduces an algorithm to optimize the area of digit serial MCM operations at the gate level by considering implementation costs of digit serial addition, subtraction, and shift operations. The proposed filter architecture aims to reduce area and power compared to designs using generic digit serial multipliers through the use of MCM blocks optimized for area. Experimental results indicate the algorithm leads to lower complexity digit serial MCM designs.
Software defined radios (SDRs) are highly motivated for wireless device modelling due to their flexibility and scalability over alternative wireless design options. The evolutionary structure of finite impulse response (FIR) filters was designed for a proposed reconfigurable canonical sign digit (CSD) approach. Considering the complex trade-off, this is accomplished with many FIR taps, which is a challenging assignment. On the baseband processing side, design is given with parameterization-controlled FIR filter tap selection. Optimal processing models to overcome the reconfigurable design issues associated with the SDR system for a multi-standard wireless communication system root cosine filter standard are often used to implement multiple FIR channelization topologies, each of which is tied to a particular in-phase and quadrature (IQ) symbol. Additionally, it demonstrates the viability of using a multi-modulation baseband modulator in the SDR system for next-generation wireless communication systems to maximise adaptability with the least amount of computational complexity overhead. The proposed multiplier-less FIR filter-based reconfigurable baseband modulator, according to the experimental results, offers a 6% complexity reduction and a 47% improvement in performance efficiency over the current SDR system
Modified Distributive Arithmetic Based DWT-IDWT Processor Design and FPGA Imp...IOSR Journals
1) The document describes a modified distributive arithmetic based discrete wavelet transform (DWT) processor architecture and its FPGA implementation for image compression.
2) The proposed architecture uses four lookup tables to store pre-computed partial products of filter coefficients, achieving a latency of 44 clock cycles and throughput of 4 clock cycles.
3) A software reference model is developed in Matlab to analyze the performance of various wavelets for image compression using the distributive arithmetic based DWT approach. The input image is resized and decomposed into sub-bands using DWT and reconstructed using IDWT.
FOLDED ARCHITECTURE FOR NON CANONICAL LEAST MEAN SQUARE ADAPTIVE DIGITAL FILT...VLSICS Design
Power consumption reduction is transpiring drift in area of VLSI digital signal processing. This gives rise
to need of minimization of silicon area which is done by folding algorithm. As silicon area decreases power
consumption of a circuit decreases. Folding is an algorithm which reduces silicon chip area by combining
various arithmetic operations into one operation by time scheduling technique. It is applied on iterative
data flow graph with appropriate folding set. Least mean square algorithm alters coefficients of Adaptive
filter in order to achieve desired output. Proposed work is focused on design of efficient VLSI architecture
for LMS adaptive filter aims at reducing mainly area which results in power consumption reduction and
hardware complexity. LMS filter structure used here is called non-canonical as transpose FIR structure is
used. Results show that numbers of adders are reduced by 37.5 % and multipliers by 33.33% without
changing characteristics of filter.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
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yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION...VLSICS Design
The document describes the design and implementation of an efficient digital down converter (DDC) for software defined radios. The proposed DDC uses optimal equiripple techniques to reduce resource requirements. It employs a computationally efficient polyphase decomposition structure to improve hardware complexity. The DDC is implemented using embedded multipliers, lookup tables, and block RAMs of a Virtex-II Pro FPGA. Simulation results show the DDC can operate at 160 MHz while consuming 0.34004W. Implementation requires few FPGA resources, providing a low-cost solution for software defined radio applications.
Efficient Hardware Co-Simulation of Down Convertor for Wireless Communication...VLSICS Design
In this paper an optimized hardware co-simulation approach is presented to design & implement GSM based digital down convertor for Software Defined Radios. The proposed DDC is implemented using optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase decomposition structure is used to improve the hardware complexity of the overall design. The proposed model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the system performance in terms of speed and area. The DDC model is designed and simulated with Simulink and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed design is consuming very less resources available on target device to provide cost effective solution for SDR based wireless applications.
CANONIC SIGNED DIGIT BASED DESIGN OF MULTIPLIER-LESS FIR FILTER USING SELFORG...ijaia
This document summarizes a research paper that proposes a design for multiplier-less finite impulse response (FIR) filters using the Self-organizing Random Immigrants Genetic Algorithm (SORIGA). FIR filter coefficients can be represented in binary or Canonic Signed Digit (CSD) number systems to reduce hardware costs by eliminating multipliers. The paper describes these number system representations and the SORIGA technique is used to optimize the coefficients to minimize hardware costs while maintaining filter performance. Simulation results are presented and hardware costs of the designed filter are analyzed and compared to other existing designs.
Design of Scalable FFT architecture for Advanced Wireless Communication Stand...IOSRJECE
Now a day’s numerous wireless communication standards have raised additional stringent requirements on each throughput and flexibility for FFT computation. Advanced wireless systems support multiple standards to satisfy the demands of user application necessities. A wireless system whereas supporting multiple standards should also satisfy performance necessities of these supported standards. Meeting performance requirements of multiple standards is a challenge while designing a system. Fast Fourier transformations, a kernel processing task in communication systems, are studied intensively for efficient software and hardware implementations. To design an efficient system, it's necessary to efficiently design its performance critical component. each system must meet stringent design parameters like high speed, low power, low area, low cost, high flexibility and high scalability, designing FFT processor to support multiple wireless standards whereas meeting the above such performance necessities is a difficult task. This paper proposed a highly efficient scalable architecture, software tools design, and design implementation. The reconstruction of the FFT computation flow is design into a scalable structure. The FFT can be easily expanded for any-point FFT computation. The various parameters satisfied the conditions, gives proper and efficient outputs as compare to other platforms.
IRJET- Review on Dynamic Reconfiguration of Filters for Signal ProcessingIRJET Journal
This document summarizes a research paper on dynamic reconfiguration of filters for signal processing. It discusses implementing a dynamically reconfigurable image processing system on an FPGA that can reconfigure in real-time without stalling overall operation. It proposes optimizing LUT-based architectures by directly mapping them to FPGA CLB primitives. Dynamic partial reconfiguration is used to reconfigure the LUT values at run-time. The combination of optimized implementations with CLB primitives and dynamic partial reconfiguration results in multi-functional, area-efficient, and high-performance systems. It also discusses implementing a partially reconfigurable FIR filter design targeting low power consumption, autonomous adaptability, and reconfigurability on FPGAs
AN EFFICIENT DSP ARCHITECTURE DESIGN IN FPGA USING LOOP BACK ALGORITHMIJARIDEA Journal
Abstract— Advanced flag processors assume a noteworthy part in electronic gadgets, bio restorative applications, correspondence conventions. Effective IC configuration is a key variable to accomplish low power and high throughput IP center improvement for convenient gadgets. Computerized flag processors assume a huge parts progressively figuring and preparing yet region overhead and power utilization are real disadvantages to accomplish productive outline requirements. Adaptable DSP engineering utilizing circle back calculation is a proposed way to deal with beat existing outline limitations. For instance, plan of 8 point FFT engineering requires 3 phases for butterfly calculation unit that 48 adders and 12 multipliers prompts high power and territory utilization. To lessen range and power, Loop back calculation is proposed and it requires 16 adders and 4 multipliers for general outline. Likewise outline of various DSP layouts like FFT, First request FIR channel and Second request FIR channel is acquainted and mapping in with the design as preparing component and applying the circle back calculation. In the outline of FFT,FIR formats adders, for example, parallel prefix viper, move and include multiplier, baugh-wooley multiplier are utilized to break down effective plan of DSP engineering. Recreation and examination of inactivity, territory, control productivity with the current structures are happens utilizing model sim 6.4a and combine utilizing Xilinx 14.3 ISE.
Keywords— Baugh-UWooley Multiplier, Loop Back Algorithm, Parallel Prefix Adders.
IRJET- Efficient Shift add Implementation of Fir Filter using Variable Pa...IRJET Journal
This document discusses efficient implementations of shift-add operations in finite impulse response (FIR) filters using variable partition hybrid form structures. FIR filters are widely used in digital signal processing and their performance is dominated by multiplication operations. The proposed method aims to reduce power consumption and complexity by implementing multiplications using optimized shift-add networks instead of multipliers. It explores variable size partitioning approaches and prefix adders to reduce gate count, dynamic power, and improve filter performance.
1. The document presents a design for a modified Booth recoder using a fused add-multiply (FAM) operator to implement digital signal processing applications more efficiently.
2. It proposes a new recoding technique to decrease the critical path delay and reduce area and power consumption of the FAM unit compared to existing recoding schemes.
3. The technique is also applied to the implementation of finite impulse response (FIR) filters to further optimize hardware usage and achieve faithfully rounded outputs within tight area and power constraints for mobile applications.
International Journal of Engineering Inventions (IJEI) provides a multidisciplinary passage for researchers, managers, professionals, practitioners and students around the globe to publish high quality, peer-reviewed articles on all theoretical and empirical aspects of Engineering and Science.
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Medical image analysis has witnessed significant advancements with deep learning techniques. In the domain of brain tumor segmentation, the ability to
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Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Neural network optimizer of proportional-integral-differential controller par...IJECEIAES
Wide application of proportional-integral-differential (PID)-regulator in industry requires constant improvement of methods of its parameters adjustment. The paper deals with the issues of optimization of PID-regulator parameters with the use of neural network technology methods. A methodology for choosing the architecture (structure) of neural network optimizer is proposed, which consists in determining the number of layers, the number of neurons in each layer, as well as the form and type of activation function. Algorithms of neural network training based on the application of the method of minimizing the mismatch between the regulated value and the target value are developed. The method of back propagation of gradients is proposed to select the optimal training rate of neurons of the neural network. The neural network optimizer, which is a superstructure of the linear PID controller, allows increasing the regulation accuracy from 0.23 to 0.09, thus reducing the power consumption from 65% to 53%. The results of the conducted experiments allow us to conclude that the created neural superstructure may well become a prototype of an automatic voltage regulator (AVR)-type industrial controller for tuning the parameters of the PID controller.
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A review on features and methods of potential fishing zoneIJECEIAES
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Bibliometric analysis highlighting the role of women in addressing climate ch...IJECEIAES
Fossil fuel consumption increased quickly, contributing to climate change
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A bibliometric analysis of data from the last ten years has been carried out to
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findings discussed the relevant to the sustainable development goals (SDGs),
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inclusivity in climate change decision-making processes.
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Smart grids are one of the last decades' innovations in electrical energy.
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datasets have been analyzed using a bibliometric tool called bibliometrix.
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research.
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Design and implementation of DA FIR filter for bio-inspired computing architecture
1. International Journal of Electrical and Computer Engineering (IJECE)
Vol. 11, No. 2, April 2021, pp. 1709~1718
ISSN: 2088-8708, DOI: 10.11591/ijece.v11i2.pp1709-1718 1709
Journal homepage: http://ijece.iaescore.com
Design and implementation of DA FIR filter for bio-inspired
computing architecture
B. U. V. Prashanth1
, Mohammed Riyaz Ahmed2
, Manjunath R. Kounte3
1,3
School of Electronics and Communication Engineering, REVA University, India
2
School of Multidisciplinary Studies, REVA Universiy, India
Article Info ABSTRACT
Article history:
Received Apr 23, 2020
Revised Jul 27, 2020
Accepted Sep 16, 2020
This paper elucidates the system construct of DA-FIR filter optimized for
design of distributed arithmetic (DA) finite impulse response (FIR) filter and
is based on architecture with tightly coupled co-processor based data
processing units. With a series of look-up-table (LUT) accesses in order to
emulate multiply and accumulate operations the constructed DA based FIR
filter is implemented on FPGA. The very high speed integrated circuit
hardware description language (VHDL) is used implement the proposed filter
and the design is verified using simulation. This paper discusses two
optimization algorithms and resulting optimizations are incorporated into
LUT layer and architecture extractions. The proposed method offers an
optimized design in the form of offers average miminimizations of the
number of LUT, reduction in populated slices and gate minimization for DA-
finite impulse response filter. This research paves a direction towards
development of bio inspired computing architectures developed without
logically intensive operations, obtaining the desired specifications with
respect to performance, timing, and reliability.
Keywords:
Bio-inspired computing
Distributed arithmetic
Finite impulse response
MAC and parallel filters
Processor architecture
Systolic array
This is an open access article under the CC BY-SA license.
Corresponding Author:
B. U. V. Prashanth
School of Electronics and Communication Engineering
REVA University
Rukmini Knowledge Park, Yelahanka, Bengaluru-560064, India
Email: prashanthbuv@reva.edu.in
1. INTRODUCTION
High throughput is required since the finite impulse response filters are used intensively in video,
communications systems as well as bio-inspired computing systems. Essentially, digital filters are used in
time and frequency domain to adjust the characteristics of the signals and are identified as the primary digital
signal processing feature [1]. The DSP design techniques focus mainly on multiplier-based architectures for
multiply-and-accumulate (MAC) blocks implementation which represent the FIR filters and several
functions. High speed parallel filter designs are elucidated in excruciating detail. Finite impulse response
(FIR) filters are prominent building blocks for several applications in the field of digital signal processing
(DSP). High-speed FIR filters have been widely used to perform signal equalization on the received data in
real time due to the increasing demand for video-signal processing and transmission. Therefore a structured
VLSI architecture is needed for a programmable fast FIR filter [2].
The various FIR Filters were suggested in last few decades, many structures and different algorithms
have been utilized for the enhamcement of the filter weights. The very common structures utilized were least
mean square (LMS) derived models since their response in convergence is strong. Block processing with
distributed arithmetic methods is explored to derive a design that should give high throughput [3]. The
2. ISSN: 2088-8708
Int J Elec & Comp Eng, Vol. 11, No. 2, April 2021 : 1709 - 1718
1710
parallelism assists in minimizing the number of clock cycles desired for partial product calculation. This
increases the proposed processing speed as compared with current systems.
Distributed arithmetic (DA) is a strategy of high-speed multiplication which is a bit serial word
parallel technique where the throughput rate does not depend on the data size. The DA facilitates to avoid the
multipliers in the design and makes the area of the system efficient in the throughput and several DA based
structures were designed in order to minimize the area and to reduce the cost of processing [4]. The primary
operations necessary for DA-based processing are a series of accesses to a lookup table (LUT), preceded by
the LUT output's shift-accumulation operations. The standard framework of DA used to implement the FIR
filter implies that the coefficients of the impulse response are fixed and this action allows use of ROM based
LUTs. However, with linear filter order the memory requirement for Distributed Arithmetic implementation
of FIR filters rises exponentially is one of the hard problems to be addressed [5]. The key contributions of
this research are:
- Develop systolic array architecture with tightly coupled co-processor based data processing units.
- Develop optimization algorithms with optimizations incorporated into LUT layer with architecture
extractions and propose bio inspired computing architecture to compute FIR filters at high processing
speeds using reconfigurable computing based on DA strategy.
2. RELATED WORK
Modular finite-impulse response (FIR) filter whose filter coefficients switch dynamically during
latency, which plays a major role in architectures for software-defined radio (SDR), multi-channel filters, bi-
inspired computing and digital up/down converters. However, when the filter coefficients vary dynamically,
the well-known multiple constant multiplication (MCM)-based methods that are widely used to realize the
FIR filters cannot be used. Addressing to the solution to the problem of such large memory requirement,
systolic decomposition techniques are utilized for DA-based implementation of long-length convolutions and
FIR filter of large orders. It is necessary to use rewritable RAM based LUT instead of ROM based LUT for
reconfigurable DA based FIR filter whose filter coefficients alter dynamically. Another method is to store the
analog domain coefficients using serial digital to analog converters, resulting in mixed-signal architectures
[6].
A pipelined design for an adaptive FIR filter carry out the save accumulation technique which is
used for partial inner product calculation that facilitates in enhancing the throughput with block processing is
utilized in increasing the computational speed of the system. On the other hand, a particular multiplier-based
structure requires a wide chip region, and thereby controls limitations on the highest allowable order of the
filter that can be interpreted for high-throughput applications [7]. In recent years, distributed arithmetic (DA)-
based technique has gained substantial popularity due to its high capacity for processing throughput and
increased regularity, resulting in cost-effective and area-time efficient computing structures.
The primary operations required for DA-based processing are a sequence of accesses to a lookup
table (LUT), followed by the LUT output's shift-accumulation operations [8]. The conventional
implementation of the DA used to implement the FIR filter assumes that the coefficients of the impulse
response are fixed and this behavior allows the use of ROM based LUTs. However, with the filter order the
memory requirement for DA-based implementation of FIR filters increases exponentially [9].
The systolic decomposition techniques are used to get rid of the problem of such a large memory
requirement. For long-length convolutions and large-order FIR filter for DA-based implementation, we must
use rewritable RAM based LUT instead of ROM based LUT for reconfigurable DA-based FIR filter whose
filter coefficients change dynamically. Another approach is to store the coefficients in the analog domain by
using serial digital to analog converters resulting in mixed-signal architecture. We also find quite a few
works on DA based implementation of adaptive filters, where the coefficients change at every cycle [10].
3. PROPOSED METHOD AND ALGORITHM DESIGN
Distributed arithmetic is a popular architecture without the use of multipliers to implement FIR
filters. DA makes efficient use of LUTs, shifters, and adders to calculate the sum of products required for
FIR filters. Since these operations effectively map onto an FPGA, Distributed arithmetic on these devices is a
favourable architecture [11].
The Figure 1 illustrates the experimental design of the research work presented in this manuscript.
Distributed Arithmetic is a prominent architecture without the use of multipliers to implement FIR filters. DA
makes efficient use of LUTs, shifters, and adders to calculate the sum of multiplication factors needed for
FIR filters. Though distributed arithmetic implements the FIR filter by serialization bits of inputs, a filter
quantisation is required. Due to the fixed data path requirements in input analog to digital converter (ADC)
3. Int J Elec & Comp Eng ISSN: 2088-8708
Design and implementation of DA FIR filter for bio-inspired computing architecture (B. U. V. Prashanth)
1711
and the output digital to analog converter (DAC) widths the length of the word with 12 bit input and output
with 11 fractional bits are assumed to be required to quantize the FIR filter [12].
Figure 1. Block diagram of experimental design
After the quantization process the HDL Code is generated with DA architecture. The HDL code
generator uses distributed arithmetic architecture, and partitions the look-up-table (LUT) into a specified
number of LUT partitions with the range of taps each partition associates. It is best to divide the taps into a
number of LUTs for a filter with many taps, with each LUT storing the sum of coefficients only for the taps
that are associated with it.
The FIR filter structure has symmetric coefficients, and we consider converting the structure to
reduce the area. Here we convert the filter structure to direct form symmetric and generate the HDL code for
default radix of 2. In hardware, a symmetrical filter structure offers advantages, as it halves the number of
coefficients to work with which substantially reduces the complexity of the hardware. The predefined
architecture is an implementation of Radix 2 that runs on one bit of input data per clock period. Before an
output is obtained, the number of clock phases elapsed is equal to the number of bits in the input data and DA
may effectively limit the throughput. DA can be configured to process multiple bits in parallel, to improve
the DA throughput. The processing of 12 bits at a time for a 12 bit input word length can be specified with
the corresponding DA-Radix values of 212
. The speed vs. area is trade off by selecting different 'DARadix'
values and the amount of parallel bits illustrates the factor with the increased rate of the clock which is the
number of cycles to perform an iteration [13]. The Tables 1-3 elucidate the information of DA architecture.
The Table 1 depicts the 'DARadix' values with corresponding values of number of cycles to perform an
iterationand multiple for LUT sets for the given filter. Further Table 2 illustrates the details of LUTs with
corresponding 'DALUTPartition' values. Details of LUT indicate number of LUTs with the sizes of LUT for
example (1x1024x18) implies 1 LUT of 1024 18-bit wide locations [14].
Table 1. 'DARadix' values with number of cycles to perform an iterationand multiple for LUT sets
Folding Factor LUT Sets Multiple DA Radix
1 12 212
2 6 26
3 4 24
4 3 23
6 2 22
12 1 21
4. ISSN: 2088-8708
Int J Elec & Comp Eng, Vol. 11, No. 2, April 2021 : 1709 - 1718
1712
Table 2. Details of LUTs with corresponding partitions of DA-LUT
Address
Width
Size (bits) LUT DA LUT Partition
W12 b’259072 [1024x13], [13x4096], [14x4096], [15x4096], [18x4096] (12) (12) (12) (12) (10)
W11 b’147544 [2x2048x14], [1x2048x18], [2x2048x13], [1x8x11] (11) (11) (11) (11) (11) (3)
W10 b’78080 [1x1024x18], [3x1024x13], [1x1024x16], [1x256x13] (10) (10) (10) (10) (10) (8)
W09 b’43712 [1x512x12], [1x512x14], [1x512x18], [1x16x12], [2x512x13],
[1x512x15]
(9) (9) (9) (9) (9) (9) (4)
W08 b’25384 [1x4x10], [1x256x14], [1x256x18], [4x256x13], [1x256x15] (8) ( 8) (8) (8) (8) (8) (8)( 2)
W07 b’14248 [1x128x14], [1x128x16], [1x4x10], [2x128x12], [3x128x13],
[1x128x18]
(7) (7 )(7) (7) (7) (7) (7) (2)
W06 b’8000 [4x64x12], [1x16x12], [1x64x17], [2x64x14], [1x64x16], [1x64x13] one(9,1)*(6), (4)
W05 b’4696 [1x8x11], [4x32x12], [3x32x13], [1x32x15], [1x32x14], [1x32x17],
[1x32x11]
one(1,11)*(5), (3)
W04 b’2904 [1x16x15], [5x16x12], [2x16x13], [2x16x14], [1x16x17], [1x4x10],
[3x16x11]
one(1,14)*(4),(2)
W03 b’1926 [8x8x12], [2x8x14], [2x8x15], [1x8x17], [1x2x7], [5x8x11],
[1x8x13]
one(1,19)*(3), 1
W02 b’1412 [12x4x11], [2x4x13], [2x4x15], [1x4x17], [2x4x10], [6x4x12],
[4x4x14]
one(1,29)*(2)
Table 3. Tabular column of complete twiddle factor for each LUT inputs
Folding Factor LUT Inputs LUT Size LUT Details
1 LUT4 S(34848) (1x4x10, 5x16x12, 2x16x14, 2x16x13, 1x16x15, 1x16x17, 3x16x11)x12
2 LUT4 S(17424) (3x16x17, 5x16x12, 2x16x14, 2x16x13, 1x16x15, 1x16x11, 1x4x10)x6
3 LUT4 S(11616) (1x4x10, 5x16x12, 2x16x14, 2x16x13, 1x16x17, 1x16x15, 3x16x11)x4
4 LUT4 S(8712) (1x4x10, 5x16x12, 2x16x14, 2x16x13, 1x16x17, 1x16x15,3x6x11)x3
6 LUT4 S(5808) (1x4x10, 5x16x12, 2x16x14, 2x16x13, 1x16x17, 1x16x15,3x6x11)x2
12 LUT4 S(2904) (1x4x10, 5x16x12, 2x16x14, 2x16x13, 1x16x17, 1x16x15,3x6x11)x1
As depicted in Table 3, if it is required to increase the clock rate by four scales the sampling
frequency and utilize six input LUTs then we can verify that the details of LUT meets the area requirements.
Next a test bench is designed with a standard setup, and uses a simulator to verify the generated code for
distributed arithmetic architecture [15]. The synthesis tool is utilized to compare the area and speed of the
DA architecture. The Algorithm 1 illustrates the performance analysis and optimation of LUT layer. As
shown in Algorithm 2, the cost function could be any arbitrary parameters delay, power or power delay
multiplication (PDM) returned from optimized LUT.
Algorithm 1: Performance analysis and optimization of LUT layer
Result: Optimization of LUT Layer
Start
Optimize LUT (Addr bits: k, num LUTs: m)
Delay(LUTi,1) ← dlut[j] ; for all j set of [k]
Power(LUTi,1)← plut[j] for all j set of [k]
Power Delay(LUTj,1)← pdlut[j]; for all j set of [k]
While {Read the Input Parameters}{
for (i=2; i <= k; i++)
for (j=2; j <= m; j++)
else If{Perform Optimization}
{
Delay(LUTi,j)←minu{max{ dlut[u] +D(LUTi-u,j-1)}
};
P(LUTi,j)←minima w{plut[w] + Power(LUTi-w,j-1)};
PD(LUTi,j)←minima{Delay(LUTi,j.Power Utilization (LUTi,j)};
end for
}{Compute:return Delay(LUTk,m), Power(LUTk,m) Power Delay(LUTk,m)}
Calculate the performance;
}
Stop
Algorithm 2: Algorithm steps to optimized architecture extractions
Result: Optimized Architecture Extractions
Start;
Define parameters;
While {Read the Input Parameters}
{
Architecture Optimize (N:Filter Order):
5. Int J Elec & Comp Eng ISSN: 2088-8708
Design and implementation of DA FIR filter for bio-inspired computing architecture (B. U. V. Prashanth)
1713
Optimized Solution← infinity;
Select cost from (Delay | Power | Power Delay Muliplication)
for (i=1; i <= N; i++)
for (j=1; j <=i; j++)
else If{Perform Optimization}
{
ArchCost = cost(OptimizeLUT(i,j))
if (Architecture Cost )
Optmized response←Architecture Cost;
end for
end for
}
Compute:
return:
Optimum Solution
Calculate the performance;
Stop
}
4. RESULTS AND DISCUSSIONS
The fixed point settings are applied in order to obtain the characteristic plot of magnitude response
(dB) indicating the curves between the magnitude (dB) and the normalized frequency (π radians per sample)
with the comparison between reference and quantized filter as depicted in Figure 2(a). The characteristic plot
representing the complete design specification of DA FIR filter along with the Log magnitude (dB) and phase
(degrees) is as depicted in Figure 2(b). In this case the full precision override is not considered and custom
coefficient data type is considered in the design. With the optimizations addressed by variations in
architectural level enhancements using DA concept of digital filtering which improves device utilization
[16, 17].
(a) (b)
Figure 2. Plot of (a) magnitude response (dB), (b) log magnitude (dB)-phase (degrees)
Here the clock rate is four times the input sample rate for this architecture and the effective filter
length for serial partition value is 58 along with three samples of HDL latency, achieved with the FIR
compiler and the corresponding frequency response diagram obtained in FIR compiler is as depicted in
Figure 3(a) and with reference to this the pole-zero (P-Z) diagram is as depicted in Figure 3(b). Because of
mid-stage pipelining, the entire architecture is split into two sections, namely the input section and the output
section. Here the power consumption of the DA architecture is estimated at 20 MHz frequency and the final
DA architecture is designed using the systolic rearrangement of delay elements. The preconfigured logic
functions, that is the intellectual property (IP) cores optimized for FPGAs is generated using FIR compiler
and Figure 4 illustrates the block design to verify the DA FIR filter responses as obtained in the Figure 2 and
Figure 3.
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(a) (b)
Figure 3. Plot of (a) frequency response (dB), (b) pole-zero (P-Z) diagram
Figure 4. A system construct of DA-FIR filter optimized for ZYNQ FPGA
As depicted in Figure 4 the RAM based shift register is having 16 bit width and 16 bit depth is
configured as a circular buffer and it is initialized with memory initialization radix and memory initialization
vector of 16-bits as arbitary waveform generator and on every cycle of 100 MHz clock, the shift RAM
outputs the last sample first and proceeds towards the initial sequence and loops back. Further the complete
DA FIR filter is processed using the ZYNQ FPGA as a special purpose tightly coupled processor. The
Figure 5 illustrates the performance evaluation of the design with behavioral simulation of DA FIR Filter
obtained in Xilinx ISE environment with phase (phase 0, 3) and serial (serial out 1, 2, 3) and the Figure 6
depicts the performance evaluation with analysis of filter coefficient values.
The Figure 7 compares the proposed DA FIR filter design with the previous designs available in
[18-21] in terms of number of multipliers versus the filter order as depicted in Figure 7(a). In Figure 7(b) the
number of adders versus order of Filter is illustrated along with the LUT optimization with number of LUTs
versus order of filter in Figure 7(c), the Figure 7(d) represents the number of registers versus the filter order.
The estimated delay based on (Gate delay-DG) for Distributed Arithmetic unit of LUT, LUT-less and
7. Int J Elec & Comp Eng ISSN: 2088-8708
Design and implementation of DA FIR filter for bio-inspired computing architecture (B. U. V. Prashanth)
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proposed architecture implementation [22, 23] is as shown in the Figure 8. Here the delay of the proposed
architecture is 14 % (for 8-order filter) and 64.7% (for 140-order filter) less delay in comparison of LUT-less
architecture [24, 25].
Figure 5. Performance evaluation with simulation of DA-FIR Filter with phase, and serial outputs
Figure 6. Performance evaluation with simulation of DA-FIR Filter with filter coefficients
Figure 7. Comparisons of previous research with proposed research with filter order versus (a) Number of
multipliers, (b) Number of adders, (c) Number of LUT’s, (d) Number of registers
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Figure 8. Estimated gate delay of FIR Filters for DA based architectures
The Table 4 illustrates the comparison of the obtained synthesis results of the proposed research
work with the previously published literature. Here the factor B is denoted as bit width of the filter
coefficients. Further extending this concept in the following mathematical formulae compares the hardware
and time complexities of our proposed DA-FIR structures with other filter structures.
Here if: B: = bit width of filter coefficients,
M: = image width,
TM: = delay of multiplier,
TPA: =delay of parallel adder)
Then: T1 =TPA + 2.TFA (log2 N −1),
TDAHLUT =2TPA,
TPU = TMUX + TSAB,
TSAB = TFA + TXOR + TD
Table 4. Synthesis results comparison of proposed structure with past works
Design
Minimum Sampling
Period(ns)
Area(μm2
)
Power
(mw)
Area Delay Product
(μm2
ns)
Energy per
output
Throughput
(MHz)
[26]
B = 8, 11.79
B = 16, 13.3
1,720,962.1471
12,661,783.52
50.0106
181.165
2,537,558
10,550,431
312.56
566.14
678.19
1200
[27]
B = 8, 13.01
B = 16, 14.65
356,293.0216
1,154,123.0880
9.3807
26.9941
4,636,084
16,907,903
1319.07
312.56
76.80
68.25
[28]
B = 3, 2.11
B = 7, 2.34
B= 15, 2.41
98,266.83
412,267.34
1,734,743.62
2.47
8.91
36.48
207,343.01
964,704.78
4,180,732.12
1235
4555
18,240
-
This Work
B = 8, 6.73
B = 16, 6.92
651,615.4709
4,936,081.6759
20.1069
102.3432
531,880
2,131,770
175.66
319.82
1325.11
2325.48
The TMUX, TFA, TXOR and TD are the delay of MUX, full adder, XOR gate and D flip-flop,
respectively. This comparison of time complexities and hardware of proposed DA-FIR designs with other
filter designs is as depicted in Table 5. The Table 4 illustrates our best solution and compares the obtained
parameters of our synthesis results with previous works in terms of numerical values of (MSP)-Minimum
Sampling Period(ns), Area(μm2
), Power(mw) ,(ADP)-Area Delay Product(μm2
ns), Energy per output,
Throughput(MHz) [29, 30]. Further the Table 5 compares the obtained results in our work with previous
works with numerically addressing with mathematical formulas of various parameters such as Throughput,
multipliers, adders and registers [31, 32]. The implementation of multi-core computing system is done on the
ZYNQ platform with the use of VERILOG language to program and compile the framework [33].
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Design and implementation of DA FIR filter for bio-inspired computing architecture (B. U. V. Prashanth)
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Table 5. Time complexities and hardware of proposed DA-FIR designs with other designs
Design Throughput Multipliers Adders Registers
[34] L/(TM + T1) M 2
M 2
−1 (M +N)(M −1)
[35] 1/(TM +2TPA) MN 2
L([NxN] −1) (M +N)(M −1)
This Work N/(3TPA + 2.B.TPU) - N(7(L + N) − 26) +L((3M 2
/5) − 1) N(M −1)+N.Lc
5. CONCLUSIONS
The VHDL is used implement the proposed DA finite implse response filter and the design is
verified using simulation. The calculated theoretical values of the design match with obtained practical
values in the real time simulation environment. Two optimization algorithms are proposed and the resulting
optimizations are incorporated into LUT layer and architecture extractions of designed block. The proposed
work offers an optimized design in the form of average reductions of number of LUT, reduction in populated
slices and reduction in the number of gates for DA-finite impulse response filter implementation. This
research paves a way for bio inspired computing architecture with reconfigurable computing strategies
designed to avoid computationally intensive operations, achieving the desired specifications with respect to
flexibility, timing, and performance.
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