Toward Automatic Generation of Models with Probes from the SDL System Specification
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This document summarizes the automatic generation of Promela models with probes from SDL system specifications. It describes inserting probes into generated models to detect invalid states, semantic rule violations, and potentially erroneous executions. A case study on formally verifying the V.76 telecommunications protocol specification is presented, where probes revealed implicit signaling, ignored commands, and violations of temporal properties. The approach supports modeling SDL concepts like processes, data types, communication, and verification with the Spin model checker.
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![Toward Automatic Generation of Models with Probes from the SDL System Specification University of Maribor Faculty of Electrical Engineering and Computer Science Boštjan Vlaovič , Ph. D. [email_address] Workshop on Formal Verification of Telecommunication Systems , Part I Zagreb, 5. 11. 2004 UM FERI](https://image.slidesharecdn.com/feri-fer2004-sdl2pmlv2-110511074728-phpapp02/85/Toward-Automatic-Generation-of-Models-with-Probes-from-the-SDL-System-Specification-1-320.jpg)
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This document contains a summary of qualifications and experience for Mallikarjun S Bankapur. It includes details of his education such as an M.Tech in Signal Processing and VLSI from Jain University and a B.E. in Electronics and Communication. It lists his skills in HDLs like Verilog and SystemVerilog, verification methodologies, protocols, and EDA tools. It provides details of his internship projects including designing an RTL router and verifying IP cores for SPI, UART, and GPIO. It also lists his post-graduation projects on SAR data compression and noise elimination in EMG signals.
Soc.pptx
This document discusses hardware design verification and testing techniques. It covers emulation architectures like FPGA-based and processor-based systems. It also discusses formal property verification methods, software formal verification, design for test objectives, chip-level DFT techniques, automatic test pattern generation, and testing techniques for analog/mixed-signal circuits like ADCs, PLLs and oscillators.
Co emulation of scan-chain based designs
As the complexity of the scan algorithm is dependent on the number of design registers, large SoC scan
designs can no longer be verified in RTL simulation unless partitioned into smaller sub-blocks. This paper
proposes a methodology to decrease scan-chain verification time utilizing SCE-MI, a widely used
communication protocol for emulation, and an FPGA-based emulation platform. A high-level (SystemC)
testbench and FPGA synthesizable hardware transactor models are developed for the scan-chain ISCAS89
S400 benchmark circuit for high-speed communication between the host CPU workstation and the FPGA
emulator. The emulation results are compared to other verification methodologies (RTL Simulation,
Simulation Acceleration, and Transaction-based emulation), and found to be 82% faster than regular RTL
simulation. In addition, the emulation runs in the MHz speed range, allowing the incorporation of software
applications, drivers, and operating systems, as opposed to the Hz range in RTL simulation or submegahertz
range as accomplished in transaction-based emulation. In addition, the integration of scan
testing and acceleration/emulation platforms allows more complex DFT methods to be developed and
tested on a large scale system, decreasing the time to market for products.
UVM_TB_20220621_slides-1.pdf
Here are the answers to the matching questions from the previous section:
1. A class cannot have any: I/O ports.
Classes can define interfaces and virtual interfaces, but cannot have physical I/O ports like modules can.
2. An interface bus must be: instantiated, to be useful.
An interface bus is just a declaration of related signals until it is instantiated as an object that can be connected to other objects.
3. Access uvm_config_db using: static methods set, get().
The uvm_config_db is accessed through static methods like set() and get() rather than through objects.
4. Calling method run_test(): will launch the test
An Effective Design and Verification Methodology for Digital PLL
An Effective Design and Verification Methodology for Digital PLLQuEST Global (erstwhile NeST Software)
Complex digital and analog circuits and multiple clock signals used for design and development of modern systems usually make the job of engineers and designers a tedious one. While working with complex circuits and signals, a designer might encounter problems with circuit validation due to long simulation time. These complexities adversely affect the development time and hence increase time to market incurring higher production costs. By applying a new methodology in their Digital Phase-Locked Loop (Digital PLL) design, the engineers at QuEST reduced the simulation effort to one-by-third.Fpga applications using hdl
The document describes two FPGA projects using HDL:
1. Salt and pepper noise removal from images using a median filter optimized for FPGA hardware. The filter reduces comparison times by 40% over traditional algorithms.
2. Generation of pulse-width modulation (PWM) signals using a counter and comparator on an FPGA. A 25% duty cycle PWM signal is successfully generated to control devices.
The document provides details on the hardware design, VHDL code modules, and testing of both projects. Real-time filtering of 1Kx1K images and MATLAB simulation of PWM generation are demonstrated. Guidelines for efficient HDL coding suited for FPGA implementation are also listed.
Advancing VLSI Design Reliability: A Comprehensive Examination of Embedded De...
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1) EDT insertion enhances test and fault coverage, but also increases the number of test patterns required.
2) There are significant shifts in fault sub-classes like untestable faults and tied cells after EDT insertion, highlighting its nuanced effects.
3) Results provide empirical evidence for designers to optimize testability by strategically integrating EDT logic.
Fault Modeling of Combinational and Sequential Circuits at Register Transfer ...
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.
FAULT MODELING OF COMBINATIONAL AND SEQUENTIAL CIRCUITS AT REGISTER TRANSFER ...
This document summarizes research on modeling faults at the register transfer level (RTL) for digital circuit testing. It proposes a new RTL fault model that models stuck-at faults by inserting buffers for each bit in the variables of the RTL code. Fault simulation is performed on faulty circuits generated from the RTL code to determine fault coverage. Results on combinational and sequential circuits show the RTL fault coverage obtained matches closely with gate-level fault coverage obtained through logic synthesis and gate-level fault simulation. The proposed RTL fault model provides a way to estimate fault coverage earlier in the design cycle compared to traditional gate-level fault simulation.
Resume for Embedded Engineer_1
Gajendrakumar Parmar is seeking a technical engineering position. He has a B.E. in Electronics and Communication from Sankalchand Patel College of Engineering, Visnagar, Gujarat, India and a M.E. in Electronics and Communication from Dharmsinh Desai University, Nadiad, Gujarat, India. He has over 8 years of experience in electronics, embedded systems, teaching, and as an embedded engineer. His areas of interest include embedded systems, communication, and electronics and he has strong analytical, time management, and group/individual work skills.
Ramesh resume
This document is a resume for Ramesh Kumar Bankapalli summarizing his objective, qualifications, skills and projects. He has a PG Diploma in ASIC Design from RV-VLSI Design Center and an M.Tech in VLSI. He has experience with synthesis tools like PrimeTime and design tools like IC Compiler. His projects include block level physical design of a torpedo subsystem and static timing analysis using 180nm technology.
Podem_Report
• Implemented a Path Oriented Decision Making (PODEM) algorithm for an Automatic Test Generator (ATG) for combinational logic circuits with re-convergent fan-out.
• The generated test vectors were verified using deductive fault simulation.
• The fault coverage after implementing Random Test Generator (RTG) was calculated and plotted.
• The ATG, RTG and fault simulator were all written in more than 1200+ lines of code in python.
PCB Virtual Prototyping with PSpice
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VIT_Workshop.ppt
Vinoth Raj R teaches a course on digital logic design using Verilog HDL at Velammal Institute of Technology. The course covers various topics related to Verilog including data types, operators, levels of abstraction for modeling circuits, gate-level modeling using primitives, user-defined primitives, data flow modeling, behavioral modeling, and file handling. The emphasis is on modeling, verifying, and synthesizing digital circuits specified in Verilog.
AMS SoC Formal Verification based on Hybrid Scheme
This paper proposes for AMS SoC formal
verification based on Hybrid Scheme combined with symbolic
computing and LHPN model, FV-HS. The paper is concerned
with a class of AMS designs, continuous-time AMS designs
i.e., tunnel diode oscillator for research target. Firstly,
Labeled Hybrid Petri Net model is established for safety
property verification of tunnel diode oscillator, then
mathematical expression for this model is extracted for
efficiency enhancement, and then proof policy built in
computer algebra Maple is applied to the corresponding
LHPN model for tunnel diode oscillator to verify the
property. The proposed method is implemented on tunnel
diode oscillator and experiment results demonstrate the
advantages of the proposed method over previous method.
The proposed method overcomes the drawbacks of LHPN,
makes full use of the merits of LHPN and symbolic
computing, simplifies the workflow of algorithm and
enhances the efficiency.
High speed customized serial protocol for IP integration on FPGA based SOC ap...
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
DSP Based Implementation of Scrambler for 56kbps Modem
Scrambler is generally employed in data communication systems to add redundancy in the transmitted data stream so that at the receiver end, timing information can be retrieved to aid the synchronization between data terminals. Present paper deals with simulation and implementation of the scrambler for 56Kbps voice-band modem. Scrambler for the transmitter of 56kbps modem was chosen as a case study. Simulation has been carried out using Simulink of Matlab. An algorithm for the scrambling function has been developed and implemented on Texas Instrument’s based TMS320C50PQ57 Digital Signal Processor (DSP). Signalogic DSP software has been used to compare the simulated and practical results.
SHERLOG DFR 2016
The document describes the components and modules of the SHERLOG CRX fault recorder and power quality measuring system. It includes a description of the basic device structure, power supply units, CPU and relays modules, analog and binary input modules, optional fibre optic and synchronization modules. It also provides an overview of the SHERLOG operating software for configuration, device management, evaluation and licensing. The document concludes with guidance on how to prepare an offer, including the information needed from the customer and components to include based on their requirements.
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FAULT MODELING OF COMBINATIONAL AND SEQUENTIAL CIRCUITS AT REGISTER TRANSFER ...
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Toward Automatic Generation of Models with Probes from the SDL System Specification
- 1. Toward Automatic Generation of Models with Probes from the SDL System Specification University of Maribor Faculty of Electrical Engineering and Computer Science Boštjan Vlaovič , Ph. D. [email_address] Workshop on Formal Verification of Telecommunication Systems , Part I Zagreb, 5. 11. 2004 UM FERI
- 7. Model Checking Technique system specification requirements model of the system model with probes formal verification tool SDL Promela claims, temporal formulas Şpin violation of the requirements counter-example
- 12. Promela Model of the System proctype dataLink__AtoB(pt__chan input; pt__pid parent){ pt__pid offspring, sender; byte pv__ptr, pv__cur; xr input; V76paramTyp V76par; goto ready; ready: end_1: do :: table_channum_ptr[input] > pv__cur -> table_channum_prio[input]=false; pv__cur++; pv__ptr=0; atomic{ do :: pv__ptr <= cv__buff-1 -> if :: else -> set__clear(); fi; pv__ptr++ ; :: else -> goto ready_start; od; } ready_start: if :: table_channum_prio[input]==true -> pv__ptr=0; do :: (pv__ptr <= cv__buff-1) && (table_channum_nsp[input].data[pv__ptr].prio==true) -> if /* PRIORITY INPUT */ :: else -> skip; fi; :: (pv__ptr == cv__buff) -> break; :: else -> pv__ptr++ od; :: else -> pv__ptr=0; do :: (pv__ptr <= cv__buff-1) -> if :: skip__save() :: else -> . . . }
- 16. Communication
- 20. System V76test
- 21. Block DLC[ab]
- 22. Model of the environment
- 25. Corrections of the Specification
- 31. Counter Example
Editor's Notes
- 1