This document summarizes several circuit-level techniques for reducing leakage current in cache memories, including gated-Vdd, gated-ground, drowsy caches, and asymmetric SRAM cells. Gated-Vdd and gated-ground work by adding transistors to gate the supply voltage or ground in unused sections of the cache, reducing leakage through stacking effects. Drowsy caches put unused cache lines in a low-power "drowsy" mode instead of fully powering them off. Asymmetric SRAM cells use different threshold voltages for transistors to reduce leakage when certain bit values are stored. The techniques provide varying levels of leakage reduction from 40-97% but can increase access time or circuit area as tradeoffs
Time and Low Power Operation Using Embedded Dram to Gain Cell Data RetentionIJMTST Journal
Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM because of their small size, non rationed operation, low static leakage, and two port functionality. But traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. The boosted levels require an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this paper, we present a novel, logic compatible, 3T GC-eDRAM bit cell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated in 0.25μm CMOS process targeted at low power, energy efficient application.
Process Variation and Radiation-Immune Single Ended 6T SRAM CellIDES Editor
The leakage power can dominate the system power
dissipation and determine the battery life in battery-operated
applications with low duty cycles, such as the wireless sensors,
cellular phones, PDAs or pacemakers. Driven by the need of
ultra-low power applications, this paper presents single ended
6T SRAM (static random access memory) cell which is also
radiation hardened due to maximum use of PMOS
transistors. Due to process imperfection, starting from the 65
nm technology node, device scaling no longer delivers the
power gains. Since then the supply voltage has remained
almost constant and improvement in dynamic power has
stagnated, while the leakage currents have continued to
increase. Therefore, power reduction is the major area of
concern in today’s circuit with minimum-geometry devices
such as nanoscale memories. The proposed design in this
paper saves dynamic write power more than 50%. It also
offers 29.7% improvement in TWA (write access time), 38.5%
improvement in WPWR (write power), 69.6% improvement in
WEDP (write energy delay product), 26.3% improvement in
WEDP variability, 5.6% improvement in RPWR (read power) at
the cost of 22.5% penalty in SNM (static noise margin) at
nominal voltage of VDD = 1 V. The tighter spread in write EDP
implies its robustness against process and temperature
variations. Monte Carlo simulation measurements validate
the design at 32 nm technology node.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This paper presents a spin-transfer torque- magnetic
tunnel junction (STT-MTJ) based non-volatile 9-transistor
(9T) SRAM cell. The cell achieves low power dissipation due
to its series connected MTJ elements and read buffer which
offer stacking effect. The paper studies the impact of PVT
(process, voltage, and temperature) variations on the design
metric of the SRAM cell such as write delay and compares the
results with non-volatile 8T SRAM cell (NV8T). The proposed
design consumes lower leakage power and exhibits narrower
spread in write delay compared with NV8T.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
Time and Low Power Operation Using Embedded Dram to Gain Cell Data RetentionIJMTST Journal
Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM because of their small size, non rationed operation, low static leakage, and two port functionality. But traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. The boosted levels require an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this paper, we present a novel, logic compatible, 3T GC-eDRAM bit cell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated in 0.25μm CMOS process targeted at low power, energy efficient application.
Process Variation and Radiation-Immune Single Ended 6T SRAM CellIDES Editor
The leakage power can dominate the system power
dissipation and determine the battery life in battery-operated
applications with low duty cycles, such as the wireless sensors,
cellular phones, PDAs or pacemakers. Driven by the need of
ultra-low power applications, this paper presents single ended
6T SRAM (static random access memory) cell which is also
radiation hardened due to maximum use of PMOS
transistors. Due to process imperfection, starting from the 65
nm technology node, device scaling no longer delivers the
power gains. Since then the supply voltage has remained
almost constant and improvement in dynamic power has
stagnated, while the leakage currents have continued to
increase. Therefore, power reduction is the major area of
concern in today’s circuit with minimum-geometry devices
such as nanoscale memories. The proposed design in this
paper saves dynamic write power more than 50%. It also
offers 29.7% improvement in TWA (write access time), 38.5%
improvement in WPWR (write power), 69.6% improvement in
WEDP (write energy delay product), 26.3% improvement in
WEDP variability, 5.6% improvement in RPWR (read power) at
the cost of 22.5% penalty in SNM (static noise margin) at
nominal voltage of VDD = 1 V. The tighter spread in write EDP
implies its robustness against process and temperature
variations. Monte Carlo simulation measurements validate
the design at 32 nm technology node.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This paper presents a spin-transfer torque- magnetic
tunnel junction (STT-MTJ) based non-volatile 9-transistor
(9T) SRAM cell. The cell achieves low power dissipation due
to its series connected MTJ elements and read buffer which
offer stacking effect. The paper studies the impact of PVT
(process, voltage, and temperature) variations on the design
metric of the SRAM cell such as write delay and compares the
results with non-volatile 8T SRAM cell (NV8T). The proposed
design consumes lower leakage power and exhibits narrower
spread in write delay compared with NV8T.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
Analysis and Simulation of Sub-threshold Leakage Current in P3 SRAM Cell at D...IDES Editor
In this work, the analysis and simulation work is
proposed for the low-power (reduced subthreshold leakage)
and high performance SRAM bit-cells for mobile multimedia
applications in deep-sub-micron (DSM) CMOS technology.
The sub-threshold leakage analysis of the P3 SRAM cell has
been carried out. It has been observed that due to pMOS
stacking and full supply body-biasing, there is a reduction of
70% and 86% in sub-threshold leakage current at VDD=0.8V
and VDD=0.7V respectively as compared to conventional 6T
SRAM cell. Due to this a reduction in the standby power has
been achieved w.r.t the 6T and PP SRAM design at a bearable
expense of the SVNM and the WTV.
A SINGLE-ENDED AND BIT-INTERLEAVING 7T SRAM CELL IN SUB-THRESHOLD REGION WITH...jedt_journal
In recent years, to reduce power consumption and increase cell resistance against soft error, several subthreshold SRAM cell have been provided. Also, in the memory design, to increase the memory density and reduce the occupied area, sub-100 nm technologies have been used. These technologies also increase the sensitivity of the cell against soft error. Among the proposed methods to confront soft error, bitinterleaving
structure is one of the most successful methods. But the designed bit-interleaving cells usually have many transistors in order to achieve the ideal features. Moreover, another problem in the bitinterleaving cells is half-select issue. In this paper, a single-ended sub-threshold cell is presented. This cell has been designed in multi-Vt 32nm technology. On the other hand, the suggested cell can be implemented in the bit-interleaving structure to confront soft error. In the cell, 7 transistors have been used while the cell is without half-select problem. Simulations show the suggested cell has less power consumption compared with standard 6T and other bit-interleaving cells. Also, in the proposed cell, write margin and
write time delay are better than the under comparison cells, while the suggested cell stability in read and hold modes and read time delay are also optimal.
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
Design and implementation of 4 t, 3t and 3t1d dram cell design on 32 nm techn...VLSICS Design
In this paper average power consumption, write access time, read access time and retention time of dram
cell designs have been analyzed for the nano-meter scale memories. Many modern day processors use
dram cell for on chip data and program memory storage. The major power in dram is the off state leakage
current. Improving on the power efficiency of a dram cell is critical for the improvement in average power
consumption of the overall system. 3T dram cell, 4T dram and 3T1D DRAM cells are designed with the
schematic design technique and their average power consumption are compared using TANNER EDA tool
.average power consumption, write access time, read access time and retention time of 4T, 3T dram and
3T1D DRAM cell are simulated and compared on 32 nm technology
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
FPGA IMPLEMENTATION OF RECOVERY BOOSTING TECHNIQUE TO ENHANCE NBTI RECOVERY I...Editor IJMTER
Negative Bias Temperature Instability is an important lifetime reliability problem in
microprocessors. SRAM-based structures within the processor are especially susceptible to NBTI
since one of the PMOS devices in the memory cell always has an input of ‘0’. Previously proposed
recovery techniques for SRAM cells aim to balance the degradation of the two PMOS devices by
attempting to keep their inputs at a logic ‘0’ exactly 50% of the time. However, one of the devices is
always in the negative bias condition at any given time. In this paper, we propose a technique called
Recovery Boosting that allows both PMOS devices in the memory cell to be put into the recovery
mode by slightly modifying the design of conventional SRAM cells to verify its functionality and
quantity area and power consumption.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Analysis and Simulation of Sub-threshold Leakage Current in P3 SRAM Cell at D...IDES Editor
In this work, the analysis and simulation work is
proposed for the low-power (reduced subthreshold leakage)
and high performance SRAM bit-cells for mobile multimedia
applications in deep-sub-micron (DSM) CMOS technology.
The sub-threshold leakage analysis of the P3 SRAM cell has
been carried out. It has been observed that due to pMOS
stacking and full supply body-biasing, there is a reduction of
70% and 86% in sub-threshold leakage current at VDD=0.8V
and VDD=0.7V respectively as compared to conventional 6T
SRAM cell. Due to this a reduction in the standby power has
been achieved w.r.t the 6T and PP SRAM design at a bearable
expense of the SVNM and the WTV.
A SINGLE-ENDED AND BIT-INTERLEAVING 7T SRAM CELL IN SUB-THRESHOLD REGION WITH...jedt_journal
In recent years, to reduce power consumption and increase cell resistance against soft error, several subthreshold SRAM cell have been provided. Also, in the memory design, to increase the memory density and reduce the occupied area, sub-100 nm technologies have been used. These technologies also increase the sensitivity of the cell against soft error. Among the proposed methods to confront soft error, bitinterleaving
structure is one of the most successful methods. But the designed bit-interleaving cells usually have many transistors in order to achieve the ideal features. Moreover, another problem in the bitinterleaving cells is half-select issue. In this paper, a single-ended sub-threshold cell is presented. This cell has been designed in multi-Vt 32nm technology. On the other hand, the suggested cell can be implemented in the bit-interleaving structure to confront soft error. In the cell, 7 transistors have been used while the cell is without half-select problem. Simulations show the suggested cell has less power consumption compared with standard 6T and other bit-interleaving cells. Also, in the proposed cell, write margin and
write time delay are better than the under comparison cells, while the suggested cell stability in read and hold modes and read time delay are also optimal.
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
Design and implementation of 4 t, 3t and 3t1d dram cell design on 32 nm techn...VLSICS Design
In this paper average power consumption, write access time, read access time and retention time of dram
cell designs have been analyzed for the nano-meter scale memories. Many modern day processors use
dram cell for on chip data and program memory storage. The major power in dram is the off state leakage
current. Improving on the power efficiency of a dram cell is critical for the improvement in average power
consumption of the overall system. 3T dram cell, 4T dram and 3T1D DRAM cells are designed with the
schematic design technique and their average power consumption are compared using TANNER EDA tool
.average power consumption, write access time, read access time and retention time of 4T, 3T dram and
3T1D DRAM cell are simulated and compared on 32 nm technology
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
FPGA IMPLEMENTATION OF RECOVERY BOOSTING TECHNIQUE TO ENHANCE NBTI RECOVERY I...Editor IJMTER
Negative Bias Temperature Instability is an important lifetime reliability problem in
microprocessors. SRAM-based structures within the processor are especially susceptible to NBTI
since one of the PMOS devices in the memory cell always has an input of ‘0’. Previously proposed
recovery techniques for SRAM cells aim to balance the degradation of the two PMOS devices by
attempting to keep their inputs at a logic ‘0’ exactly 50% of the time. However, one of the devices is
always in the negative bias condition at any given time. In this paper, we propose a technique called
Recovery Boosting that allows both PMOS devices in the memory cell to be put into the recovery
mode by slightly modifying the design of conventional SRAM cells to verify its functionality and
quantity area and power consumption.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Médicos têm alertado há anos para os riscos à saúde do consumo excessivo de sal. Agora, imagine um lugar construído apenas com esses minúsculos cristais brancos capaz de encantar as pessoas. Quem chega à pacata cidade de Wieliczka, no sul da Polônia, nem imagina que ela está localizada exatamente sobre a mais antiga mina de sal em atividade do mundo. Leia mais em: www.dzai.com.br/alfandegario/blog/alfandegario
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of Memory Cell for Low Power ApplicationsIJERA Editor
Aggressive CMOS scaling results in lower threshold voltage and thin oxide thickness for transistors manufactured in nano regime. As a result, reducing the sub-threshold and tunneling gate leakage currents has become crucial in the design of ICs. This paper presents a new method to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance.
FPGA IMPLEMENTATION OF LOW POWER SRAM BASED PROCESSOR IN 8T USING HETTSEditor IJMTER
In MOSFETs lower limit sub threshold swing (60mv/decade) restricts the low power
operation. Low voltage operation is enabled by low Vth while maintaining performance. Hence steep
sub threshold slopes provide power-efficient operation without any loss of performance. To obtain
sub threshold swings of less than 30mV/decade with large ON current, Si/SiGe heterojunction
tunneling transistor uses gate controlled modulation. To overcome the impact of HETT
characteristics on SRAM, seven transistors HETT based SRAM design is introduced. Compared to
CMOS this new 8T HETT SRAM achieves reduction in leakage power.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Research Inventy : International Journal of Engineering and Scienceresearchinventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
Testing DRAM and Correcting errorsby using Adaptive TechniqueIJERA Editor
DRAM(dynamic random access memory) is most widely used in memorytoday. Leakage power is the main
issue of DRAM cell. Iteffects the performance of the DRAM. In this paper introduce a new technique ie
adaptive technique a spare wire is used to reroute the data in cell which is damaged
Implementation of pull up pull-down network for energy optimization in full a...IJARIIT
Nowadays the requirements of energy optimized low power circuits in higher-end applications such as
communication, IoT, biomedical systems etc., there are several techniques used to implement energy optimization in low power
circuits but the static power dissipation need to improve such kind of circuits. The conventional topology has been
implemented in basic logical gates but the delay and power much higher in each individual cell. Now we proposed an
unbalanced pull-up and pull-down network in full adder circuit using symbols. These techniques were employed to reduce the
static power dissipation and switching delay in each individual cell. The design was implemented in Cadence virtuoso TMSC
180nm CMOS technology and it’s obtaining the total power dissipation 5.128nW.The pull-up and pull-down network used to
reduce the static power dissipation in full adder is used to improve the operating speed of each individual.
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1. Urvashi Chaudhari, Rachna Jani / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 2, March -April 2013, pp.457-460
A Study of Circuit Level Leakage Reduction Techniques in Cache
Memories
Urvashi Chaudhari*, Rachna Jani**
*(Department of Electronics & Communication, CHARUSAT University, Changa)
** (Associate Professor Department of Electronics & Communication, CHARUSAT University, Changa)
ABSTRACT
The Performance of microprocessor can by low-VTH MOSFET and leakage current by high-
be improved by increasing the capacity of on-chip VTH MOSFET [2]. This technique use high-VTH
caches. On-chip caches consume noticeable pMOSFET and nMOSFET as a Switch for
fraction of total power consumption of disconnecting power supply in standby mode and
microprocessors. The performance gained can be thereby reduce leakage current. Disadvantage of this
achieved by reducing energy consumption due to circuits are fabrication of MOS with different
leakage current in cache memories. The threshold-voltage, increase overall circuit area and it
technique for power reduction in cache is divided adds extra parasitic capacitance and delay. Another
in mainly two parts Circuit level and technique is Dual VTH [3]. It uses low VTH for
architectural level technique. In this paper a critical path and high VTH for rest of the circuit. Due
circuit level techniques like gated-Vdd, gated- to high VTH, it increases the access time of the
Ground, Drowsy caches, Asymmetric SRAM cell memory cell. Dynamic sleep transistor also used as
for reducing leakage current in cache memory leakage reduction technique [4]. In that sleep
are discussed. transistor is use to isolate the circuit from the
supply.
Keywords - Asymmetric cell, Cache memory, The rest of the paper organized as follows:
Drowsy caches, Gated-ground, Gated-Vdd, leakage Section II describes Gated- Vdd techniques. Section
current. III describes Data retention gated-ground cache.
Section IV describes Drowsy cache. Section V
I. INTRODUCTION describes Asymmetric SRAM cell. Section VI
A Microprocessor devotes a large fraction describes Conclusion.
of chip area for memory structure. Due to large size
of on-chip caches reduction of leakage current even II. GATED-VDD: GATING THE SUPPLY
in single cell of cache can reduce a large fraction of VOLTAGE
the total power in the microprocessor. The main To prevent leakage power dissipation in
memory compared to cache memory is slow and not DRI i-cache [5] a circuit level technique, gated- VDD
able to maintain the speed with processor. Cache is used, by gating the supply voltage from the
memory is placed between the main memory and SRAM cell of the cache unused portion [6].
the processor. SRAMs are used as a cache memory A. SRAM Cell with gated- Vdd :
because they are faster and not required periodic In this techniques an extra transistor in the supply
refresh compared to DRAM. Now leakage current voltage or the ground of the cache‟s SRAM cell is
becomes a major contributor for power dissipation added as shown in fig.1, it turn on in the used
in CMOS circuit in deep submicron technology. So, section and turn off in unused section, so the cell‟s
reduction in leakage current becomes main task for supply voltage is gated. The main reason behind the
designers. It is also important to estimate leakage reduction in leakage current is stacking effect of self
current in CMOS at nanotechnology. An efficient reverse-biasing series-connected transistors.
technique for estimating leakage current has been
proposed in [1]
Many circuit and architecture level techniques have
been proposed for leakage reduction. The
architectural level technique can reduce power
significantly but it produce negative impact on
performance. So that in this paper some of circuit
level techniques are discussed which reduces
leakage and less impacts on performance. There are
many circuit level techniques for leakage current
reduction. One of them is multi-threshold CMOS
(MTCMOS) technique. It increases operating speed
Fig.1. SRAM cell with an nMOS Gated-Vdd [6].
457 | P a g e
2. Urvashi Chaudhari, Rachna Jani / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 2, March -April 2013, pp.457-460
This technique maintains both lower supply and data retention capability reduces the leakage power
threshold voltage while reducing leakage current. by 97% while increasing read time by 8% using
Gated-Vdd transistor must be large enough to sink 0.2v and 0.4v for low and high VTH respectively [7].
the current through SRAM cell, but a large transistor
may reduce the stacking effect and also increase the III. Data Retention Gated-Ground Cache
area overhead. So here a trade-off between area over (DRG-Cache):
head and leakage reduction. In this technique an extra nMOS transistor
connected between ground and virtual ground node
B. Trade- offs between nMOS and pMOS Gated of SRAM cell, which is called gated-ground. In this
Vdd transistor: technique, to reduce power, the unused section of
By Using nMOS transistor as Gated-Vdd, it the memory is put in to the low leakage mode.
reduce standby leakage current through stacking Gated-ground transistor enables a DRG-cache to
effect of three series connected nMOS transistor turn off the supply voltage and eliminate leakage
between bitlines and ground. Alternatively, using energy virtually in unused section of the memory
pMOS transistor it reduces required transistor width [8].
and thereby reduce area overhead, and also it not A. DRG-Cache Technique with SRAM Cell
provide the isolation between the bitlines and the
ground as nMOS, reducing energy saving. nMOS
gated-Vdd impact on cell performance while pMOS
not significantly impact on the cell performance.
There is a fundamental trade-off between reduction
in leakage, transistor switching speed and area
overhead of gated-Vdd transistor.
C. Impact of lowering threshold voltage:
In table 1 from first three rows it is
concluded that decreasing threshold voltage of
SRAM cell increases active leakage energy and
standby leakage energy. From last three rows, if Fig.2. Circuit of gated-ground transistor with SRAM
threshold voltage of gated-Vdd decrease than there cell [8].
is further reduction in the standby leakage energy. In fig. 2 light colour transistor are on and
dark colour transistor are off. The extra transistor
Table 1. Impacts of changing SRAM and gated-Vdd turns on in the used section and turn off in unused
threshold Voltages [6] section of the memory thereby gating the supply
voltage. As in the gated-Vdd technique, this
technique reduces leakage due to series connection
of two off transistor. This effect is due the stacking
effect. Here this technique retains the data which is
not possible in the case of gated-Vdd. A careful
design of transistor is necessary because size of the
gated-ground is important in data retention and
stability.
B. Energy Performance Trade-off:
D. Impact of widening gated-Vdd transistor: Table 3. Energy performance trade-off [8]
Table 2. Widening the gated-Vdd transistor [6]
First two rows of table3 shows that
increasing the width of the gated-ground transistor
From table 2 it is shown that by increasing the size improve the read time, data retention capability and
of the gated-Vdd transistor read time of the circuit stability of cell, but decrease the energy saving and
decreases but active and standby leakage energy increases the area. Last two row shows that
increases. For a processor this technique without threshold voltage increases the leakage energy. This
458 | P a g e
3. Urvashi Chaudhari, Rachna Jani / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 2, March -April 2013, pp.457-460
technique for a processor with VTH 250mv reduce voltage, while asymmetric SRAM cells have low
leakage power by 40% while increase read time by leakage and less impact on performance. In this
4.4% compared to conventional Cache [7]. technique when cell is storing „0‟, selected
transistors are “weakened” to reduce leakage. A
IV. DROWSY CACHES: weakening can be possible by using higher threshold
In Caches, for fix period of time the voltage and also by proper sizing of transistor.
activity is centred at some cache lines. So, putting In conventional SRAM of symmetrical transistor to
rest of cache lines in low power mode can reduce reduce leakage current one method can be used that
the leakage significantly. This low power mode of is making all transistors of high Vth, but it degrades
cache line is called Drowsy Caches [9][10]. In stand the performance. This drawback can be overcome
of turning off cache line putting it in to a low power by using asymmetric SRAM cell. It works on
drowsy mode can reduce leakage significantly. In following principle: selecting a preferred stored
drowsy caches the chance of putting wrong line into value and weaken only those transistors necessary to
drowsy mode is less, for that different policies have reduce leakage by increasing the threshold voltage
been proposed in [9]. When caches are in drowsy when this value is stored.
mode the data in it are preserved. Drowsy caches
can be implemented by adaptive body-biasing with A. Working of Asymmetric SRAM Cell:
multi-threshold CMOS (ABB-CMOS), dynamic In cell most of the leakage is dissipated by
voltage scaling (DVS). Gated-Vdd. transistors that are off and have a voltage
differential across their drain and source. This state
A. Drowsy memory circuit: of transistor can be finding by the value stored in it.
As shown in fig.3 SRAM cell is connected When a cell storing a„0‟ value, as shown in fig.4, the
to voltage-scaling controller. This controller consist leaky transistors will be P1, N4 and N2. If cell was
of two pMOS pass transistor, one with high storing „1‟ value then leakage transistor would be
threshold voltage while other with low threshold P2, N1 and N3.
voltage. One pMOS supplies normal supply voltage
and other low for drowsy cache lines. Each pass
transistor of SRAM cell is of high Vth to prevent the
leakage current from the normal supply to the low
supply through the two pMOS pass gate transistor.
For each cache line a separate voltage controller is
needed.
Fig.4. SRAM Cell with storing a „0‟ value [11].
To reduce leakage in cell when it storing a
„0‟ value, replace leaky transistor by high Vth. The
resulted circuit is shown in fig. 5, which is called
basic asymmetric (BA) SRAM cell. This circuit has
Fig.3. Schematic of Drowsy memory circuit [9]. the same leakage as conventional SRAM cell when
storing „1‟, but it reduces leakage by 70 times when
A possible disadvantage of this circuit is storing „0‟., due to longer discharge time.
that increased susceptibility to noise. In a 0.07um
CMOS process, drowsy caches will be able to
reduce the total energy consumption by 50% -75%,
and cache lines can be maintained in drowsy mode
without affecting performance by more than 1% [9].
V. Asymmetric SRAM Cell:
As this technique used in cache it is refer to
as asymmetric-cell caches (ACCs). Comparing to
conventional cache ACCs reduce leakage power
even when there are few parts of the cache that are
left unused [11]. Traditional SRAM cell transistors Fig.5.Basic asymmetric SRAM cell [11].
are symmetrical with identical leakage and threshold
459 | P a g e
4. Urvashi Chaudhari, Rachna Jani / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 2, March -April 2013, pp.457-460
To improve in leakage reduction and speed [3] J.Kao, and A. Chandrakasan, “ Dual-
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Techniques Leakage Impact on Computer Engineering, Purdue
reduction performance University,2000.
[6] M.powell,S.Yang, B Falsafi, k.Roy, T
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Vijaykumar, “Gated-VDD: A circuit
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[8] Amit Agarwal, Hai Li, Student Member,
The comparison of all technique is shown
IEEE, and Kaushik Roy, Fellow, IEEE, “A
in Table4.From this comparison it can be concluded
Single-Vt Low-Leakage Gated-Ground
that asymmetric cell and drowsy cache are better
Cache for Deep Submicron”, IEEE J. Of
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Solid-State Circuits, Vlo.38, no.2, February
asymmetric cell have high leakage reduction and
2003.
better performance, it has some drawbacks.
[9] K. Flautner, Nam sung kim, S. Martin, D.
Asymmetric cell do not consider gate leakage
Blaauw and T. Mudge, “Drowsy Caches:
component so that their total leakage saving will be
simple techniques for reducing leakage
less. However asymmetric cells are expected to
power,” proc. Of IEEE/ACM Intl.Symp. on
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computer Architecture, PP. 148~157, 2002.
high operating temperature. Furthermore in
[10] Nam sung kim, K. Flautner, D. Blaauw and
successive technologies, the stability of asymmetric
T. Mudge, “Drowsy instruction cache-
cells may decrease.
Leakage power reduction using dynamic
voltage scaling and cache sub-bank
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