This document presents a new low power SRAM design that combines column decoupling with virtual grounding. It summarizes existing SRAM designs including the conventional 6T SRAM, 8T column decoupled SRAM, and virtual grounding SRAM. It then proposes a new 7T SRAM design that uses virtual grounding to improve read stability over the 6T SRAM. Finally, the document describes a simulation comparing the proposed design that combines 8T column decoupling and virtual grounding to the existing designs, showing it achieves lower power at 50nm technology with reduced area.
Process Variation and Radiation-Immune Single Ended 6T SRAM CellIDES Editor
The leakage power can dominate the system power
dissipation and determine the battery life in battery-operated
applications with low duty cycles, such as the wireless sensors,
cellular phones, PDAs or pacemakers. Driven by the need of
ultra-low power applications, this paper presents single ended
6T SRAM (static random access memory) cell which is also
radiation hardened due to maximum use of PMOS
transistors. Due to process imperfection, starting from the 65
nm technology node, device scaling no longer delivers the
power gains. Since then the supply voltage has remained
almost constant and improvement in dynamic power has
stagnated, while the leakage currents have continued to
increase. Therefore, power reduction is the major area of
concern in today’s circuit with minimum-geometry devices
such as nanoscale memories. The proposed design in this
paper saves dynamic write power more than 50%. It also
offers 29.7% improvement in TWA (write access time), 38.5%
improvement in WPWR (write power), 69.6% improvement in
WEDP (write energy delay product), 26.3% improvement in
WEDP variability, 5.6% improvement in RPWR (read power) at
the cost of 22.5% penalty in SNM (static noise margin) at
nominal voltage of VDD = 1 V. The tighter spread in write EDP
implies its robustness against process and temperature
variations. Monte Carlo simulation measurements validate
the design at 32 nm technology node.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Built-in Self Repair for SRAM Array using RedundancyIDES Editor
In this paper, a built-in self repair technique for
word-oriented two-port SRAM memories is presented. The
technique is implemented by additional hardware design
instead of traditional software diagnostic procedures and the
computation time is minimized. A built-in self-test (BIST) is
used to detect the faulty locations which are isolated
immediately after detection. Therefore, the redirection process
can be executed as soon as possible. Spare rows are used to
replace the faulty rows. The hardware overhead of the
automatic fault isolation design depends on size of memory
system. All the repairs using BISR circuit are done at power
on.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed...VLSICS Design
Abstract This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) cell and Dynamic Random Access Memory (DRAM) cell to develop low power consumption. SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 12-transistor SRAM cell built from a simple static latch and tri state inverter. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines.
Process Variation and Radiation-Immune Single Ended 6T SRAM CellIDES Editor
The leakage power can dominate the system power
dissipation and determine the battery life in battery-operated
applications with low duty cycles, such as the wireless sensors,
cellular phones, PDAs or pacemakers. Driven by the need of
ultra-low power applications, this paper presents single ended
6T SRAM (static random access memory) cell which is also
radiation hardened due to maximum use of PMOS
transistors. Due to process imperfection, starting from the 65
nm technology node, device scaling no longer delivers the
power gains. Since then the supply voltage has remained
almost constant and improvement in dynamic power has
stagnated, while the leakage currents have continued to
increase. Therefore, power reduction is the major area of
concern in today’s circuit with minimum-geometry devices
such as nanoscale memories. The proposed design in this
paper saves dynamic write power more than 50%. It also
offers 29.7% improvement in TWA (write access time), 38.5%
improvement in WPWR (write power), 69.6% improvement in
WEDP (write energy delay product), 26.3% improvement in
WEDP variability, 5.6% improvement in RPWR (read power) at
the cost of 22.5% penalty in SNM (static noise margin) at
nominal voltage of VDD = 1 V. The tighter spread in write EDP
implies its robustness against process and temperature
variations. Monte Carlo simulation measurements validate
the design at 32 nm technology node.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Built-in Self Repair for SRAM Array using RedundancyIDES Editor
In this paper, a built-in self repair technique for
word-oriented two-port SRAM memories is presented. The
technique is implemented by additional hardware design
instead of traditional software diagnostic procedures and the
computation time is minimized. A built-in self-test (BIST) is
used to detect the faulty locations which are isolated
immediately after detection. Therefore, the redirection process
can be executed as soon as possible. Spare rows are used to
replace the faulty rows. The hardware overhead of the
automatic fault isolation design depends on size of memory
system. All the repairs using BISR circuit are done at power
on.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed...VLSICS Design
Abstract This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) cell and Dynamic Random Access Memory (DRAM) cell to develop low power consumption. SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 12-transistor SRAM cell built from a simple static latch and tri state inverter. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Comparison of PMD Compensation in WDM SystemsIOSR Journals
The need for larger capacities in long haul optical digital transmission lead to greater channel
density which can be achieved by wavelength division multiplexing and increasing the bit rate of each channel.
As data rates increases, certain phenomena such as dispersion began to show up as obstacles. At higher bit
rates beyond 2.5Gbps polarization mode dispersion (PMD) becomes a main factor in the degradation of the
transmission characteristics. PMD occurs when slightly different planes of light inside a fiber travel at slightly
different speeds and make it impossible to transmit data reliably at high speed in single mode fibers. PMD is
caused due to optical birefringence in the fiber due to which the two modes within a single mode fiber travel
with different group velocities and the random change of this birefringence along the fiber length results in
random coupling between the modes. This effect of PMD results in broadening of transmitted pulses that limit
the transmission capacity of the fiber. In high-speed optical communication systems working at data rates of
10Gbps and beyond, signal distortion caused by PMD is also a major limitation of the transmission distance.
This paper intends to analyze the performance of PMD compensation by optical compensation technique and
using DCF in a two channel WDM system. The analysis is done through eye diagrams from which the Q value
and bit error rate can be determined by simulating with OptSim5.3, which includes the latest simulation
algorithms to guarantee the highest possible accuracy and real world results
This paper proposes a variation – tolerant dual-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. The use of appropriate DCNT (diameter of CNFET) and hence Vt of CNFETs is a critical piece of our design strategy. In this work, dual-Vt and dual-diameter CNFETs have been used using suitable chiral vectors for appropriate transistors. It also investigates the impact of process, voltage and temperature variations on its design metrics and compares the results with its counterpart − CMOS-based 7T SRAM cell and standard 6T SRAM cell (only few parameters). The proposed SRAM cell offers 1.35× and 1.25× improvement in standby power on an average @ VDD = 1 V and 0.9 V respectively, 30% improvement in SNM (Static Noise Margin) over CMOS-based 7T cell. Proposed design outperforms 6T in terms of 71.4% improvement in RSNM and shows same read stability as its CMOS counterpart, It shows its robustness by offering 1.4× less spread in TRA (read access time) at 1 V and 1.2× less spread in TRA at 0.9 V than that of its CMOS counterpart at the expense of 1.6× read delay. The proposed bitcell also exhibits higher performance while writing (takes 1.3× and 1.2× less TWA (write access time) @ VDD = 1 V and VDD= 0.9 V respectively). It also proves its robustness against process variations by featuring tighter spread in TWA variability (1.4× and 1.2× @ VDD= 1 V and 0.9 V respectively).
A Low Control Overhead Cluster Maintenance Scheme for Mobile Ad hoc NETworks ...IDES Editor
Clustering is an important research area for
mobile ad hoc networks (MANETs) as it increases the
capacity of network, reduces the routing overhead and
makes the network more scalable in the presence of both
high mobility and a large number of mobile nodes. In
clustering the clusterhead manage and store recent routing
information. However the frequent change of clusterhead
leads to loss of routing information stored, changes the route
between two nodes, affects the performance of the routing
protocol and makes the cluster structure unstable.
Communication overhead in terms of exchanging messages
is needed to elect a new clusterhead. The goal then would be
to keep the clusterhead change as least as possible to make
cluster structure more stable, to prevent loss of routing
information which in turn improve the performance of
routing protocol based on clustering. This can be achieved
by an efficient cluster maintenance scheme. In this work, a
novel clustering algorithm, namely Incremental
Maintenance Clustering Scheme (IMS) is proposed for
Mobile Ad Hoc Networks. The goals are yielding low
number of clusterhead and clustermember changes,
maintaining stable clusters, minimizing the number of
clustering overhead. Through simulations the performance
of IMS is compared with that of least cluster change (LCC)
and maintenance scheme of Cluster Based Routing Protocol
(CBRP) in terms of the number of clusterhead changes,
number of cluster-member changes and clustering overhead
by varying mobility and speed. The simulation results
demonstrate the superiority of IMS over LCC and
maintenance scheme of CBRP.
17 9253 denial of impedance for mobile cellular (edit ari)IAESIJEECS
Wireless network broadly utilized today incorporate, cell system, remote cross section system (WMNs), remote neighbourhood and individual zone system. The expanding interest for these systems has transformed range into a valuable asset. Consequently, there is dependably a requirement for techniques to pack more bits/Hz. In this paper, we list the purposes behind this far reaching doubt, and talk about how present and future patterns will expand the need and reasonability of multiuser collectors for both the uplink, where numerous offbeat clients will be all the while identified, and the downlink, where clients will be planned and generally orthogonal zed, yet the portable handset will in any case need to adapt to a couple of predominant meddling base stations. New results for impedance wiping out beneficiaries that utilization traditional front finishes are appeared to ease a large number of the deficiencies of earlier systems, especially for the testing uplink. This paper gives a diagram of key late research leaps forward on obstruction cancelation, and highlights framework level contemplations for future multiuser recipients.
Project Report on Modeling and Robust Control of Blu-Ray disc Servo MechanismsManu Mitra
This project deals with the modeling and the robust control of the next generation of optical disc drives servo-mechanisms. While in many industrial servo-control implementations, the radial and focus loops are considered as decoupled, e.g. DVD drives, this is no longer true for HD-DVD and Blu-ray disc (BD) formats which are more sensitive to opto-mechanical interactions at high frequencies. The impact of such phenomena on the robustness of the servo is evaluated by using experimental data, and an h∞ controller is designed to reduce the coupling effect, by using a suitable disturbance model into the problem formulation. Simulations using experimental data illustrate the performance improvement of the compensated system despite the parametric uncertainties in mass-production optical drives. (Aug 2009 - Dec 2009)
Optical waveguiding systems constructions and applicationseSAT Journals
Abstract
The basic geometry of a waveguide reflects its functions. These consist of wave simulation for information carriers, guiding and networking in the telecommunication industry, applying the laser guided modes in various research areas such as particle dispersion and randomization effect theories. The basic uitlity of a waveguiding system is determined by the optical efficiency of that system, which is the percentage ratio of effective transmission carried out by that particular waveguide. Advanced guiding networks consist of complex tubes with different alterations in their sizes in order to fulfill this requirement. As the industry grows, so does the demand for wave simulation techniques and thus, day by day new methods are being developed which focus on the development of effective wave propogation. Another important factor which is included in the designing of wave guiding devices is the frequency of the optical signal. A signal with significantly higher frequency bands will be guided through a complex system which in turn does not guide waves of lower frequency. Conventional designs have been consisting of the long hollow metallic tubes which guide the electromagnetic signals towards the receiving ends. However, slight deviation is being observed in the newly enhanced devicing.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Comparison of PMD Compensation in WDM SystemsIOSR Journals
The need for larger capacities in long haul optical digital transmission lead to greater channel
density which can be achieved by wavelength division multiplexing and increasing the bit rate of each channel.
As data rates increases, certain phenomena such as dispersion began to show up as obstacles. At higher bit
rates beyond 2.5Gbps polarization mode dispersion (PMD) becomes a main factor in the degradation of the
transmission characteristics. PMD occurs when slightly different planes of light inside a fiber travel at slightly
different speeds and make it impossible to transmit data reliably at high speed in single mode fibers. PMD is
caused due to optical birefringence in the fiber due to which the two modes within a single mode fiber travel
with different group velocities and the random change of this birefringence along the fiber length results in
random coupling between the modes. This effect of PMD results in broadening of transmitted pulses that limit
the transmission capacity of the fiber. In high-speed optical communication systems working at data rates of
10Gbps and beyond, signal distortion caused by PMD is also a major limitation of the transmission distance.
This paper intends to analyze the performance of PMD compensation by optical compensation technique and
using DCF in a two channel WDM system. The analysis is done through eye diagrams from which the Q value
and bit error rate can be determined by simulating with OptSim5.3, which includes the latest simulation
algorithms to guarantee the highest possible accuracy and real world results
This paper proposes a variation – tolerant dual-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. The use of appropriate DCNT (diameter of CNFET) and hence Vt of CNFETs is a critical piece of our design strategy. In this work, dual-Vt and dual-diameter CNFETs have been used using suitable chiral vectors for appropriate transistors. It also investigates the impact of process, voltage and temperature variations on its design metrics and compares the results with its counterpart − CMOS-based 7T SRAM cell and standard 6T SRAM cell (only few parameters). The proposed SRAM cell offers 1.35× and 1.25× improvement in standby power on an average @ VDD = 1 V and 0.9 V respectively, 30% improvement in SNM (Static Noise Margin) over CMOS-based 7T cell. Proposed design outperforms 6T in terms of 71.4% improvement in RSNM and shows same read stability as its CMOS counterpart, It shows its robustness by offering 1.4× less spread in TRA (read access time) at 1 V and 1.2× less spread in TRA at 0.9 V than that of its CMOS counterpart at the expense of 1.6× read delay. The proposed bitcell also exhibits higher performance while writing (takes 1.3× and 1.2× less TWA (write access time) @ VDD = 1 V and VDD= 0.9 V respectively). It also proves its robustness against process variations by featuring tighter spread in TWA variability (1.4× and 1.2× @ VDD= 1 V and 0.9 V respectively).
A Low Control Overhead Cluster Maintenance Scheme for Mobile Ad hoc NETworks ...IDES Editor
Clustering is an important research area for
mobile ad hoc networks (MANETs) as it increases the
capacity of network, reduces the routing overhead and
makes the network more scalable in the presence of both
high mobility and a large number of mobile nodes. In
clustering the clusterhead manage and store recent routing
information. However the frequent change of clusterhead
leads to loss of routing information stored, changes the route
between two nodes, affects the performance of the routing
protocol and makes the cluster structure unstable.
Communication overhead in terms of exchanging messages
is needed to elect a new clusterhead. The goal then would be
to keep the clusterhead change as least as possible to make
cluster structure more stable, to prevent loss of routing
information which in turn improve the performance of
routing protocol based on clustering. This can be achieved
by an efficient cluster maintenance scheme. In this work, a
novel clustering algorithm, namely Incremental
Maintenance Clustering Scheme (IMS) is proposed for
Mobile Ad Hoc Networks. The goals are yielding low
number of clusterhead and clustermember changes,
maintaining stable clusters, minimizing the number of
clustering overhead. Through simulations the performance
of IMS is compared with that of least cluster change (LCC)
and maintenance scheme of Cluster Based Routing Protocol
(CBRP) in terms of the number of clusterhead changes,
number of cluster-member changes and clustering overhead
by varying mobility and speed. The simulation results
demonstrate the superiority of IMS over LCC and
maintenance scheme of CBRP.
17 9253 denial of impedance for mobile cellular (edit ari)IAESIJEECS
Wireless network broadly utilized today incorporate, cell system, remote cross section system (WMNs), remote neighbourhood and individual zone system. The expanding interest for these systems has transformed range into a valuable asset. Consequently, there is dependably a requirement for techniques to pack more bits/Hz. In this paper, we list the purposes behind this far reaching doubt, and talk about how present and future patterns will expand the need and reasonability of multiuser collectors for both the uplink, where numerous offbeat clients will be all the while identified, and the downlink, where clients will be planned and generally orthogonal zed, yet the portable handset will in any case need to adapt to a couple of predominant meddling base stations. New results for impedance wiping out beneficiaries that utilization traditional front finishes are appeared to ease a large number of the deficiencies of earlier systems, especially for the testing uplink. This paper gives a diagram of key late research leaps forward on obstruction cancelation, and highlights framework level contemplations for future multiuser recipients.
Project Report on Modeling and Robust Control of Blu-Ray disc Servo MechanismsManu Mitra
This project deals with the modeling and the robust control of the next generation of optical disc drives servo-mechanisms. While in many industrial servo-control implementations, the radial and focus loops are considered as decoupled, e.g. DVD drives, this is no longer true for HD-DVD and Blu-ray disc (BD) formats which are more sensitive to opto-mechanical interactions at high frequencies. The impact of such phenomena on the robustness of the servo is evaluated by using experimental data, and an h∞ controller is designed to reduce the coupling effect, by using a suitable disturbance model into the problem formulation. Simulations using experimental data illustrate the performance improvement of the compensated system despite the parametric uncertainties in mass-production optical drives. (Aug 2009 - Dec 2009)
Optical waveguiding systems constructions and applicationseSAT Journals
Abstract
The basic geometry of a waveguide reflects its functions. These consist of wave simulation for information carriers, guiding and networking in the telecommunication industry, applying the laser guided modes in various research areas such as particle dispersion and randomization effect theories. The basic uitlity of a waveguiding system is determined by the optical efficiency of that system, which is the percentage ratio of effective transmission carried out by that particular waveguide. Advanced guiding networks consist of complex tubes with different alterations in their sizes in order to fulfill this requirement. As the industry grows, so does the demand for wave simulation techniques and thus, day by day new methods are being developed which focus on the development of effective wave propogation. Another important factor which is included in the designing of wave guiding devices is the frequency of the optical signal. A signal with significantly higher frequency bands will be guided through a complex system which in turn does not guide waves of lower frequency. Conventional designs have been consisting of the long hollow metallic tubes which guide the electromagnetic signals towards the receiving ends. However, slight deviation is being observed in the newly enhanced devicing.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Salwaar kameez or sarees initially came with simple patterns with very little innovations in patterns. Obviously, the designs and the embellishments dominated the entire attire, but when it came to cuts and draping style it was not that experimented. People were then satisfied with the entire look.
Average and Static Power Analysis of a 6T and 7T SRAM Bit-Cell at 180nm, 90nm...idescitation
A lot of consideration has been given to problems arising due to power dissipation.
Different ideas have been proposed by many researchers from the device level to the
architectural level and above. However, there is no universal way to avoid tradeoffs between
the power, delay and area. This is why; the designers are required to choose appropriate
techniques that satisfy application and product needs. Another important component of
power which contributes to power dissipation is Dynamic Power. This power is increasing
due to prolonged use of the electronic equipments. This is due to the fact that now-a-days
people are working on electronic systems from morning till night; it may be a mobile phone
or a laptop or any other equipment. This paper deals with the estimation of two components
of power i.e. static power (when device is in the standby mode) and the average power
(average amount of energy consumed with respect to time) of a 6T and 7T SRAM (Static
Random Access Memory) bit-cell at 180nm, 90nm, and 45nm CMOS Technology. This is
done in order to estimate the power required for a high speed operation of 6T and 7T
SRAM bit-cell.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
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Time and Low Power Operation Using Embedded Dram to Gain Cell Data RetentionIJMTST Journal
Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM because of their small size, non rationed operation, low static leakage, and two port functionality. But traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. The boosted levels require an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this paper, we present a novel, logic compatible, 3T GC-eDRAM bit cell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated in 0.25μm CMOS process targeted at low power, energy efficient application.
This paper presents a spin-transfer torque- magnetic
tunnel junction (STT-MTJ) based non-volatile 9-transistor
(9T) SRAM cell. The cell achieves low power dissipation due
to its series connected MTJ elements and read buffer which
offer stacking effect. The paper studies the impact of PVT
(process, voltage, and temperature) variations on the design
metric of the SRAM cell such as write delay and compares the
results with non-volatile 8T SRAM cell (NV8T). The proposed
design consumes lower leakage power and exhibits narrower
spread in write delay compared with NV8T.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
1. V. Partha Sarathi Reddy, Durga Prasad / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1485-1489
A New low power Technology for power reduction in SRAM’s using
Column Decoupling combined with virtual grounding
V. Partha Sarathi Reddy1, Durga Prasad2
1
(PG Student, ECE, JayaPrakash Narayan College of Engg./JNTU, India)
2
(Associate Professor, ECE, JayaPrakash Narayan College of Engg./JNTU, India)
Abstract: In this paper we are going to modify Particularly, it conflicts with the need to maintain a
the column decoupled SRAM for the purpose of high signal to noise ratio, or high noise margins, in
more reduced leakages than the existing type of SRAMs and is one of the major impediments to
designs as well as the new design which is producing a stable cell at low voltage. When
combined of virtual grounding with column combined with other effects such as narrow width
decoupling logic is compared with the existing effects, soft error rate (SER), temperature, and
technologies & the nanometer technology is also process variations and parasitic transistor resistance,
improved for the purpose of much improved the scaling of SRAMs becomes increasingly
reduction of area & power factors the difficult due to reduced margins [2]. Fig. 1
simulations were done using microwind & DSCH illustrates the saturation in the scaling trend (dashed
results. line) of SRAM cells across technology generations.
Keywords: Column Decoupled SRAM, DSCH, The plot indicates that the SRAM area scaling drops
Nanometer technology, Microwind, Virtual below 50% for 32-nm technology and beyond.
Grounding. Furthermore, voltage scaling is virtually nullified.
Higher fail probabilities occur due to voltage
I. Introduction: scaling, and low voltage operation is becoming
The main objective of this is to provide problematic as higher supply voltages are required
new low power solutions for Very Large Scale to conquer these process variations.
Integration (VLSI) designers. Especially, this work
focuses on the reduction of the power dissipation, To overcome these challenges, recent industry
which is showing an ever-increasing growth with trends have leaned towards exploring larger cells
the scaling down of the technologies. Various and more exotic SRAM circuit styles in scaled
technique sat the different levels of the design technologies. Examples are the use of write-assist
process have been implemented to reduce the power design [3], read-modify-write [4], read-assist
dissipation at the circuit, architectural and system designs [5], and the 8T register file cell.
level. Conventional 6T used in conjunction with these
techniques does not lead to power saving due to
exposure to half select condition Column
Low power has emerged as a principal theme in
select/half-select is very commonly used in SRAMs
today‟s electronics industry. The need for low
to provide SER protection and to enable area
power has caused a major paradigm shift where
efficient utilization and wiring of the macro.
power dissipation has become as important a
Nevertheless, the use of column select introduces a
consideration as performance and area. Two
read disturb condition for the unselected cells along
components determine the power consumption in a
a row (half-selected cells), potentially destabilizing
CMOS circuit.
them.
DEVICE miniaturization and the rapidly growing
demand for mobile or power-aware systems have
resulted in an urgent need to reduce power supply
voltage (Vdd). However, voltage reduction along
with device scaling is associated with decreasing
signal charge. Furthermore, increasing intra-die
process parameter variations, particularly random
dopant threshold voltage variations can lead to large
number of fails in extremely small channel area
memory designs. Due to their small size and large
numbers on chip, SRAM cells are adversely
affected. This trend is expected to grow significantly Fig1: Problem during operation in the SRAM‟s
as designs are scaled further with each technology
generation [1].
1485 | P a g e
2. V. Partha Sarathi Reddy, Durga Prasad / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1485-1489
II. Using 8T column decoupling logic design increase to the BL metal capacitance while
for this problem: maintaining the original diffusion capacitance
contributed by the 6T cell. Column decode signal
integrated with higher level metal. Area penalty can
be further reduced to 30% via use of 6T thin cell
integration. Further reduction can be achieved by
use of non-DRC clean devices.
The area can be reduced further to30% by utilizing
thin cells as presented in this paper without
degrading the bit line capacitance.
III. Concept of using Virtual Grounding:
SRAM is an important part of modern
microprocessor design, taking a large portion of the
total chip area and power. Increasing the density of
SRAM caches provides an effective method to
enhance system performance. That has resulted in
Fig2: SRAM with column Decoupling Logic
over 70% of the chip area being occupied by SRAM
[1]. Scaling device size doubled the transistor count
every two years according to Moore‟s law, and
Fig.2 illustrates a new 8T-CDC SRAM cell
hence the density of SRAM caches kept mounting
(inside dashed rectangle) with a gated wordline
every next generation. However device dimensions
which enables the decoupling of the column/half-
become too small in nano-scale technologies and are
select condition [5] hence eliminating half select
more prone to variations due to manufacturing
stability fails. A localized gated inverter consisting
process. These variations can disturb the read/write
of two additional transistors, T1 and T2, effectively
stability of a SRAM design causing reliability
perform a logical “AND” operation between the
problems. A conventional 6T-SRAM has a poor
column select signal (BDT0) and the decoded row,
read stability due to constraint design requirements,
or global word line, GWLE. The output of the
and can suffer functional failures due to high
inverter is the local wordline signal (LWLE0). The
threshold voltage variations.
local wordline is ON only when both the column
Statistical variability arising from the discreteness of
and row are selected (i.e., for fully selected cells
charge and matter is a major source of threshold
only); hence, as illustrated in the waveforms of Fig.
variation that degrades the reliability of
3, LWLE0 of the selected columned turns ON while
conventional SRAM design [2].
LWLE1 of the half-selected column remains low.
Conventionally device sizing is used to enhance the
This ensures that the local word line for only the
read stability of SRAM cell design. However
selected cells is activated, thereby effectively
conventional sizing can be ineffective in nano-
protecting the half-selected SRAM cells from the
scaled technologies due to large threshold variations
read disturb scenario that exists in 6T cell due to
[3, 4]. Different SRAM designs have previously
wordline sharing. Alternatively, it is possible to
been presented that use from 6 to 10 transistors to
swap the input and supply pairs of the gated
provide reliable and/or low power operation. Sub-
inverter; however this comes at the cost of extra
threshold (below 200 mV) [3] and low power [5]
delay stage and power. The advantages of the
6T-SRAM designs have been proposed, however the
8T-CDC cell are as follows: 1) conforming with
write speed for both is degraded due to single-sided
traditional 6T requirements in terms of (a) allowing
read/write. A low power 6TSRAM design was
the designer to integrate it in a column select
presented in [6] that provided an improvement by
fashion and (b) offering/maintaining SER protection
1/2 in access delay and reduced the write power by
while 2) maximizing array efficiency, 3) eliminating
1/10. However it did not improve noise margin and
the read disturb to the unselected cells, and 4)
required a negative voltage during a read operation
reducing power with simplification in peripheral
that degrades device reliability. A 7T-SRAM design
logic.
was presented for low voltage SNM free operation,
The two extra devices are integrated on top
but it suffered from dynamic retention [7]. Also the
of an existing 6T cell to allow for easy cell
write margin decreased at lower voltage, and read
mirroring and integration into an array topology.
operation could destroy cell data. Other designs
The addition of the two new transistors results in a
used 8 or 10 transistors to increase robustness [8, 9].
cell area increase of 40% (all in -direction). Through
However, they had a very high area overhead. For
the use of higher level metallurgy to wire in the
example, the 8T design incurred an area overhead of
column decode (BDC) signal, the growth to
30 %.
thedirection of cell was not impacted. The increase
to the –dimension of the cell causes a proportionate
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3. V. Partha Sarathi Reddy, Durga Prasad / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1485-1489
IV. Design of 7T-SRAM for enhanced ground (Gnd_vir2) is used to retrieve data on read
read stability bit line (BLR) during a read operation. Our design
A conventional 6TSRAM cell design decouples read/write operation using separate
consists of a cross-coupled inverter pair (M3-M6) read/write access transistors. Therefore it doesn‟t
that does data storage and two access transistors suffer from constrained read/write requirements as
(M1-M2) to load/retrieve data on bit lines, BL and in 6T-SRAM design.
BLB. During a write operation, the data is loaded on
the bit lines and the word select signal WS is turned V. Proposed Design & results using
high. A successful write operation occurs if the data Microwind& DSCH
is correctly latched in the cell. The bit lines are pre- Our idea is to combine these to different
charged to the supply voltage and the word select technologies & to design a new circuit with much
line is turned high to retrieve data during a read efficiency than the existing two designs. Thus we
operation. The bit line (BL) connected to the storage are designing a new circuit & showing the
node (V1) storing a „0‟ gets discharged. The storage simulation results of the different technologies as
node (V1) rises above „0‟ during a read operation shown below.
due to voltage division between the access transistor
(M1) and the driver transistor (M6). A read failure
can occur if the voltage drop rises higher than the
threshold voltage of the inverter (M3,M5).
1.1 Conventional 6T SRAM
1.2 Layout for Conventional 6T SRAM
A conventional 6T-SRAM cell provides
poor read stability since the access transistors
provide direct access to the cell storage during a
read operation. The proposed design (see Fig. 3)
removes the access hazard during a read operation
and therefore eliminates the chances of cell content 1.3. Characteristic waveform for Conventional 6T
being inadvertently flipped. It consists of a cross- SRAM
coupled pair (M3-M6) for data storage as in case of
a conventional 6T-SRAM cell. However the ground
terminal of the inverter pair is connected to a virtual
ground (Gnd_vir1) in the proposed design to
provide high speed low-power write operation. The
word select line „WS‟ is held high only during a
write operation to load new data in the cell by
turning on the write access transistors (M1-M2). A
read access transistor (M7) connected to a virtual
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4. V. Partha Sarathi Reddy, Durga Prasad / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1485-1489
2.1 8T SRAM Design 3.3 Characteristic waveform for Virtual Grounding
Embedded SRAM
2.2 8T SRAM layout
4.1 Our Proposed design combined with 8T &
Virtual grounding concept
2.3 Characteristic waveform for 8T SRAM
4.2 Our Proposed layout combined with 8T &
Virtual grounding concept
3.1 Virtual Grounding Embedded SRAM
4.3 Characteristic waveform for our proposed
layout combined with 8T & Virtual grounding
concept.
VI. Conclusion
Our proposed design shows that much less
3.2 Virtual Grounding Embedded SRAM layouts power than the existing ones. 1.76uw at the standard
Our Proposed layout combined with 8T & Virtual
grounding concept 50nm technology. And it is
having much reduced area than the conventional
SRAM designs. Thus this design can be used for
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5. V. Partha Sarathi Reddy, Durga Prasad / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1485-1489
future SRAM core memories.
References
[1] Kevin, Z., Embedded Memories for Nano-
Scale VLSIs. 2009: Springer Publishing
Company, Incorporated. 400.
[2] Brown, A.R., Roy, G., and Asenov, A.,
Poly-Si-Gate- Related Variability in
DecananometerMOSFETs With
Conventional Architecture. Electron
Devices, IEEE Transactions on, 2007.
54(11): p. 3056-3063.
[3] Bo, Z., et al. A Sub-200mV 6T SRAM in
0.13um CMOS. in Solid-State Circuits
Conference, 2007. ISSCC 2007. Digest of
Technical Papers. IEEE International.
2007.
[4] Cheng, B., Roy, S., Roy, G., Brown, A.,
and Asenov, A. Impact of Random Dopant
Fluctuation on Bulk CMOS 6-T SRAM
Scaling. inSolid-State Device Research
Conference, 2006. ESSDERC
2006.Proceeding of the 36th European.
2006.
[5] Jawar Singh, D.K.P., Simon Hollis, and
Saraju P. Mohanty, A single ended 6T
SRAM cell design for ultra-low-voltage
applications.IEICE Electronics Express,
2008.5(18): p. 750-755.
[6] Mizuno, H. and T. Nagano, Driving
source-line cell architecture for sub-1-V
high-speed low-power applications. Solid-
State Circuits, IEEE Journal of,
1996.31(4): p. 552-557.
[7] Takeda, K., et al., A read-static-noise-
margin-free SRAM cell for low-VDD and
high-speed applications. Solid-State
Circuits, IEEE Journal of, 2006.41(1): p.
113-121.
[8] Chang, L., et al., An 8T-SRAM for
Variability Tolerance and Low-Voltage
Operation in High-Performance
Caches.Solid-State Circuits, IEEE Journal
of, 2008.43(4): p. 956-963.
[9] Tae-Hyoung, K., et al. A High-Density
Subthreshold SRAM with Data-
Independent Bitline Leakage and Virtual
Ground Replica Scheme.inSolid-State
Circuits Conference, 2007. ISSCC 2007.
Digest of Technical Papers. IEEE
International. 2007.
[10] Wang, X., Roy, S., and Asenov, A., Impact
of Strain on the Performance of high-
k/metal replacement gate MOSFETs, in
Proc. 10th Ultimate Integration on Silicon
(ULIS 2009). 2009.
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