This is Paper solution of BCA 2016 According to JNVU sayllbus For more update connect with my facebookpage https://www.facebook.com/vgeducation7/

1. ALL THE BEST 1
BCA examination 2016
Computer System Architecture
Q.1 A.What is Instruction Cycle?
Ans: INSTRUCTION CYCLE
A program residing in the memory unit of the computer consists of a sequence of instructions. The
program is executed in the computer by going through a cycle for each instruction. Each instruction
cycle in turn is subdivided into a sequence of sub cycles or phases. In the basic computer each
instruction cycle consists or the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.
Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and execute the
next instruction. This process continues indefinitely unless a HALT instruction is encountered.
B. Compare Vectored and non-vectored interrupt?
Ans: For TRAP, RST 7.5, RST 6.5, RST 5.5 interrupts, the program is automatically transferred
to the ISS address without any external hardware .These interrupts for which hardware
automatically transfers the program to a specific memory location is known as Vector Interrupt.
When several I/O devices are connected to INTR interrupts line an external hardware is
used to interface I/O devices. This circuit generates RST-n codes to implement the multiple
interrupts schemes. These are not vector interrupts.
RST 7.5, RST 6.5, RST 5.5- RST 7.5, RST 6.5, RST 5.5 are mask able interrupts. They
are enable by software using instruction EI and SIM. SIM instruction enables or disable
according to the bit of accumulator.
C. What is IO interface ? how are these important?
Ans: Input - Output Interface
Input Output Interface provides a method for transferring information between internal storage
and external I/O devices. Peripherals connected to a computer need special communication links
for interfacing them with the central processing unit. The purpose of communication link is to
resolve the differences that exist between the central computer and each peripheral.
The Major Differences are:-
1. Peripherals are electro mechanical and electromagnetic devices and CPU and memory are
electronic devices. Therefore, a conversion of signal values may be needed.
2. The data transfer rate of peripherals is usually slower than the transfer rate of CPU and
consequently, a synchronization mechanism may be needed.
3. Data codes and formats in the peripherals differ from the word format in the CPU and
memory.
4. The operating modes of peripherals are different from each other and must be controlled so as
not to disturb the operation of other peripherals connected to the CPU.
D. Why are Read and Write control lines in DMA controller are bidirectional?
Ans: In CPU controller and DMA controller. The write and read control lines are “shared‟
between the DMA controller and CPU controller. they all have to be bidirectional .so we can say
that both the CPU controller and the DMA controller can control (active) these lines when
needed. on the other word also we can say that. These control lines running through the data

2. ALL THE BEST 2
buses and also having control signals, when a DMA controller places a Bus request input (BR) to
CPU and to take the control the over Buses.
E. How Many line of address bus must be used to access 2048 bytes of memory?
Ans :
G. Define the term operation code.
Ans: An opcode is the first byte of an instruction in machine language which tells the hardware
what operation needs to be performed with this instruction. Every processor/controller has its
own set of opcodes defined in its architecture. An opcode is followed by data like address,
values etc if needed.
H. Difference LDA and STA instructions.
Ans :
Q.2 What are Micro Operation? What are its various types? Illustrate the implementation
of each category of Micro Operation through its block diagram.
Ans: Micro Operation: A micro-operation is an elementary operation which is performed on
the data stored in registers. We can classify the micro-operations into four categories:
1. Register transfer: transfer binary information from one register to another.
2. Arithmetic: perform arithmetic operations on numeric data stored in registers.
3. Logic: perform bit manipulation operation on non-numeric data stored in registers.
4. Shift: perform shift operations on data stored in registers.
These micro-operations, transfer information from one register to another. It should be noted that
the information does not change during this micro-operation. A register transferred micro-
operation may be designed as:
R1 ¬ R2
This implies that transfer the content of register R2 to register R1. Since we expect the register
transfer to occur in a pre-determined control condition, the destination register should have a
parallel load capability. A common internal data bus of the processor is used for connecting

3. ALL THE BEST 3
various registers. In general, the size of this data bus should be equal to the number of bits in a
general register. There are some transfers which do not take place through the internal data bus,
but through the system bus. These transfers are related to memory and input/output modules.
Also the input/output operation is treated as a separate activity where normally a program and
therefore instructions are executed. Memory transfer is considered as the most important transfer
for instruction execution because it takes place at least once for every instruction.
Memory transfer can be achieved via a system bus. Since, the main memory is a random access
memory, therefore address of the location which is to be used is to be supplied. This address is
supplied by the CPU on the address bus. There are two memory transfer operations: Read and
Write.
MEMORY READ
1. Put memory address in the memory address register (MAR).
2. Read the data of the location. Generally this is achieved by putting the data in MAR on
address bus along with a memory read control signal on the control bus. The resultant of memory
read is put into the data bus which in turn stores the read data in the data register (DR). This
whole operation can be shown as:
DR ¬ M[MAR]
MEMORY WRITE
1. Put the desired memory address in memory address register (MAR) and the data to be written
in the data register (DR).
2. Write the data into the location: MAR puts the address on address bus and DR puts the data on
data bus to be written into the memory location addressed by MAR.
M [MAR] ¬ DR
Usually a memory read or write operation requires more clock cycles than a register transfer
operation.
Arithmetic Micro Operation:
These micro-operations perform some basic arithmetic operations on the numeric data
stored in the registers. These basic operations may be addition, subtraction, incrementing a
number, decrementing a number and arithmetic shift operation. An „add‟ micro-operation can be
specified as:
R3 ¬ R1 + R2
It implies: add the contents of registers R1 and R2 and store the sum in register R3.
The add operation mentioned above requires three registers along with the addition circuit in the
ALU. Subtraction, is implemented through complement and addition operation as:
R3 ¬ R1 – R2 is implemented as
R3 ¬ R1 + (2‟s complement of R2)
R3 ¬ R1 + (1‟s complement of R2 + 1)
R3 ¬ R1 + R2 + 1
An increment operation can be symbolized as:
R1 ¬ R1 + 1
while a decrement operation can be symbolized as:
R1 ¬ R1 – 1
We can implement increment and decrement operations by using a combinational circuit or
binary up/down counters. In most of the computers multiplication and division are implemented
using add/subtract and shift micro-operations. If a digital system has implemented division and
multiplication by means of combinational circuits then we can call these as the micro-operations
for that system. An arithmetic circuit is normally implemented using parallel adder circuits. Each
of the multiplexers (MUX) of the given circuit has two select inputs. This 4-bit circuit takes

4. ALL THE BEST 4
input of two 4-bit data values and a carry-in-bit and outputs the four resultant data bits and a
carry-out-bit. With the different input values we can obtain various micro operations. Equivalent
micro-operation Micro operation name
R ¬ R1 + R2 Add
R ¬ R1 + R2 +1 Add with carry
R ¬ R1 + R2 Subtract with borrow
R ¬ R1 + 2‟s Subtract
R ¬ R1 Transfer
R ¬R1 + 1 Increment
R ¬ R1 – 1 Decrement
Logical Micro Operation
These operations are performed on the binary data stored in the register. For a logic micro-
operation each bit of a register is treated as a separate variable.
For example, if R1 and R2 are 8 bits registers and
R1 contains 10010011 and
R2 contains 01010101
R1 AND R2 00010001
Some of the common logic micro-operations are AND, OR, NOT or complements. Exclusive
OR, NOR, NAND. We can have four possible combinations of input of two variables. These are
00, 01, 10 and 11. Now, for all these 4 input combination we can have 24 = 16 output
combinations of a function. This implies that for two variables we can have 16 logical
operations.
Shift Micro Operation
Shift micro operation can be used for serial transfer of data. They are used generally with the
arithmetic, logic, and other data-processing operations. The contents of a register can be shifted
to the left or the right. During a shift-right operation the serial input transfers a bit into the
leftmost position. The serial input transfers a bit into the rightmost position during a shift-left
operation. There are three types of shifts, logical, circular and arithmetic.
logical shift operation
A logical shift operation transfers 0 through the serial input. We use the symbols shl and shr for
logicalshift left and shift right micro operations, e.g.
R1 ¬ shl R1
R2 ¬ shr R2
are the two micro operations that specify a 1-bit shift left of the content of register R1 and a 1-
bit shift right of the content of register R2.
Circular Shift
The circular shift is also known as rotate operation. It circulates the bits of the register around the
two ends and there is no loss of information. This is accomplished by connecting the serial
output of the shift register to its serial input. We use the symbols cil and cir for the circular shift
left and circular shift right.
E.g. suppose Q1 register contains 01101101 then after cir operation, it contains 0110110 and
after cil operation it will contain 11011010.
Arithmetic Shift Micro Operation
An arithmetic shift micro operation shifts a signed binary number to the left or right. The effect
of an arithmetic shift left operation is to multiply the binary number by 2. Similarly an arithmetic
shift right divides the number by 2. Because the sign of the number must remain the same
arithmetic shift-right must leave the sign bit unchanged, when it is multiplied or divided by 2.
The left most bit in a register holds the sign bit, and the remaining bits hold the number. The sign

5. ALL THE BEST 5
bit is 0 for positive and 1 for negative. Negative numbers are in 2‟s complement form. Following
figure shows a typical register of n bits.
Sign bit Arithmetic shift right
Bit Rn-1 in the left most position holds the sign bit. Rn-2 is the most significant bit of the
number and R0 is the least significant bit. The arithmetic shift-right leaves the sign bit
unchanged and shifts the number (including the sign bits) to the right. Thus Rn-1 remains the
same, Rn-2 receives the bit from Rn-1, and so on for other bits in the register.
Q.3 a) What is the importance of timing control in the design of control unit?
Ans: TIMING AND CONTROL
The timing for all registers in the basic computer is controlled by a master clock generator.
The clock pulses are applied to all flip-flops and registers in the system, including the flip-flops
and registers in the control unit. The clock pulses do not change the state of a register unless the
register is enabled by a control signal. The control signals are generated in the control unit and
provide control inputs for the multiplexers in the common bus, control inputs in processor
registers, and micro operations or the accumulator.
There are two major types of control organization: hardwired control and micro
programmed control. in the hardwired organization, the control logic is implemented with gates,
flip-flops, decoders, and other digital circuits. It has the advantage that it can be optimized to
produce a fast mode of operation. In the micro programmed organization, the control information
is stored in a control memory. The control memory is programmed to initiate the required
sequence of micro operations. A hardwired control, as the name implies, requires changes in the
wiring among
the various components if the design has to be modified or changed. In the micro programmed
control, and required changes or modifications can be done by updating the micro program in
control memory. A hardwired control for the basic computer is presented in this section.
The block diagram of the control unit is shown in Fig. 3-2. It consists of two decoders, a
sequence counter, and a number of control logic gates. An instruction read from memory is
placed in the instruction register (IR): .The instruction register is shown again in Fig. 3.2 where it
is divided into three parts: the I. bit, the operation code, and bits 0 through 11. The operation
code in bits 12 through 14 are decoded with a 3 × 8 decoder. The eight outputs of the decoder are
designated by the symbols D0 through D7. The subscripted decimal number is equivalent to the
binary value of the corresponding operation code. Bits 15 of the instruction is transferred to a
flipflop designated by the symbol I. Bits 0 through 11 are applied to the control logic gates. The
4-bit sequence counter can count in binary from 0 through 15. The outputs of the counter are
decoded into 16 timing signals T0 through T15 . The internal logic of the control gates will be
derived later when we consider the design of the computer in detail.
The sequence counter SC can be incremented or cleared synchronously. Most of the time,
the counter is incremented to provide the sequence of timing signals out of the 4 × 16 decoder.
Once in a while, the counter is cleared to 0, causing the next active timing signal to be T0. As an
example, consider the case where SC is incremented to provide timing signals T0, T 1, T2, T3,
and T4 in sequence. At time T4, SC is cleared to 0 if decoder output D3 is active. This is
expressed symbolically by the statement
D3 T4: SC ← 0

6. ALL THE BEST 6
The timing diagram of Fig. 3-3 shows the time relationship of the control signals. The sequence
counter SC responds to the positive transition of the clock. Initially, the CLR input of SC is
active. The first positive transition of the
Figure 3-2 Control unit basic computer
Clock clears SC to 0, which in turn activates the timing signal T0 out of the decoder. T0 is
active during one clock cycle. The positive clock transition labeled T0 in the diagram will trigger
only those registers whose control inputs are connected to timing signal T0. SC is incremented
with every positive clock transition, unless its CLR input is active. This produces the sequence of
timing signals T0, T1, T2, T3, T4, and so on, as shown in the diagram (Note the relationship
between the timing signal and its corresponding positive clock transition.) If SC is not cleared,
the timing signals will continue with T5, T6, up to T15 and back to T0.

7. ALL THE BEST 7
Figure 3.3 Example of control timing signals
The last three waveforms in Fig 3.3 show how SC is cleared when D3T4 = 1. Output D3 from
the operation decoder becomes active at the end of timing signal T2 . When timing signal T4
becomes active, the output of the AND gate that implements the control function D3D4 becomes
active. This signal is applied to the CLR input of SC. On the next positive clock transition (the
one marked T4 in the diagram) the counter is cleared to 0. This causes the timing signal T0 to
become active instead of T5 that would have been active if SC were incremented instead of
cleared.
A memory read or write cycle will be initiated with the rising edge of a timing signal. It will be
assumed that a memory cycle time is less than the clock cycle time. According to this
assumption, a memory read or write cycle initiated by a timing signal will be completed by the
time the next clock gives through its positive transition. The clock transition will then be used to
load the memory word into a register. This timing relationship is not valid in many computers
because the memory cycle time is usually longer than the processor clock cycle. In such a case it
is necessary to provide wait cycles in the processor until the memory word is available. To
facilitate the presentation, we will assume that a wait period is not necessary in the basic
computer. To fully comprehend the operation of the computer, it is crucial that one understands
the timing relationship between the clock transition and the timing signals. For example, the
register transfer statement
T0: AR ← PC
specifies a transfer of the content of PC into AR if timing signal T0 is active during an entire
clock cycle interval. During this time the content of PC is placed onto the bus (with S2 S1 S0 =
10) and the LD (load) input of AR is enabled. The actual transfer does not occur until the end of
the clock cycle when the clock goes through a positive transition. This same positive clock
transition increments the sequence counter SC from 0000 to 0001. The next clock cycle has T1
active and T0 inactive.
Q.3 b) Explain all peripheral devices and write about each of them.
Ans: Peripheral devices
 In addition to the processor and a set of memory modules, the third key element of a
computer system is a set of input-output subsystem referred to as I/O, provides an
efficient mode of communication between the central system and the outside
environment.
 Programs and data must be entered into computer memory for processing and results
obtained from computations must be recorded or displayed for the user.
 Devices that are under the direct control of the computer are said to be connected on-line.
These devices are designed to read information into or out of the memory unit upon
command from CPU.
 Input or output devices attached to the computer are also called peripherals.
 Among the most common peripherals are keyboards, display units, and printers.
 Perhaps those provide auxiliary storage for the systems are magnetic disks and tapes.
 Peripherals are electromechanical and electromagnetic devices of some complexity.
 We can broadly classify peripheral devices into three categories:
 Human Readable: Communicating with the computer users, e.g. video display
terminal, printers etc.

8. ALL THE BEST 8
 Machine Readable: Communicating with equipments, e.g. magnetic disk, magnetic
tape, sensor, actuators used in robotics etc.
 Communication: Communicating with remote devices means exchanging data with
that, e.g. modem, NIC (network interface Card) etc.
Fig: Block diagram
of Peripheral device
 Control signals determine the
function that the device will perform such as send data to I/O module, accept data from I/O
module.
 Status signals indicate the state of the device i.e. device is ready or not.
 Data bits are actual data transformation.
 Control logic associated with the device controls the device's operation in response to
direction from the I/O module.
 The transducer converts data from electrical to other forms of energy during output and from
other forms to electrical during input.
 Buffer is associated with the transducer to temporarily hold data being transferred between
the I/O module and external devices i.e. peripheral environment.
Q4. a) What is the difference between isolated I/O and memory mapped I/O ?
Also ,explain the advantages and disadvantages of each.
Ans : Isolated I/O versus Memory Mapped I/O
 Isolated I/O
 Separate I/O read/write control lines in addition to memory read/write control lines
 Separate (isolated) memory and I/O address spaces
 Distinct input and output instructions
 Memory-mapped I/O
 A single set of read/write control lines (no distinction between memory and I/O
transfer)
 Memory and I/O addresses share the common address space which reduces memory
address range available
 No specific input or output instruction so the same memory reference instructions
can be used for I/O transfers
 Considerable flexibility in handling I/O operations

9. ALL THE BEST 9
Q.4 b) What are the Addressing modes? Discuss different types of addressing
modes?
Ans: Addressing mode refers to the specification of the location of data required by an
operation • Pentium supports three fundamental addressing modes: ∗ Register mode ∗ Immediate
mode ∗ Memory mode • Specification of operands located in memory can be done in a variety of
ways ∗ Mainly to support high-level language constructs and data structures
The operation field of an instruction specifies the operation to be performed. This
operation must be executed on some data stored in computer registers or memory words. The
way the operands are chosen during program execution in dependent on the addressing mode of
the instruction. The addressing mode of the instruction. The addressing mode specifies a rule for
interpreting or modifying the address field of the instruction before the operand is actually
referenced. Computers use addressing mode techniques for the purpose of accommodating one
or both of the following provisions:
1 To give programming versatility to the user by providing such facilities as pointers to
Memory, counters for loop control, indexing of data, and program relocation
2 To reduce the number of bits in the addressing field of the instruction.
3 The availability of the addressing modes gives the experienced assembly language
programmer flexibility for writing programs that are more efficient with respect to the
number of instructions and execution time.
Although most addressing modes modify the address field of the instruction, there are two
modes that need no address field at all. These are the implied and immediate modes.
1 Implied Mode: In this mode the operands are specified implicitly in the definition of
theinstruction. For example, the instruction “complement accumulator” is an implied-mode
instruction because the operand in the accumulator register is implied in the definition of the
instruction. In fact, all register reference instructions that sue an accumulator are implied-mode
instructions. Figure 1: Instruction format with mode field Zero-address instructions in a stack-
organized computer are implied-mode instructions since the operands are implied to be on top of
the stack.
2 Immediate Mode: In this mode the operand is specified in the instruction itself. Inother
words, an immediate mode instruction has an operand field rather than an address field. The
operand field contains the actual operand to be used in conjunction with the operation specified
in the instruction. Immediate-mode instructions are useful for initializing registers to a constant
value. It was mentioned previously that the address field of an instruction may specify either a
memory word or a processor register. When the address field specifies a processor register, the
instruction is said to be in the register mode.
3 Register Mode: In this mode the operands are in registers that reside within the CPU.The
particular register is selected from a register field in the instruction. A k-bit field can specify any
one of 2k registers.
4 Register Indirect Mode: In this mode the instruction specifies a register in the CPUwhose
contents give the address of the operand in memory. In other words, the selected register
contains the address of the operand rather than the
5 Auto increment or Auto decrement Mode: This is similar to the register indirect
modeexcept that the register is incremented or decremented after (or before) its value is used to

10. ALL THE BEST 10
access memory. When the address stored in the register refers to a table of data in memory, it is
necessary to increment or decrement the register after every access to the table. This can be
achieved by using the increment or decrement instruction. However, because it is such a
common requirement, some computers incorporate a special mode that automatically increments
or decrements the content of the register after data access. The address field of an instruction is
used by the control unit in the CPU to obtain the operand from memory. Sometimes the value
given in the address field is the address of the operand, but sometimes it is just an address from
which the address of the operand is calculated. To differentiate among the various addressing
modes it is necessary to distinguish between the address part of the instruction and the effective
address used by the control when executing the instruction. The effective address is defined to be
the memory address obtained from the computation dictated by the given addressing mode. The
effective address is the address of the operand in a computational-type instruction. It is the
address where control branches in response to a branch-type instruction. We have already
defined two addressing modes in previous chapter.
6 Direct Address Mode: In this mode the effective address is equal to the address part ofthe
instruction. The operand resides in memory and its address is given directly by the address field
of the instruction. In a branch-type instruction the address field specifies the actual branch
address.
7 Indirect Address Mode: In this mode the address field of the instruction gives theaddress
where the effective address is stored in memory. Control fetches the instruction from memory
and uses its address part to access memory again to read the effective address.
8 Relative Address Mode: In this mode the content of the program counter is added to
theaddress part of the instruction in order to obtain the effective address. The address part of the
instruction is usually a signed number (in 2‟s complement representation) which can be either
positive or negative. When this number is added to the content of the program counter, the result
produces an effective address whose position in memory is relative to the address of the next
instruction. To clarify with an example, assume that the program counter contains the number
825 and the address part of the instruction contains the number 24. The instruction at location
825 is read from memory during the fetch phase and the program counter is then incremented by
one to 826 + 24 = 850. This is 24 memory locations forward from the address of the next
instruction. Relative addressing is often used with branch-type instructions when the branch
address is in the area surrounding the instruction word itself. It results in a shorter address field
in the instruction format since the relative address can be specified with a smaller number of bits
compared to the number of bits required to designate the entire memory address.
9 Indexed Addressing Mode: In this mode the content of an index register is added to the
address part of the instruction to obtain the effective address. The index register is a special CPU
register that contains an index value. The address field of the instruction defines the beginning
address of a data array in memory. Each operand in the array is stored in memory relative to the
beginning address. The distance between the beginning address and the address of the operand is
the index value stores in the index register. Any operand in the array can be accessed with the
same instruction provided that the index register contains the correct index value. The index
register can be incremented to facilitate access to consecutive operands. Note that if an index-
type instruction does not include an address field in its format, the instruction converts to the
register indirect mode of operation. Some computers dedicate one CPU register to function
solely as an index register. This register is involved implicitly when the index-mode instruction

11. ALL THE BEST 11
is used. In computers with many processor registers, any one of the CPU registers can contain
the index number. In such a case the register must be specified explicitly in a register field within
the instruction format.
10 Base Register Addressing Mode: In this mode the content of a base register is added to the
address part of the instruction to obtain the effective address. This is similar to the indexed
addressing mode except that the register is now called a base register instead of an index register.
The difference between the two modes is in the way they are used rather than in the way that
they are computed. An index register is assumed to hold an index number that is relative to the
address part of the instruction. A base register is assumed to hold a base address and the address
field of the instruction gives a displacement relative to this base address. The base register
addressing mode is used in computers to facilitate the relocation of programs in memory. When
programs and data are moved from one segment of memory to another, as required in
multiprogramming systems, the address values of the base register requires updating to reflect
the beginning of a new memory segment.
Q.5 Explain the followings
a)ALU Design
b)Instruction Format
Ans: a)ALU Design:
ALU is the combinational circuit of that part of computer that actually performs
arithmetic and logical operations on data. All of the other elements of computer system- control
unit, registers, memory, I/O are their mainly to bring data into the ALU for it to process and then
to take the result back out. An ALU & indeed all electronic components in computer are based
on the use of simple digital logic device that can store binary digit and perform simple Boolean
logic function. Figure indicates in general in general term how ALU is interconnected with rest
of the processor.
Data are presented to ALU in register
and the result of operation is stored in
register. These registers are temporarily
storage location within the processor that
are connected by signal path to the ALU.
The ALU may also set flags as the result
of an operation. The flags values are also
stored in registers within the processor. The control unit provides signals that control the
operation of ALU and the movement of data into an out of ALU.
The design of ALU has three stages.
1. Design the arithmetic section
The basic component of arithmetic circuit is a parallel adder which is constructed with a number
of full adder circuits connected in cascade. By controlling the data inputs to the parallel adder, it
is possible to obtain different types of arithmetic operations. Below figure shows the arithmetic
circuit and its functional table.

12. ALL THE BEST 12
2. Design the logical section
The basic components of logical circuit are AND,
OR, XOR and NOT gate circuits connected
accordingly. Below figure shows a circuit that
generates four basic logic micro-operations. It
consists of four gates and a multiplexer. Each of four
logic operations is generated through a gate that
performs the required logic. The two selection input
S1 and S0 choose one of the data inputs of the
multiplexer and directs its value to the output. Functional table lists the logic operations.
b)Instruction Format: The computer can be used to perform a specific task, only by
specifying the necessary steps to complete the task. The collection of such ordered steps forms a
„program‟ of a computer. These ordered steps are the instructions. Computer instructions are
stored in central memory locations and are executed sequentially one at a time. The control reads
an instruction from a specific address in memory and executes it. It then continues by reading the
next instruction in sequence and executes it until the completion of the program.
A computer usually has a variety of Instruction Code Formats. It is the function of the
control unit within the CPU to interpret each instruction code and provide the necessary control
functions needed to process the instruction. An n bit instruction that k bits in the address field
and m bits in the operation code field come addressed 2k location directly and specify 2m
different operation. 
 The bits of the instruction are divided into groups called fields.
 The most common fields in instruction formats are:
 An Operation code field that specifies the operation to be performed.
 An Address field that designates a memory address or a processor register.
 A Mode field that specifies the way the operand or the effective address is determined.
The operation code field (Opcode) of an instruction is a group of bits that define various
processor operations such as add, subtract, complement, shift etcetera. The bits that define the
mode field of an instruction code specify a variety of alternatives for choosing the operands from
the given address. Operation specified by an instruction is executed on some data stored in the
processor register or in the memory location. Operands residing in memory are specified by their
memory address. Operands residing in processor register are specified with a register address.
Types of Instruction
 Computers may have instructions of several different lengths containing varying number
of addresses.

13. ALL THE BEST 13
 The number of address fields in the instruction format of a computer depends on the
internal organization of its registers.
 Most computers fall into one of 3 types of CPU organizations:
1.Single accumulator organization:- All the operations are performed with an accumulator
register. The instruction format in this type of computer uses one address field. For example:
ADD X, where X is the address of the operands .
2.General register organization:- The instruction format in this type of computer needs three
register address fields. For example: ADD R1,R2,R3
3.Stack organization:- The instruction in a stack computer consists of an operation code with no
address field. This operation has the effect of popping the 2 top numbers from the stack,
operating the numbers and pushing the sum into the stack. For example: ADD
Q.6 a) Illustrate the influence of number of address on X=(R+S)(U+V) using three
address, Two address and Zero address instruction.
Q.6 b) What do you understand by an instruction set ? what are different types of
instructions? Discuss the significance of each type of Instruction .
Ans: Instruction set: An instruction set is a group of commands for a CPU in machine
language. The term can refer to all possible instructions for a CPU or a subset of
instructions to enhance its performance in certain situations.
All CPUs have instruction sets that enable commands to the processor directing
the CPU to switch the relevant transistors. Some instructions are simple read, write and
move commands that direct data to different hardware.
In CISC (Complex Instruction Set Computer) processors there is also a microcode
layer, which involves programmable instructions stored in fast memory that may be
updated.
The RISC (Reduced Instruction Set Computer) architecture, on the other hand,
has hard-wired control; it does not require microcode but has a greater base instruction
set.
Enhancement instruction sets are more familiar to users as they have often been
used in marketing a given CPU. Examples of this go back to the Pentium 166Mhz with
MMX technologies marketed for enhancing Intel CPU multimedia performance.
Depending on operation they perform, all instructions are divided in several groups:
 Arithmetic Instructions
 Branch Instructions
 Data Transfer Instructions
 Logic Instructions
 Bit-oriented Instructions
 Control Instruction

14. ALL THE BEST 14
The first part of each instruction, called MNEMONIC refers to the operation an instruction
performs (copy, addition, logic operation etc.). Mnemonics are abbreviations of the name of
operation being executed.
Arithmetic instructions
Arithmetic instructions perform several basic operations such as addition, subtraction, division,
multiplication etc. After execution, the result is stored in the first operand. For example: ADD
A,R1 - The result of addition (A+R1) will be stored in the accumulator.
Opcode Operand Explanation of
Instruction
Description
ADD R
M
Add register or
memory, to
accumulator
The contents of the operand (register or
memory) are added to the contents of the
accumulator and the result is stored in the
accumulator. If the operand is a memory location,
its location is specified by the contents of the HL
registers. All flags are modified to reflect the
result of the addition.
Example: ADD B or ADD M
ADC R
M
Add register to
accumulator
with carry
The contents of the operand (register or
memory) and M the Carry flag are added to the
contents of the accumulator and the result is
stored in the accumulator. If the operand is a
memory location, its location is specified by the
contents of the HL registers. All flags are
modified to reflect the result of the addition.
Example: ADC B or ADC M
ADI 8-bit data Add immediate
to accumulator
The 8-bit data (operand) is added to the contents
of the accumulator and the result is stored in the
accumulator. All flags are modified to reflect the
result of the addition.
Example: ADI 45H
ACI 8-bit data Add immediate
to accumulator
with carry
The 8-bit data (operand) and the Carry flag are
added to the contents of the accumulator and
the result is stored in the accumulator. All flags
are modified to reflect the result of the addition.
Example: ACI 45H
LXI Reg. pair, Load register The instruction loads 16-bit data in the register

15. ALL THE BEST 15
16-bit
data
pair immediate pair designated in the operand.
Example: LXI H, 2034H or LXI H, XYZ
DAD Reg. pair Add register pair
to H and L
registers
The 16-bit contents of the specified register pair
are added to the contents of the HL register and
the sum is stored in the HL register. The contents
of the source register pair are not altered. If the
result is larger than 16 bits, the CY flag is set. No
other flags are affected.
Example: DAD H
SUB R
M
Subtract register
or memory from
accumulator
The contents of the operand (register or memory
) are subtracted from the contents of the
accumulator, and the result is stored in the
accumulator. If the operand is a memory location,
its location is specified by the contents of the HL
registers. All flags are modified to reflect the
result of the subtraction.
Example: SUB B or SUB M
SBB R
M
Subtract source
and borrow from
accumulator
The contents of the operand (register or memory
) and M the Borrow flag are subtracted from the
contents of the accumulator and the result is
placed in the accumulator. If the operand is a
memory location, its location is specified by the
contents of the HL registers. All flags are
modified to reflect the result of the subtraction.
Example: SBB B or SBB M
SUI 8-bit data Subtract
immediate from
accumulator
The 8-bit data (operand) is subtracted from the
contents of the accumulator and the result is
stored in the accumulator. All flags are modified
to reflect the result of the subtraction.
Example: SUI 45H
SBI 8-bit data Subtract
immediate from
accumulator
with borrow
The contents of register H are exchanged with
the contents of register D, and the contents of
register L are exchanged with the contents of
register E.
Example: XCHG

16. ALL THE BEST 16
INR R
M
Increment
register or
memory by 1
The contents of the designated register or
memory) are incremented by 1 and the result is
stored in the same place. If the operand is a
memory location, its location is specified by the
contents of the HL registers.
Example: INR B or INR M
INX R Increment
register pair by 1
The contents of the designated register pair are
incremented by 1 and the result is stored in the
same place.
Example: INX H
DCR R
M
Decrement
register or
memory by 1
The contents of the designated register or
memory are M decremented by 1 and the result
is stored in the same place. If the operand is a
memory location, its location is specified by the
contents of the HL registers.
Example: DCR B or DCR M
DCX R Decrement
register pair by 1
The contents of the designated register pair are
decremented by 1 and the result is stored in the
same place.
Example: DCX H
DAA none Decimal adjust
accumulator
The contents of the accumulator are changed
from a binary value to two 4-bit binary coded
decimal (BCD) digits. This is the only instruction
that uses the auxiliary flag to perform the binary
to BCD conversion, and the conversion procedure
is described below. S, Z, AC, P, CY flags are
altered to reflect the results of the operation.
If the value of the low-order 4-bits in the
accumulator is greater than 9 or if AC flag is set,
the instruction adds 6 to the low-order four bits.
If the value of the high-order 4-bits in the
accumulator is greater than 9 or if the Carry flag
is set, the instruction adds 6 to the high-order
four bits.
Example: DAA

17. ALL THE BEST 17
Branch Instructions
There are two kinds of branch instructions: Unconditional jump instructions: upon their
execution a jump to a new location from where the program continues execution is executed.
Conditional jump instructions: a jump to a new program location is executed only if a specified
condition is met. Otherwise, the program normally proceeds with the next instruction.
Opcode Operand Explanation
of Instruction
Description
JMP 16-bit
address
Jump
unconditionally
The program
sequence is
transferred to the
memory location
specified by the
16-bit address
given in the
operand.
Example: JMP
2034H or JMP XYZ
Opcode Description
Flag
Status
JC Jump on Carry CY = 1
JNC Jump on no Carry CY = 0
JP Jump on positive S = 0
JM Jump on minus S = 1
JZ Jump on zero Z = 1
JNZ Jump on no zero Z = 0
JPE
Jump on parity
even
P = 1
JPO Jump on parity odd P = 0
16-bit
address
Jump
conditionally
The program
sequence is
transferred to the
memory location
specified by the
16-bit address
given in the
operand based on
the specified flag
of the PSW as
described below.
Example: JZ 2034H
or JZ XYZ
Opcode Description Flag Status
CC Call on Carry CY = 1
CNC Call on no Carry CY = 0
CP Call on positive S = 0
16-bit
address
Unconditional
subroutine call
The program
sequence is
transferred to the
memory location
specified by the

18. ALL THE BEST 18
CM Call on minus S = 1
CZ Call on zero Z = 1
CNZ Call on no zero Z = 0
CPE Call on parity even P = 1
CPO Call on parity odd P = 0
16-bit address
given in the
operand. Before
the transfer, the
address of the next
instruction after
CALL (the contents
of the program
counter) is pushed
onto the stack.
Example: CALL
2034H or CALL XYZ
RET none Return from
subroutine
unconditionally
The program
sequence is
transferred from
the subroutine to
the calling
program. The two
bytes from the top
of the stack are
copied into the
program
counter,and
program execution
begins at the new
address.
Example: RET
Opcode Description
Flag
Status
RC Return on Carry CY = 1
RNC Return on no Carry CY = 0
RP Return on positive S = 0
RM Return on minus S = 1
RZ Return on zero Z = 1
RNZ Return on no zero Z = 0
RPE
Return on parity
even
P = 1
none Return from
subroutine
conditionally
The program
sequence is
transferred from
the subroutine to
the calling
program based on
the specified flag
of the PSW as
described below.
The two bytes from
the top of the stack

19. ALL THE BEST 19
RPO
Return on parity
odd
P = 0
are copied into the
program counter,
and program
execution begins at
the new address.
Example: RZ
PCHL none Load program
counter with
HL contents
The contents of
registers H and L
are copied into the
program counter.
The contents of H
are placed as the
high-order byte
and the contents
of L as the low-
order byte.
Example: PCHL
RST 0-7 Restart The RST instruction
is equivalent to a
1-byte call
instruction to one
of eight memory
locations
depending upon
the number. The
instructions are
generally used in
conjunction with
interrupts and
inserted using
external hardware.
However these can
be used as
software
instructions in a
program to
transfer program
execution to one of

20. ALL THE BEST 20
the eight locations.
The addresses are:
Instruction
Restart
Address
RST 0 0000H
RST1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
The 8085 has four
additional
interrupts and
these interrupts
generate RST
instructions
internally and thus
do not require any
external hardware.
These instructions
and their Restart
addresses are:
Interrupt
Restart
Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH
Data Transfer Instructions

21. ALL THE BEST 21
Data transfer instructions move the content of one register to another. The register the
content of which is moved remains unchanged. If they have the suffix “X” (MOVX), the data
is exchanged with external memory.
opcode Operand Explanation of
Instruction
Description
MOV Rd, Rs
M, Rs
Rd, M
Copy from source(Rs)
to destination(Rd)
This instruction copies the contents
of the source register into the
destination register; the contents of
the source register are not altered. If
one of the operands is a memory
location, its location is specified by
the contents of the HL registers.
Example: MOV B, C or MOV B, M
MVI Rd, data
M, data
Move immediate 8-bit The 8-bit data is stored in the
destination register or memory. If
the operand is a memory location, its
location is specified by the contents
of the HL registers.
Example: MVI B, 57H or MVI M,
57H
LDA 16-bit
address
Load accumulator The contents of a memory location,
specified by a 16-bit address in the
operand, are copied to the
accumulator. The contents of the
source are not altered.
Example: LDA 2034H
LDAX B/D Reg.
pair
Load accumulator
indirect
The contents of the designated
register pair point to a memory
location. This instruction copies the
contents of that memory location
into the accumulator. The contents
of either the register pair or the
memory location are not altered.
Example: LDAX B

22. ALL THE BEST 22
LXI Reg. pair,
16-bit data
Load register pair
immediate
The instruction loads 16-bit data in
the register pair designated in the
operand.
Example: LXI H, 2034H or LXI H,
XYZ
LHLD 16-bit
address
Load H and L registers
direct
The instruction copies the contents
of the memory location pointed out
by the 16-bit address into register L
and copies the contents of the next
memory location into register H. The
contents of source memory locations
are not altered.
Example: LHLD 2040H
STA 16-bit
address
16-bit address The contents of the accumulator are
copied into the memory location
specified by the operand. This is a 3-
byte instruction, the second byte
specifies the low-order address and
the third byte specifies the high-
order address.
Example: STA 4350H
STAX Reg. pair Store accumulator
indirect
The contents of the accumulator are
copied into the memory location
specified by the contents of the
operand (register pair). The contents
of the accumulator are not altered.
Example: STAX B
SHLD 16-bit
address
Store H and L registers
direct
The contents of register L are stored
into the memory location specified
by the 16-bit address in the operand
and the contents of H register are
stored into the next memory
location by incrementing the
operand. The contents of registers
HL are not altered. This is a 3-byte

23. ALL THE BEST 23
instruction, the second byte specifies
the low-order address and the third
byte specifies the high-order
address.
Example: SHLD 2470H
XCHG none Exchange H and L with
D and E
The contents of register H are
exchanged with the contents of
register D, and the contents of
register L are exchanged with the
contents of register E.
Example: XCHG
SPHL none Copy H and L registers
to the stack pointer
The instruction loads the contents of
the H and L registers into
the stack pointer register, the
contents of the H register provide
the high-order address and the
contents of the L register provide the
low-order address. The contents of
the H
and L registers are not altered.
Example: SPHL
XTHL none Exchange H and L with
top of stack
The contents of the L register are
exchanged with the stack location
pointed out by the contents of the
stack pointer register. The contents
of the H register are exchanged with
the next stack location (SP+1);
however, the contents of the stack
pointer register are not altered.
Example: XTHL
PUSH Reg. pair Push register pair onto
stack
The contents of the register pair
designated in the operand are
copied onto the stack in the
following sequence. The stack
pointer register is decremented and

24. ALL THE BEST 24
the contents of the highorder
register (B, D, H, A) are copied into
that location. The stack pointer
register is decremented again and
the contents of the low-order
register (C, E, L, flags) are copied to
that location.
Example: PUSH B or PUSH A
POP Reg. pair Pop off stack to
register pair
The contents of the memory location
pointed out by the stack pointer
register are copied to the low-order
register (C, E, L, status flags) of the
operand. The stack pointer is
incremented by 1 and the contents
of that memory location are copied
to the high-order register (B, D, H, A)
of the operand. The stack pointer
register is again incremented by 1.
Example: POP H or POP A
OUT 8-bit port
address
Output data from
accumulator to a port
with 8-bit address
The contents of the accumulator are
copied into the I/O port specified by
the operand.
Example: OUT F8H
IN 8-bit port
address
Input data to
accumulator from a
port with 8-bit address
The contents of the input port
designated in the operand are read
and loaded into the accumulator.
Example: IN 8CH
Logic Instructions
Logic instructions perform logic operations upon corresponding bits of two registers. After
execution, the result is stored in the first operand.

25. ALL THE BEST 25
Opcode Operand Explanation of
Instruction
Description
CMP R
M
Compare
register or
memory with
accumulator
The contents of the operand (register or
memory) are M compared with the contents of
the accumulator. Both contents are preserved .
The result of the comparison is shown by setting
the flags of the PSW as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
Example: CMP B or CMP M
CPI 8-bit
data
Compare
immediate with
accumulator
The second byte (8-bit data) is compared with
the contents of the accumulator. The values
being compared remain unchanged. The result of
the comparison is shown by setting the flags of
the PSW as follows:
if (A) < data: carry flag is set
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H
ANA R
M
Logical AND
register or
memory with
accumulator
The contents of the accumulator are logically
ANDed with M the contents of the operand
(register or memory), and the result is placed in
the accumulator. If the operand is a memory
location, its address is specified by the contents
of HL registers. S, Z, P are modified to reflect the
result of the operation. CY is reset. AC is set.
Example: ANA B or ANA M
ANI 8-bit
data
Logical AND
immediate with
accumulator
The contents of the accumulator are logically
ANDed with the
8-bit data (operand) and the result is placed in
the
accumulator. S, Z, P are modified to reflect the
result of the

26. ALL THE BEST 26
operation. CY is reset. AC is set.
Example: ANI 86H
XRA R
M
Exclusive OR
register or
memory with
accumulator
The contents of the accumulator are Exclusive
ORed with M the contents of the operand
(register or memory), and the result is placed in
the accumulator. If the operand is a memory
location, its address is specified by the contents
of HL registers. S, Z, P are modified to reflect the
result of the operation. CY and AC are reset.
Example: XRA B or XRA M
XRI 8-bit
data
Exclusive OR
immediate with
accumulator
The contents of the accumulator are Exclusive
ORed with the 8-bit data (operand) and the result
is placed in the accumulator. S, Z, P are modified
to reflect the result of the operation. CY and AC
are reset.
Example: XRI 86H
ORA R
M
Logical OR
register or
memory with
accumulator
The contents of the accumulator are logically
ORed with M the contents of the operand
(register or memory), and the result is placed in
the accumulator. If the operand is a memory
location, its address is specified by the contents
of HL registers. S, Z, P are modified to reflect the
result of the operation. CY and AC are reset.
Example: ORA B or ORA M
ORI 8-bit
data
Logical OR
immediate with
accumulator
The contents of the accumulator are logically
ORed with the 8-bit data (operand) and the result
is placed in the accumulator. S, Z, P are modified
to reflect the result of the operation. CY and AC
are reset.
Example: ORI 86H
RLC none Rotate
accumulator
left
Each binary bit of the accumulator is rotated left
by one position. Bit D7 is placed in the position
of D0 as well as in the Carry flag. CY is modified

27. ALL THE BEST 27
according to bit D7. S, Z, P, AC are not affected.
Example: RLC
RRC none Rotate
accumulator
right
Each binary bit of the accumulator is rotated right
by one position. Bit D0 is placed in the position
of D7 as well as in the Carry flag. CY is modified
according to bit D0. S, Z, P, AC are not affected.
Example: RRC
Bit-oriented Instructions
Similar to logic instructions, bit-oriented instructions perform logic operations. The
difference is that these are performed upon single bits.
BIT-ORIENTED INSTRUCTIONS
Mnemonic Description Byte Cycle
CLR C Clears the carry flag 1 1
CLR bit Clears the direct bit 2 3
SETB C Sets the carry flag 1 1
SETB bit Sets the direct bit 2 3
CPL C
Complements the carry
flag
1 1
Control Instruction:
Opcode Operand Explanation
of Instruction
Description
NOP none No operation No operation is performed. The instruction is
fetched and decoded. However no operation is
executed.

28. ALL THE BEST 28
Example: NOP
HLT none Halt and enter
wait state
The CPU finishes executing the current instruction
and halts any further execution. An interrupt or
reset is necessary to exit from the halt state.
Example: HLT
DI none Disable
interrupts
The interrupt enable flip-flop is reset and all the
interrupts except the TRAP are disabled. No flags
are affected.
Example: DI
EI none Enable
interrupts
The interrupt enable flip-flop is set and all
interrupts are enabled. No flags are affected. After
a system reset or the acknowledgement of an
interrupt, the interrupt enable flipflop is reset,
thus disabling the interrupts. This instruction is
necessary to reenable the interrupts (except
TRAP).
Example: EI
RIM none Read interrupt
mas
This is a multipurpose instruction used to read the
status of interrupts 7.5, 6.5, 5.5 and read serial
data input bit. The instruction loads eight bits in
the accumulator with the following
interpretations.
Example: RIM
SIM none Set interrupt
mask
This is a multipurpose instruction and used to
implement the 8085 interrupts 7.5, 6.5, 5.5, and
serial data output. The instruction interprets the
accumulator contents as follows.
Example: SIM

29. ALL THE BEST 29
Q. 7 Write a assembly Program to find Largest in Three numbers.
Ans:
Label Instruction Comments
MVI A, 06H ; Loads Accumulator with 06H
MVI B, 0AH ; Loads register B with 0AH
MVI C, 0BH ; Loads register C with 0BH
CMP B ; Compares B with A
JNC jump1: ; On no carry jumps to jump1:
MOV A, B ; Moves content of B to A
jump1: CMP C ; Compares C with A
JNC jump2: ; On no carry jumps to jump2:
MOV A, C ; Moves content of C to A
jump2: STA 4200H ; Stores content of A to memory location 4200H
HLT ; Terminates the program
Algorithm
Step 1: Load Accumulator (A) with value1
Step 2: Load register B with value2
Step 3: Load register C with value3
Step 4: Compare B with A, gives carry if value2 is greater than value1 (i.e. B>A)
Step 5: When no carry from Step 4: go to Step 7: (i.e. when A>B)
Step 6: Move content of register B to A (i.e. when B>A)
Step 7: Compare C with A, gives carry if value3 is greater than value1 (i.e. C>A)
Step 8: When no carry from Step 7: go to Step10: (i.e. when A>C)
Step 9: Move content of register C to A (i.e. when C>A)
Step 10: Store content of Accumulator to memory location 4200H
Step 11: Terminate the program
Q.8 Write Short notes on :

30. ALL THE BEST 30
a) Direct Memory Access(DMA)
b) 8085 architecture
Ans: a) Direct Memory Access(DMA): Direct memory access (DMA) is a method that
allows an input/output (I/O) device to send or receive data directly to or from the main memory,
bypassing the CPU to speed up memory operations. The process is managed by a chip known as
a DMA controller (DMAC).
A computer's system resource tools are used for communication between hardware and software.
The four types of system resources are:
 I/O addresses
 Memory addresses
 Interrupt request numbers (IRQ)
 Direct memory access (DMA) channels
DMA channels are used to communicate data between the peripheral device and the system
memory. All four system resources rely on certain lines on a bus. Some lines on the bus are used
for IRQs, some for addresses (the I/O addresses and the memory address) and some for DMA
channels.
A DMA channel enables a device to transfer data without exposing the CPU to a work
overload. Without the DMA channels, the CPU copies every piece of data using a peripheral bus
from the I/O device. Using a peripheral bus occupies the CPU during the read/write process and
does not allow other work to be performed until the operation is completed.
With DMA, the CPU can process other tasks while data transfer is being performed. The
transfer of data is first initiated by the CPU. During the transfer of data between the DMA
channel and I/O device, the CPU performs other tasks. When the data transfer is complete, the
CPU receives an interrupt request from the DMA controller.
DMA Transfer Types
Memory To Memory Transfer
In this mode block of data from one memory address is moved to another memory address.
In this mode current address register of channel 0 is used to point the source address and the
current address register of channel is used to point the destination address in the first transfer
cycle, data byte from the source address is loaded in the temporary register of the DMA
controller and in the next transfer cycle the data from the temporary register is stored in the
memory pointed by destination address. After each data transfer current address registers are
decremented or incremented according to current settings. The channel 1 current word count
register is also decremented by 1 after each data transfer. When the word count of channel 1 goes
to FFFFH, a TC is generated which activates EOP output terminating the DMA service.
Auto initialize
In this mode, during the initialization the base address and word count registers are loaded
simultaneously with the current address and word count registers by the microprocessor. The
address and the count in the base registers remain unchanged throughout the DMA service.
After the first block transfer i.e. after the activation of the EOP signal, the original values of
the current address and current word count registers are automatically restored from the base
address and base word count register of that channel. After auto initialization the channel is
ready to perform another DMA service, without CPU intervention.

31. ALL THE BEST 31
DMA Controller
The controller is integrated into the processor board and manages all DMA data transfers.
Transferring data between system memory and an 110 device requires two steps. Data goes from
the sending device to the DMA controller and then to the receiving device. The microprocessor
gives the DMA controller the location, destination, and amount of data that is to be transferred.
Then the DMA controller transfers the data, allowing the microprocessor to continue with other
processing tasks. When a device needs to use the Micro Channel bus to send or receive data, it
competes with all the other devices that are trying to gain control of the bus.
This process is known as arbitration. The DMA controller does not arbitrate for control of the
BUS instead; the I/O device that is sending or receiving data (the DMA slave) participates in
arbitration. It is the DMA controller, however, that takes control of the bus when the central
arbitration control point grants the DMA slave's request.

32. ALL THE BEST 32
b) 8085 Architecture: This is the functional block diagram of the 8085 Microprocessor.
This is the functional Block Diagram of 8085 Microprocessor.
Accumulator:-It is a 8-bit register which is used to perform arithmetical and logical operation. It
stores the output of any operation. It also works as registers for i/o accesses.
Temporary Register:-It is a 8-bit register which is used to hold the data on which the accumulator
is computing operation. It is also called as operand register because it provides operands to ALU.
Registers:-These are general purposes registers. Microprocessor consists 6 general purpose
registers of 8-bit each named as B,C,D,E,H and L. Generally theses registers are not used for
storing the data permanently. It carries the 8-bits data. These are used only during the execution
of the instructions.
These registers can also be used to carry the 16 bits data by making the pair of 2 registers. The
valid register pairs available are BC,DE HL. We can not use other pairs except BC,DEand HL.
These registers are programmed by user.

33. ALL THE BEST 33
ALU:-ALU performs the arithmetic operations and logical operation.
Flag Registers:-It consists of 5 flip flop which changes its status according to the result stored in
an accumulator. It is also known as status registers. It is connected to the ALU.
There are five flip-flops in the flag register are as follows:
1.Sign(S)
2.zero(z)
3.Auxiliary carry(AC)
4.Parity(P)
5.Carry(C)
The bit position of the flip flop in flag register is:
All of the three flip flop set and reset according to the stored result in the accumulator.
1.Sign- If D7 of the result is 1 then sign flag is set otherwise reset. As we know that a number on
the D7 always desides the sign of the number.
if D7 is 1: the number is negative.
if D7 is 0: the number is positive.
2.Zeros(Z)-If the result stored in an accumulator is zero then this flip flop is set otherwise it is
reset.
3.Auxiliary carry(AC)-If any carry goes from D3 to D4 in the output then it is set otherwise it is
reset.
4.Parity(P)-If the no of 1's is even in the output stored in the accumulator then it is set otherwise
it is reset for the odd.
5.Carry(C)-If the result stored in an accumulator generates a carry in its final output then it is set

34. ALL THE BEST 34
otherwise it is reset.
Instruction registers(IR):-It is a 8-bit register. When an instruction is fetched from memory then
it is stored in this register.
Instruction Decoder:- Instruction decoder identifies the instructions. It takes the informations
from instruction register and decodes the instruction to be performed.
Program Counter:-It is a 16 bit register used as memory pointer. It stores the memory address of
the next instruction to be executed. So we can say that this register is used to sequencing the
program. Generally the memory have 16 bit addresses so that it has 16 bit memory.
The program counter is set to 0000H.
Stack Pointer:-It is also a 16 bit register used as memory pointer. It points to the memory
location called stack. Generally stack is a reserved portion of memory where information can be
stores or taken back together.
Timing and Control Unit:-It provides timing and control signal to the microprocessor to perform
the various operation.It has three control signal. It controls all external and internal circuits. It
operates with reference to clock signal.It synchronizes all the data transfers.
There are three control signal:
1.ALE-Airthmetic Latch Enable, It provides control signal to synchronize the components of
microprocessor.
2.RD- This is active low used for reading operation.
3.WR-This is active low used for writing operation.
There are three status signal used in microprocessor S0, S1 and IO/M. It changes its status
according the provided input to these pins.
Serial Input Output Control-There are two pins in this unit. This unit is used for serial data

35. ALL THE BEST 35
communication.
Interrupt Unit-There are 6 interrupt pins in this unit. Generally an external hardware is connected
to these pins. These pins provide interrupt signal sent by external hardware to microprocessor
and microprocessor sends acknowledgement for receiving the interrupt signal. Generally INTA
is used for acknowledgement.