This document provides information on computer organization and design. It discusses the basic components of a computer system including the CPU, memory, I/O devices, and how they interconnect. It also describes different types of computer architecture like Von Neumann and Harvard architectures. Additionally, it covers topics like instruction codes, addressing modes, instruction cycles, and levels of programming languages from low-level machine code to high-level languages.

1. Chapter three
Basic Computer Organization and Design
Computer organization refers to the way the various components of a computer system are
interconnected and work together to perform tasks and execute programs.
It encompasses the design and arrangement of hardware components, including the central
processing unit (CPU), memory, input/output devices, and control units, to ensure
efficient and effective operation of the computer.
➢ The internal organization of a digital system is defined by the sequence of micro-operations
it performs on data stored in its registers.
➢ The general-purpose digital computer is capable of executing various micro-operations
and, in addition, can be instructed as to what specific sequence of operations it must
perform.
Computer organization includes the physical connection component, like circuits with adder
subtractor. If we talk about CPU organization, its three types are:
➢ Single Accumulator Organization
➢ General Register Organization
➢ Stack Organization
Computer organization plays a crucial role in determining the overall performance and efficiency
of a computer system.
Designing efficient interactions between hardware components is essential for achieving optimal
processing speeds and responsiveness.

3. ➢ The user of the computer can control the process by means of a program. A Program is a
set of instructions that specify the operations, operands, and the sequence by which
processing has to occur.
➢ Computer Register
▪ Computer instructions are usually stored in consecutive memory locations and executed
sequentially one at a time. this requires a register which can stored the address of the next
instruction; we call it the Program Counter.
▪ We need registers which can hold the address at which a memory operand is stored as well
as the value itself.
▪ We need a place where we can store:
▪ temporary data
▪ the instruction being executed
▪ a character being read in, a character being written out.
Addressing modes
The way in which the operand is specified is called its addressing mode.
• It indicates the way of locating data or it indicates the way of locating data or operands

4. Two categories Two categories
▪ Those for data / sequential execution programming
▪ Those for branch addresses
Data related addressing modes
1. Immediate Immediate – the datum is either 8 bits or the datum is either 8 bits or 16 bits
long and is part of the instruction
2. Direct – the 16-bit effective address of the 16-bit effective address of the datum is part of
the instruction
3. Register Register – the datum is in the register that the datum is in the register that is
specified by the instruction
4. Register indirect – the effective address of the effective address of the datum is in the base
register BX or in an index register that is specified by the instruction
5. Indexed – offset of the operand is stored in one of offset of the operand is stored in one of
the index registers.
6. Register relative – the EA is the sum of an 8 bit or the EA is the sum of an 8 bit or 16-bit
displacement and the contents of a base register or an index register.
7.Based indexed – the effective address is the effective address is the sum of a base register
and an index register both of which are specified by the instruction
8. Relative Based indexed – The EA is the EA is the sum of an 8 bit or 16-bit displacement
and a based indexed address.
I. Basic organization of the von Neumann machine
➢ It is a type of digital computer architecture in which the design follows the concept of the
computers with stored programs where they store the program data along with the
instruction data in the very same memory.

5. ➢ There are four main components within the Von Neumann Architecture. These components
work together to enable processing, storage, and communication within the computer
system. They are:
➢ Central Processing Unit (CPU): The part of a computer that carries out instructions and
performs arithmetic, logical, and control operations.
➢ Memory: A place where the computer stores and retrieves data and instructions.
➢ Input-Output (I/O) devices: Components responsible for interfacing the computer with
the external world. Examples of I/O devices include keyboards, printers, and monitors.
➢ System Bus: A communication pathway that connects the CPU, memory, and I/O devices,
enabling data and control signals to flow between these components.

6. II. What is Harvard Architecture
➢ It is a type of digital computer architecture in which the design follows a basic concept of
having separate signal paths (buses) and separate storage for data and instructions.
➢ This type of architecture basically surfaced to overcome the overall bottleneck of the Von
Neumann Architecture.
➢ This microcontroller design has separate storage areas and signals for instructions and data.
The basic difference between Von Neumann and Harvard Architecture is the contrast in the
storage area for instructions and data.
➢ Unlike Harvard, Von Neumann has the same storage unit for programs and instructions.
However, modern processors use Von Neumann microcontrollers

7. Instruction Codes:
➢ A set of instructions that specify the operations, operands, and the sequence by
which processing has to occur.
➢ An instruction code is a group of bits that tells the computer to perform a specific
operation part. Format of Instruction
➢ The format of an instruction is depicted in a rectangular box symbolizing the bits
of an instruction. Basic fields of an instruction format are given below:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates the memory address or register.
3. A mode field that specifies the way the operand of effective address is
determined.
Computers may have instructions of different lengths containing varying number
of addresses. The number of address field in the instruction format depends upon
the internal organization of its registers
Computer Instructions:
The basic computer has 16-bit instruction register (IR) which can denote either memory reference
or register reference or input-output instruction.

8. I. Memory Reference – These instructions refer to memory address as an operand. The other
operand is always accumulator.
Specifies 12-bit address, 3-bit opcode (other than 111) and 1 bit addressing mode for direct
and indirect addressing.
Example – IR register contains = 0001XXXXXXXXXXXX, i.e., ADD after fetching and
decoding of instruction we find out that it is a memory reference instruction for ADD
operation.
Hence, DR <- M[AR] AC <- AC+ DR, SC <- 0
II. Register Reference – These instructions perform operations on registers rather than
memory addresses.
The IR (14-12) is 111 (differentiates it from memory reference) and IR (15) is 0 (differentiates
it from input/output instructions).
The rest 12 bits specify register operation. Example – IR register contains =
0111001000000000, i.e., CMA after fetch and decode cycle we find out that it is a register
reference instruction for complement accumulator. Hence, AC <- ~AC
III. Input/Output – These instructions are for communication between computer and outside
environment.
The IR (14-12) is 111 (differentiates it from memory reference) and IR (15) is 1 (differentiates
it from register reference instructions). The rest 12 bits specify I/O operation. Example – IR
register contains = 1111100000000000, i.e., INP after fetch and decode cycle we find out that
it is an input/output instruction for inputting character. Hence, INPUT character from
peripheral device
Direct and Indirect Addressing Modes
➢ When the second part specifies the address of an operand, the instruction is said to have
direct address.
➢ This is in contrast to a third possibility called indirect address, where the bits in the
second part of the instruction designate an address of memory word in which the address
of the operand is found.

10. The register-reference instructions
are recognized by the operation code 111 with a 0 in the left most bit (bit 15) of the instruction

12. Input-output instructions

13. Timing and Control
All sequential circuits in the Basic Computer CPU are driven by a master clock, with the
exception of the INPR register.
At each clock pulse, the control unit sends control signals to control inputs of the bus, the
registers, and the ALU.
Control unit design and implementation can be done by two general methods:
➢ A hardwired control unit is designed from scratch using traditional digital logic
design techniques to produce a minimal, optimized circuit. In other words, the control
unit is like an ASIC (application-specific integrated circuit).
➢ A microprogrammed control unit is built from some sort of ROM. The desired
control signals are simply stored in the ROM, and retrieved in sequence to drive the
microoperations needed by a particular instruction.
The following section deals with the control unit. As we can see in figure 5.1, the control unit
consists of two decoders, a sequence counter, and logic gates.

14. As depicted in figure 5.1, any instruction which is read from the memory is placed in the
Instruction Register (IR). Here, the IR is split into three parts, namely, I bit, opcode, and bits
from 0 through 11.
The opcodes are decoded with a 3 * 8 decoder whose outputs are denoted by symbols D0
through D7 .
The binary value of the respective opcode is the subscripted number in the symbol. The
symbol I which is the 15th bit of the instruction is moved to a flip flop.
The control logic gates have the bits that are applied from 0 through 11. The sequence counter
is 4-bit counts in binary from 0 through 15.
It can be incremented or cleared synchronously. The timing signals from T0 through T15 are
the decoded outputs of decoder.

15. A memory that is read or written is always initiated with the rising timing signal. We are aware
Notes that a clock cycle time is greater than a memory cycle time.
So, when the clock goes through its next positive transition, the memory read/written gets
completed.
This transition is used to load the memory word to register. But in usual cases, the memory
cycle time is longer than the processor cycle. So, it contradicts the timing relation. Therefore,
wait cycles are provided till the memory word is made available.
Consider figure 5.2 that shows the time relation between the control signals.
In figure 5.2, the control signals are generated by the 4-bit sequence counter and a 4 * 16
decoder.
In this figure, consider at time T4 , Sequence Counter (SC) is cleared to 0 if the output D3 of
decoder is active.
This can be represented as: D3T4: SC  0 The SC gives response to the positive transition of
the clock. The CLR input of the SC is active in the beginning.

16. ➢ Instruction Cycle
The main execution process is done by the processor. The processing of instruction involves two
steps, instruction fetch and instruction execution. Each instruction is fetched from the memory
separately and executed. Depending on the nature of the instruction its execution may deal with a
number of operations. An instruction cycle refers to the processing of a particular instruction.
Each instruction cycle goes through the following phases during its processing:
1. Fetching instruction from memory.
2. Decoding the instruction.
3. Reading the effective address from memory in case of indirect address.
4. Executing the instruction
After the above four steps are completed, the control switches back to the first step and repeats
the same process for the next instruction. Hence, the cycle continues until a HALT condition
is met. Figure 5.3 depicts the phases involved in the instruction cycle.
As shown in figure 5.3 the halt condition occurs when the machine gets turned off, on
occurrence of errors that are unrecoverable, and so on.
Computer Languages
Over the years, computer languages have been evolved from Low-Level to High-Level Languages.
In the earliest days of computers, only Binary Language was used to write programs. The computer
languages are classified as follows:

17. Assembly is an intermediate language between high-level programming and machine
language.
➢ machine Language (low level language)
Low-Level language is the only language which can be understood by the computer. Low-
level language is also known as Machine Language.
The machine language contains only two symbols 1 & 0. All the instructions of machine
language are written in the form of binary numbers 1's & 0's. A computer can directly
understand the machine language.
➢ Assembly Language (middle level language)
Middle-level language is a computer language in which the instructions are created using symbols
such as letters, digits and special characters.
Assembly language is an example of middle-level language. In assembly language, we use
predefined words called mnemonics.
Binary code instructions in low-level language are replaced with mnemonics and operands in
middle-level language.
But the computer cannot understand mnemonics, so we use a translator called Assembler to
translate mnemonics into machine language.

18. Assembler is a translator which takes assembly code as input and produces machine code as output.
That means, the computer cannot understand middle-level language, so it needs to be translated
into a low-level language to make it understandable by the computer. Assembler is used to translate
middle-level language into low-level language.
g++ -S main.cpp -o main’s
Assembly language is more than low-level and less than high-level language. Hence, it is also
referred to as intermediary language. It uses symbols and abbreviations instead of binary numbers
0s and 1s. For example, assembly language uses symbols often known as mnemonics like Add for
addition, Sub for subtraction, Mul for multiplication, and so forth.
Assembly language codes are more human-readable than machine languages ones. Unlike machine
code, it is not very difficult for users to remember or understand assembly codes and commands.
Since the assembly language code uses mnemonics which isn’t understandable by the CPU
directly, it needs a translator to convert mnemonic codes (assembly language code) into machine
language (machine or object or binary code). It is done with the help of a compiler known
as assembler. Now let's see what this assembler is, and it's working in detail.
➢ High Level Language
High-level language is a computer language which can be understood by the users. The high-level
language is very similar to human languages and has a set of grammar rules that are used to make
instructions more easily.
Every high-level language has a set of predefined words known as Keywords and a set of rules
known as Syntax to create instructions.
The high-level language is easier to understand for the users but the computer cannot understand
it. High-level language needs to be converted into the low-level language to make it understandable
by the computer.
We use Compiler or interpreter to convert high-level language to low-level language.

19. Languages like FORTRAN, C, C++, JAVA, Python, etc., are examples of high-level languages.
All these programming languages use human-understandable language like English to write
program instructions. These instructions are converted to low-level language by the compiler or
interpreter so that it can be understood by the computer.
g++ main.cpp