Commercial and Open SoC buses_AMBA_OCP.ppt

SoC Design
Thomas Hollstein | Kalle Tammemäe | Dept. of CS
Commercial and Open SoC busses
AMBA bus, PI bus,
IBM Core Connect
ST bus, Wishbone
OCP-IP
1

SoC Design
Outline
 Introduction to bus architectures
 AMBA bus
 PI bus
 IBM Core Connect
 ST bus
 Wishbone
 OCP-IP
 Virtual Socket Interface Alliance (VSIA)
 Nios II Avalon Bus
Extra material

SoC Design
Introduction
 Bus = shared wires by multiple communicating
units
 Connection logic to avoid electrical conflicts
 Arbitration to determine bus ownership in time
 Protocols – set of rules for transmitting information
between multiple units
 Buses designed for PCs and PCBs are not
suitable for SoC-s
 Designed for backplane
 Limited speed
 Limited number of signals
3

SoC Design
Bus protocol
 the type and order of data being sent;
 how the sending device indicates that it has
ﬁnished sending the information;
 the data compression method used, if any;
 how the receiving device acknowledges
successful reception of the information; and
 how arbitration is performed to resolve
contention on the bus and in what priority,
and the type of error checking to be used.
4
[Flynn 2011]

SoC Design
Bus-based approach
5
[Flynn 2011]
Possible
hierarchy of
buses to optimize
system-level
performance and
cost
Cores or IPs
• Format
conversion
• Segmentation
• Buffering
Address
Data
Control
Power
A bus might
deliver power to
peripherals

SoC Design
Bus architectures
 Unified or split (address and data)
 Simple with request acknowledgement
signals
 Bus with arbitration support
 Tenured split bus (bus is occupied only
during associated address or data cycles)
6
[Flynn 2011]
Memory access time
for the first word

SoC Design
Bus Architectures
Technology AMBA
AXI
(AMBA 3) CoreConnect
Smart
Interconnect
IP Nexus
Company ARM ARM IBM Sonics Fulcrum**
Core type Soft/hard Soft/hard Soft Soft Hard
Architecture Bus
Unidirectional
channels Bus Bus
NOC using
direct switch
Bus width 8 - 1024 8 - 1024 32/64/128 16 8 - 128
Frequency 200 MHz 400 MHz*
100 - 400
MHz 300 MHz 1 GHz
Maximum
BW (GB/s) 3 6.4* 2.5 - 24 4.8 72
Minimum
latency (ns) 5 2.5* 15 n/a 2
7
[Flynn 2011]
* As implemented in the ARM PL330 high-speed controller.
**Fulcrum was acquired by Intel in 2011

SoC Design
Outline
 PI bus
 AMBA bus
 ST bus
 Wishbone
 OCP-IP

SoC Design
Advance Microcontroller Bus Architecture (AMBA)
 Develped by ARM in 1996
 Distinct busses in AMBA specification:
1. Advanced High performance Bus (AHB)
2. Advanced Peripheral Bus (APB)
3. [Advanced System Bus (ASB) – designed for
lower performance systems, outdated]
 AXI - Advanced
Extensible
Interface
(since AMBA 3)
[Flynn 2011]
ARM

SoC Design
AMBA AHB
 High-performance on-chip backbone bus
 Connecting: processors, on-chip and off-chip
memory interfaces
 DMA capability
 Bridge to APB bus
 Features: burst transfers, split transactions,
single cycle bus master transfer
 Single clock edge (rising) operation and
non-tristate (central multiplexer) implementation
 Central arbiter
 Tenured (address phase can occur during previous
data phase

SoC Design
AMBA AHB bus transaction steps
 Bus Master obtains access to the Bus
 Arbiter resolves simultaneous requests
 Bus Master initiates transfer, driving signals:
 Address, Width, Direction
 Burst options
 Bus Slave provides a Response
 Success | need for delay (wait states) | error
11

SoC Design
AMBA APB bus cycle
 APB bus is optimised for minimal power and
low complexity (less performance)
 Used to interface to peripherals, which are
low bandwidth
 Three state working diagram:
Idle – Setup – Enable (actual transfer
cycles)
12

SoC Design
AMBA Advanced Extensible Interface (AXI)
 AXI4 - AMBA 4.generation for high-performance, high frequency
 Features:
 Unaligned data transfers using byte strobes
 Burst-based transactions
 Backward compatibele with AHB and APB interfaces
 Separate address/control and data phases
 Separated read and write data channels (providing low-cost DMA)
 Two channels for address (read, write) and control signals
 Additional write response channel for signaling completion of write
transactions
 AXI protocol supports several types of bursts: normal memory
access, wrapping cache line, streaming data to peripheral FIFOs
 Power management features
 ACE (Advance Cache Coherency Extensions)
 Out-of-Order transaction completion

5 channels

SoC Design
AXI protocol
14
Data channels can be:
8,16,32, … , 1024 bits wide
Three system topologies:
• Shared address and data
buses
• Shared address buses and
multiple data buses
• Multilayer, with multiple
address and data buses
Channel architecture
of reads
Channel architecture
of writes

SoC Design
AXI handshake
 VALID-READY signals
 Each channel (address,
data, response) has own
handshake signal pair
 Transfer happens at
clock edge T3 (Fig. 1
and 2) or when both are
ready, at T2 (fastest),
Fig. 3.
 There are more control
signals in all channels!
15
1
2
3

SoC Design
AXI burst transfer
 FIXED – address is same for
every transfer in the burst
(e.g. loading or unloading a
FIFO)
 INCR – address for each
transfer is an increment of
the address for previous
transfer (increment depends
on the size of transfer)
 WRAP – similar to INCR but
address wraps around to
lower address when upper
address limit is reached (used
for cache line accesses)
 Unaligned transfers
 Write strobes - indicate valid
bytes in transfer
 Narrow transfers – transfers
narrower than data bus:
 Fixed lanes (FIXED)
 different byte lanes (INCR or WRAP)
16
Example: Address 0x00, aligned,
burst length – 4 transfers, transfer
length – 32 bits

SoC Design
AXI burst and handshake examples
Overlapping
read bursts
17
One or another or
both
Both have to be
present
Write
transaction
handshake
dependencies

SoC Design
AXI on Cortex-A microprocessor
 64/128-bit
Configurable AXI Bus
 dedicated read, write,
and address channels
 up to 23 outstanding
transactions with out-
of-order completion
 AMBA® Designer
interconnect design
tool
18
Cortex-A8

SoC Design
Zync-7000 AP SoC interfaces and signals
19
[Crockett, Zync book 2014, p192]
GP – General Purpose
HP – High Performance
ACP – 64-bit
Accelerator Coherency
Port for asynchronous
cache-coherent access

SoC Design
Zync-7000
 Zynq-7000 devices
are equipped with
dual-core ARM
Cortex-A9
processors
integrated with
28nm Artix-7 or
Kintex®-7 based
programmable
logic
[Xilinx Web]
20

SoC Design
Zynq-7000 AP SoC
21
[Zynq-7000 All
Programmable SoC
Technical Reference
Manual UG585
(v1.11) September
27, 2016]

SoC Design
ARM CoreLinkTM
System (IP)
 Components and Methodology for Systems based on AMBA:
Source: ARM.com
 DMC: DRAM Controller
 MMU: Memory
Managing Unit for
hardware-assisted core
virtualisation (handling
privileged and shared
access from
hypervisors)
 NIC: hierarchical low-
power and low latency
interconnect
Source:
ARM.com
CoreLink CCI-500 Cache Coherent Interconnect for
coherency with up to four clusters including big.LITTLE and
coherent accelerators, and higher performance and efficiency
with integrated snoop filter. Optimized for mobile.

SoC Design
ARM CoreLinkTM
System
 Components and Methodology for Systems based on AMBA:
Source: ARM.com

SoC Design
ARM CoreLinkTM
System
 Security Features:
Source: ARM.com

SoC Design
ARM CoreSightTM
System
 Debug Interface:
Source: ARM.com

SoC Design
ARM CoreSightTM
System – Debug&Trace
 CoreSightTM
Debug Interface:
Source: ARM.com

SoC Design
Amba 5 AXI5, ACE5
 Design&Reuse blog by Phil Dworsky,
Synopsys
Feb. 08, 2018
Synopsys
supports launch of Arm AMBA 5 AXI5, ACE5 p
rotocols with 1st source code test suite and V
IP
27

SoC Design
Outline
 AMBA bus
 PI bus
 ST bus
 Wishbone
 OCP-IP

SoC Design
Peripheral Interconnect (PI) bus
Copyright: Siemens AG 1994, Source: http://ensiwiki.ensimag.fr/images/b/b8/Pibus.pdf

SoC Design
 Open on-chip bus standard
 Defined by Open Microprocessor Systems Initiative
(ARM, SGS-Thomson, TEMIC-Matra MHS, Philips,
Siemens)
 Synchronous and processor-independent shared bus
system
 Memory-mapped data transfers
 Multiple masters, multiple slaves
 Bus arbiter periodically analyses requests from
masters
 Free VHDL code

SoC Design
 Processor independent
 Demultiplexed operation
 Clock - synchronous
 Peak transfer rate of 200 Mbytes/s (@ 50 MHz bus clock)
 Address and data bus scalable (up to 32 bits)
 8-/16-/32-bit data accesses
 Broad range of transfer types from single to multiple data
transfers
 Multimaster capability
PI-Bus does not provide:
 Cache coherency support
 Broadcasts
 Dynamic bus sizing

SoC Design
 Designed around IBM PowerPC core (adaptable to other cores)
 Slave-centric (in contrast to most other master-centric busses)
 Multiple shared slave segments
 Three buses:
1. Processor Local Bus (PLB), 128 bits
• high bandwidth, low latency
• Processor cores,
external memory interfaces,
DMA controllers
2. On-Chip Peripheral Bus (OPB),
32 bits, multiple masters and slaves
3. Device Control Register Bus (DCR)
 Decoupled address, read and write data
buses (concurrent read and write
transfers)
 Address pipelining
 No-fee, no-royalty to companies
IBM Core Connect
Source: www.design-reuse.com

SoC Design
CoreConnect vs AMBA
IBM CoreConnect PLB AMBA 2.0 HPB
Bus architecture 32, 64, 128, extendable
to 256 bits
32, 64, and 128 bits
Data buses Separate read and write Separate or three-state
Key capabilities Multiple bus masters
Four-deep read pipeline,
Two-deep write pipeline
Split transactions
Burst transfers
Line transfers
OPB (on-chip peripheral
bus)
Multiple bus masters
Pipelining
Split transactions
Burst transfers
Line transfers
AMBA APB
Masters supported Multiple masters Single master: The APB
bridge
34

SoC Design
 Dedicated to consumer applications (set-top
boxes, digital HDTV, digital cameras)
 Set of architectures, interfaces and protocols
 Each operation consists of one or several
request/response pairs
 3 types of STBus protocols:
 Type1: simple protocol for peripheral register access
(no pipeline, acts as Request/Grant protocol)
 Type 2: Type1 + additional pipeline features and
operation codes for ordered transactions
 Type 3: Type 2 + advanced protocol implementing
split transactions (splitting into „request transaction“
and „reply transaction“)
 http://www.design-reuse.com/articles/16092/stbus-complex-interconnect-
design-and-verification-for-a-hdtv-soc.html
ST Microelectronics STBus
Source: www.design-reuse.com

SoC Design
STBus Arbitration
 Static priority (non-preemtive)
 Programmable priority
 Latency based
 Masters have counter register, loaded with max
latency during request
 Counters are decreased at each access cycle
 Arbiter grants access to master with lowest
counter register value
 When draw, static priorities will be used
37

SoC Design
 Public version available since 2002 via Open-Core,
updated in 2010 (Wishbone Rev.B4)
 „logic bus“– does not specify electrical information or topology
 Aim: support use of open cores
 Scalable bus architecture based on simple master/slave
handshake communications
 Configurable bitwidths: 8, 16, 32
 Supported interconnection topologies:
 Direct P2P (master to slave)
 Dataflow interconnection based on systolic array architectures
 Shared bus and crossbar switch interconnection (most commonly used in
SoCs)
 http://opencores.org/opencores,wishbone
Wishbone

SoC Design
 Examples for Wishbone interconnection topologies:
Wishbone
Shared Bus. Source: wikipedia.org
Pipeline. Source: wikipedia.org
Crossbar Switch. Source: wikipedia.org

SoC Design
 socket (bus wrapper) interface for SoC design
 configurable and highly scalable interface for on-chip
subsystem communications
 non-profit, open-industry standards body
 www.ocpip.org
 OCP phases
 Request
 Response
 Data Handshake
Open Core Protocol International Partnership (OCP-IP)
Source: Prashant D. Karandikar, Texas Instruments Inc

SoC Design
 Multiple request multiple data possible
 Reduced chip area by configuring into the OCP interfaces only those
features needed by the communicating cores.
 Simplified system verification and testing by providing built-in test
mechanisms
 Protocols for cache coherence
Open Core Protocol International Partnership (OCP-IP)
Source: Prashant D.
Karandikar, Texas
Instruments Inc
[OCP Specification3.0]

SoC Design
Outline
 AMBA bus
 PI bus
 ST bus
 Wishbone
 OCP-IP
Extra material

SoC Design
Virtual Socket Interface Alliance (VSIA)
 VSI enables system-level interaction on a chip using
predesigned blocks called virtual components (VC).
 Hard VC (placed and routed)
 Soft VC (HDL description)
 Firm VC (in the form of generators or partially placed
library blocks)
 Other buses can interface over VCs following VSI
standard protocols
VSIA was founded in 1996 and dissolved in 2008. All
documents are given to the public domain:
http://www.vsia.org - legacy documents
45

SoC Design
Nios II – Avalon Bus
 Switch Fabric to connect CPU, DMA, memory
and memory mapped peripherals on FPGA
 Master-slave modules
• Master address is a byte address
• Slave address is a word address
 Synchronous, rising clock edge
 Separate data in and out
 Data path up to 8, 16, …, 1024 bits (word size)
 Slave-side arbitration,
multiple simultaneous masters (each master-slave
pair has a dedicated connection between them)
 Pipelined read transfers, Burst transfers
46
Avalon does address
translation and
multiple accesses
when needed

SoC Design
Avalon Multi-Mastering
47
Example multi master system
that permits bus transfers
between two masters and two
slaves
[Simultaneous Multi-Mastering
with the Avalon Bus, Application
note 184, Altera 2002]
Avalon Bus Control Signals:
• Master Request Slave (MRS)
• Master Select Granted (MSG)
• Wait

SoC Design
Summary
48
[https://en.wikipedia.org/wiki/Bus_(computing)]
PC Express
x 4
x 16
x 1
x 16
Conventional
32-bit PCI

Commercial and Open SoC buses_AMBA_OCP.ppt

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