The document discusses various bus protocols, including the ISA, EISA, PCI, and AMBA, that facilitate communication between processors and I/O devices in computer and embedded systems. It details the specifications, advantages, and limitations of each protocol, emphasizing the need for high-speed data transfer and efficiency in system designs. Additionally, it describes the features and benefits of the AMBA architecture for complex system-on-chip designs, highlighting its role in improving compatibility, reusability, and performance.

1. BUS PROTOCOL AND AMBA
TRANSACTIONS
-ARAVINDHAKRISHNAN

2. DIFFERENT BUS PROTOCOLS
A computer system connects at high speed toother subsystems having a range of IO devices.When the IO in the
distributed embeddedsystem are networked , all can communicateusing common parallel bus.A parallel bus has a
large number of lines asper the protocol.
Figure shows processor of an Embedded
System ‘A’ connected to system memory bus
and networked to other subsystem using PCIbridge and AMBA-APB bridge respectively.

3. DIFFERENT BUS PROTOCOLS
1. We need an interconnection bus within PC orEmbedded Systems to a number of PC-Based IOcards ,
systems and devices . This bus needs to beseparated from system-bus that connects theprocessor to the
memories.The system bus and the interconnecting I/O bus haveto operate at different levels of speed.
2. ISA and EISA(Extended ISA), PCI and PCI/X buses are the interconnection buses for communicationbetween
host and device.
3. Parallel bus is a bus interconnecting the IO devices and peripherals at high speed over shortdistances.ISA
& PCI are examples of parallel bus.
4. Parallel bus is a bus interconnecting the IO devicesand peripherals at high speed over shortdistances.ISA &
PCI are examples of parallel bus

4. ISA AND EISA BUSES
An ISA bus connects only to embedded deviceswhich has an 8086,80186,80286 processor.
The limitations for memory access by system usingISA bus of original IBM PC are as follows:
ISA bus memory can be of two ranges 640Kbto 1Mb & 15Mb to 16Mb.The former rangeoverlays with the range
used by video boardsand BIOS.LinuxOS doesnotsupport thesecond range directly for accessing a device.
The limitations of IO port addresses for deviceare as follows:
8086 & 80286 processor has IO mapped I/O’s notmemory mapped I/O’s.
Instruction set provides IO instruction for 64kb IOaddresses ,the IBM PC configuration ignores theaddress lines A10 to
A15 and they are notdecoded, ie. Only 1024 IO port addresses areavailable [in hexadecimal nipple representation
itranges from 00F]
Following are the addresses allocated in IBM
standard architecture(ISA)
1)Addresses from 0x000-ox00F for DMA chip.
2)0x020 -0x021 addresses allocated for PIC 82C55.

5. ISA AND EISA BUSES
3)0x060-0x063 for parallel port programmableparallel interface.
4)Hex 2F8-2FF & 3F8-3FF for IBM COM ports.
5)Hex 380-389 & 3A0-3A9 for synchronouscommunication.
6)Synchronous datalinkcontrol (SDLC) addressesallocated are between hex 380-38C.
7)Hex 380-38F to display monitor ports & 3D0-3DF for colourand graphics.
There is a limited availability of interrupt vectors,only 256 vectors are available.Interruptservice functions are now
shared at softwarelevels(SWI). Original ISA specification did notallow that.
ISA & EISA buses are compatible with IBMarchitecture.Theyare used to connect devicesfollowing IO addresses
and interrupt vectorsas per IBM PC architecture.
EISA is 32 bit extension of ISA, it also supportsinterrupt functions and ethernetdevices.

6. PCI AND PCI/X BUSES

PCI is widely used synchronous parallel bus incomputer system for interfacing I/O devices.

It is platform independent unlike the ISAwhich depends on IBM PC platform, interruptvectors ,I0 address
and memory allocations.

PCI is a parallel synchronous I/O bus.

PCI switch(bridge) communicates withmemory through a memory bus.

A separate IO bus connects the switch to the device.

Separate memory & IO buses are used because the IO system is usually designed with maximum
flexibility to allow many different I/O devices aspossible to interface to the system while the memory bus
is designed to provide maximum possible bandwidth between the processor and the memory system.

PCI devices identifies its devices by three identification number
1)IO port
2)memory location
3)configuration register of total 256 B with 4 byteunique ID

7. PCI AND PCI/X BUS
PCI devices when interrupted handles the interrupt of type n(PCI). The PCI device has 64 bytes standardconfiguration
registers.
The PCI drivers can access the hardware automatically as well as by the programmer assigned
addresses.ThePCI feature of automatically detectingthe interfacing systems for assigning new address isimportant for
coding a device driver. The PCI bus hence simplifies addition and deletion of system peripherals.
The PCI device can initialiseat booting timethat helps in avoiding any address collision. APCI device on boot up
disables its interrupts.
Its address space is inaccessible and onlyconfiguration register space remainsaccessible.
PCI parallel bus is popular in distributedembedded devices.PCI & PCI/X buses are usedand there are independent
from IBMarchitecture.
PCI/X is an extension of PCI & supports64/100MHz transfers.

8. ADVANCED PARALLEL HIGH SPEED BUSES
The buses discussed above may not havesufficient high speed, ultra high speed andlarge bandwidth that are
required for routers,LAN’s ,switches and gateways and other products.
An embedded system may need to connect IOsystem using gigabit parallel synchronous interface
The following are advanced bus standard &proprietary protocols developed recently:
1. GMII(Gigabit ethernetMAC interchange interface)
2. XGMI(10 Gigabit ethernetMAC interchange interface)
3. CSIX-1.6.6 Gbps32 bit HSTL with 200 Mhzperformance.

9. WHAT IS AMBA, AND WHY USE IT?

The Arm Advanced Microcontroller Bus Architecture, or AMBA, is an open-standard, on-chip interconnect
specification for the connection and management of functional blocks in system-on-a-chip (SoC) designs.
Essentially, AMBA protocols define how functional blocks communicate with each other.

AMBA simplifies the development of designs with multiple processors and large numbers of controllers and
peripherals. However, the scope of AMBA has increased over time, going far beyond just microcontroller
devices.
Today, AMBA is widely used in a range of ASIC and SoC parts. These parts include applications processors
that are used in devices like IoT subsystems, smartphones, and networking SoCs.
AMBA provides several benefits:
• Efficient IP reuse IP reuse is an essential component in reducing SoC development costs and timescales. AMBA
specifications provide the interface standard that enables IP reuse. Therefore, thousands of SoCs, and IP products, are using
AMBA interfaces.
• Flexibility AMBA offers the flexibility to work with a range of SoCs. IP reuse requires a common standard while supporting
a wide variety of SoCs with different power, performance, and area requirements. Arm offers a range of interface
specifications that are optimized for these different requirements.
• Compatibility A standard interface specification, like AMBA, allows compatibility between IP components from different
design teams or vendors.

10. WHAT IS AMBA, AND WHY USE IT?
• Support AMBA is well supported. It is widely implemented and supported throughout the semiconductor
industry, including support from third-party IP products and tools.
Bus interface standards like AMBA, are differentiated through the performance that they enable. The two
main characteristics of bus interface performance are:
• Bandwidth The rate at which data can be driven across the interface. In a synchronous system, the maximum
bandwidth is limited by the product of the clock speed and the width of the data bus.
• Latency The delay between the initiation and completion of a transaction. In a burst-based system, the
latency figure often refers to the completion of the first transfer rather than the entire burst.
The efficiency of your interface depends on the extent to which it achieves the maximum bandwidth with zero
latency.

11. AXI PROTOCOL OVERVIEW

12. ARCHITECTURE

13. KEY FEATURES OF AXI PROTOCOL
1. Separate Read and Write Channels:
AXI supports independent read and write data channels. This allows read and write operations to occur simultaneously
and independently, improving overall performance.
2. Burst Data Transfers:
AXI supports burst transactions, allowing a master to transfer multiple data items in a single burst. Bursts can be of various
lengths (up to 256 beats) and types (INCR, WRAP, FIXED).
3. Data Interleaving:
AXI allows for out-of-order transaction responses and interleaving of data from multiple masters, which optimizes data
handling across multiple devices.
4. Variable Data Widths:
AXI supports variable data widths (e.g., 32-bit, 64-bit, 128-bit, and even 256-bit). The WSTRB (write strobe) signal
allows fine-grained control over byte-specific writes.
5. Low-Latency Addressing:
With a split address and data phases, AXI minimizes the latency for high-frequency address signaling while
allowing data transfer to proceed with a longer path.

14. KEY FEATURE OF AXI PROTOCOL
1. Unaligned Data Transfers:
The AXI protocol supports unaligned data transfers, which means data can be aligned to any byte boundary,
simplifying memory mapping.
2. Handshake Mechanism:
AXI uses a handshake mechanism (VALID and READY signals) to control data transfer, ensuring that both sender and
receiver are ready for the transaction, thus allowing flexible data throughput
3. Support for Quality of Service (QoS):
The AXI protocol provides QoS support, which enables traffic prioritization and can help in managing latency-sensitive
applications.
4. Cache and Protection Support:
AXI provides signals for cacheable and bufferable accesses, allowing memory controllers to optimize cache
performance. It also supports protection signals, like AWPROT and ARPROT, for secure data transactions.
5. Error Handling:
AXI includes error responses (OKAY, EXOKAY, SLVERR, and DECERR) to detect and handle data transfer errors,
enhancing the robustness of communication.

15. CHANNEL DEFINITION
Write Address channel (AW): Provides the address where data should be written
Write Data channel (W): The actual data sent
Write Response channel (B): Status of write
Read Address: A channel for read signals
Read Data: A channel for read signals

16. WRITE CHANNEL SIGNALS

17. READ CHANNEL SIGNAL

18. CHANNEL HANDSHAKE

19. SINGLE WRITE TRASACTION

20. MULTIPLE WRITE TRANSACTION

21. BURST TYPES

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