This document discusses the different addressing modes of the 8085 microprocessor, including direct, register, register indirect, immediate, and implicit addressing modes. It provides examples of instructions that use each addressing mode, showing the operation, source, and destination. The document also discusses the timing diagram of the 8080, explaining that it displays the initiation of read/write operations controlled by status signals. It notes that the microprocessor performs fetch and execute operations in machine cycles identified by unique status signal combinations.

1. Addressing Modes of 8085

2. 8085 uses the following addressing modes:
1. Direct Addressing Mode
2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Immediate Addressing Mode
5. Implicit Addressing Mode

3. In this mode, the address of the operand is given in
the instruction itself.
LDA is the operation.
2500 H is the address of source.
Accumulator is the destination.
LDA 2500 H
Load the contents of memory location 2500 H in
accumulator.

4. In this mode, the operand is in general purpose register.
MOV is the operation.
B is the source of data.
A is the destination.
MOV A, B
Move the contents of register B to A.

5. In this mode, the address of operand
is specified by a register pair.
MOV A, M Move data from memory location
specified by H-L pair to accumulator.
MOV is the operation.
M is the memory location specified by
H-L register pair.
A is the destination.

6.  In this mode, the operand is specified
within the instruction itself.
MVI A, 05 H Move 05 H in accumulator.
 MVI is the operation.
 05 H is the immediate data (source).
 A is the destination.

7.  If address of source of data as well as address of
destination of result is fixed, then there is no need to
give any operand along with the instruction.
CMA Complement accumulator.
 CMA is the operation.
 A is the source.
 A is the destination.

8. Timing diagram of 8080

9. Timing diagram is the display of initiation of read/write and
transfer of data operations under the control of 3-status signals IO /
M , S1, and S0.
As the heartbeat is required for the survival of the human being,
the CLK is required for the proper operation of different sections of
the microprocessors. All actions in the microprocessor is controlled
by either leading or trailing edge of the clock.
μP performs fetch
operation to read the instruction or data
and then execute the instruction.

10. The 3-status signals : IO / M, S1, and S0 are generated at the
beginning of each machine cycle. The unique combination of these 3-
status signals identify read or write operation and remain valid for
the duration of the cycle.

11.  Instruction Cycle (IC)
 Fetch cycle (FC)
 Execute Cycle (EC)
Instruction Cycle (IC) = Fetch cycle (FC) + Execute Cycle (EC)

12. Instruction Cycle (IC)
Instruction cycle is defined as the time required to fetch and
execute an instruction.
Fetch cycle (FC) & Execute Cycle (EC)
When μP performing the fetch and execute operations are
called fetch and execute cycle.