This document summarizes a research paper that proposes a novel cluster-based routing protocol for sensor networks aimed at pollution monitoring. The protocol aims to optimize routes while maintaining moderate energy efficiency. It first discusses challenges in sensor network routing related to dynamic topology and limited device power. It then outlines two lemmas: 1) reducing cluster head detection time can decrease routing time; and 2) changing cluster heads randomly over time can improve network lifetime. The proposed protocol selects cluster heads randomly based on energy levels and predicts cluster heads to reduce overhead. It aims to optimize routing time and energy efficiency through these techniques.
Process RTK Data Based On Kalman Filtering AlgorithmIJRES Journal
With the development of satellite positioning technology, there is a strong need for high accuracy
position information. Currently the most widely used high-precision positioning technology is RTK(Real-Time
Kinematic).RTK technology is the key to using carrier phase measurements. It takes advantage of the base
stations and monitor stations observed error of spatial correlation, except monitor stations observed by means of
differential most of the errors in the data, in order to achieve high accuracy positioning.[3]Based on Kalman
filtering algorithm to handle the noise of RTK data and selecting appropriate models to further improve the
accuracy of the data. This paper will explore the use of Kalman filtering method of RTK data processing, which
reduces random noise interference, thus improving the accuracy of GNSS deformation monitoring data.[1]
Acceleration of the Longwave Rapid Radiative Transfer Module using GPGPUMahesh Khadatare
This poster presents Weather Research and Forecast (WRF)
model is a next-generation mesoscale numerical weather
prediction system designed to serve both operational forecasting
and atmospheric research communities. WRF offers multiple
physics options, one of which is the Long-Wave Rapid Radiative
Transfer Model (RRTM). Even with the advent of large-scale
parallelism in weather models, much of the performance increase
has came from increasing processor speed rather than increased
parallelism. We present an alternative method of scaling model
performance by exploiting emerging architectures like GPGPU
using the fine-grain parallelism. We claim to get much more than
23.71x, performance gain by using asynchronous data transfer,
use of texture memory and the techniques like loop unrolling.
DESIGN OF DELAY COMPUTATION METHOD FOR CYCLOTOMIC FAST FOURIER TRANSFORMsipij
In this paper the Delay Computation method for Common Sub expression Elimination algorithm is being implemented on Cyclotomic Fast Fourier Transform. The Common Sub Expression Elimination algorithm is combined with the delay computing method and is known as Gate Level Delay Computation with Common Sub expression Elimination Algorithm. Common sub expression elimination is effective
optimization method used to reduce adders in cyclotomic Fourier transform. The delay computing method is based on delay matrix and suitable for implementation with computers. The Gate level delay computation method is used to find critical path delay and it is analyzed on various finite field elements. The presented algorithm is established through a case study in Cyclotomic Fast Fourier Transform over finite field. If Cyclotomic Fast Fourier Transform is implemented directly then the system will have high additive complexities. So by using GLDC-CSE algorithm on cyclotomic fast Fourier transform, the additive
complexities will be reduced and also the area and area delay product will be reduced.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Area, Delay and Power Comparison of Adder TopologiesVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.
Process RTK Data Based On Kalman Filtering AlgorithmIJRES Journal
With the development of satellite positioning technology, there is a strong need for high accuracy
position information. Currently the most widely used high-precision positioning technology is RTK(Real-Time
Kinematic).RTK technology is the key to using carrier phase measurements. It takes advantage of the base
stations and monitor stations observed error of spatial correlation, except monitor stations observed by means of
differential most of the errors in the data, in order to achieve high accuracy positioning.[3]Based on Kalman
filtering algorithm to handle the noise of RTK data and selecting appropriate models to further improve the
accuracy of the data. This paper will explore the use of Kalman filtering method of RTK data processing, which
reduces random noise interference, thus improving the accuracy of GNSS deformation monitoring data.[1]
Acceleration of the Longwave Rapid Radiative Transfer Module using GPGPUMahesh Khadatare
This poster presents Weather Research and Forecast (WRF)
model is a next-generation mesoscale numerical weather
prediction system designed to serve both operational forecasting
and atmospheric research communities. WRF offers multiple
physics options, one of which is the Long-Wave Rapid Radiative
Transfer Model (RRTM). Even with the advent of large-scale
parallelism in weather models, much of the performance increase
has came from increasing processor speed rather than increased
parallelism. We present an alternative method of scaling model
performance by exploiting emerging architectures like GPGPU
using the fine-grain parallelism. We claim to get much more than
23.71x, performance gain by using asynchronous data transfer,
use of texture memory and the techniques like loop unrolling.
DESIGN OF DELAY COMPUTATION METHOD FOR CYCLOTOMIC FAST FOURIER TRANSFORMsipij
In this paper the Delay Computation method for Common Sub expression Elimination algorithm is being implemented on Cyclotomic Fast Fourier Transform. The Common Sub Expression Elimination algorithm is combined with the delay computing method and is known as Gate Level Delay Computation with Common Sub expression Elimination Algorithm. Common sub expression elimination is effective
optimization method used to reduce adders in cyclotomic Fourier transform. The delay computing method is based on delay matrix and suitable for implementation with computers. The Gate level delay computation method is used to find critical path delay and it is analyzed on various finite field elements. The presented algorithm is established through a case study in Cyclotomic Fast Fourier Transform over finite field. If Cyclotomic Fast Fourier Transform is implemented directly then the system will have high additive complexities. So by using GLDC-CSE algorithm on cyclotomic fast Fourier transform, the additive
complexities will be reduced and also the area and area delay product will be reduced.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Area, Delay and Power Comparison of Adder TopologiesVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
Multi-core GPU – Fast parallel SAR image generationMahesh Khadatare
This poster presents a design for parallel processing of synthetic
aperture radar (SAR) data using multi-core Graphics Processing
Units (GP-GPUs). In this design a two-dimensional image is
reconstructed from received echo pulses and their corresponding
response values. Then the comparative performance of proposed
parallel algorithm implementation is tabulated using different set of
nvidia GPUs i.e. GT, Tesla and Fermi. Analyzing experimentation
results on image of various size 1,024 x 1,024 pixels to 4,096 x
4,096 pixels led us to the conclusion that that nvidia Fermi S2050 have
maximum performance throughput .
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLIJSRD
All processor consisting ALU and adder plays important role for design of ALU. Design of low area and power efficient adder helps to reduce power consumption and area of any processor. Now a day’s major area of research in VLSI system is design of area, high speed and low power data path logic systems. In digital adders, the speed of addition is restricted by the time necessary to send a carry signal through the adder. The area and power consumption is reduced by modifying regular CSLA architecture. The proposed architecture is developed with the help of a simple ripple carry adder (RCA) and gate-level architecture. It consists of single RCA which improves the performance of the proposed designs then the regular designs in terms of power consumption and area.
128-Bit Area Efficient Reconfigurable Carry Select Adder ijcisjournal
Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall
performance of the system. Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing
processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that
there is scope for reducing the area and power consumption in the CSLA. In this paper, we proposed an
area-efficient carry select adder by sharing the common Boolean logic term. After logic optimization and
sharing partial circuit, we only need one XOR gate and one inverter gate for sum generation. Through the
multiplexer, we can select the final-sum only and for carry selection we need only one AND gate and one
OR gate. Based on this modification 16-, 32-, 64-, and 128-bit CSLA architecture have been developed and
compared with the conventional CSLA architecture. The proposed design greatly reduces the area
compared to other CSLAs. From this improvement, the gate count of a 128-bit carry select adder can be
reduced from 3320 to 1664. The proposed structure is implemented in Artix-7 FPGA. Compared with the
proposed design, the conventional CSLA has 65.80% less area.
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesEditor IJMTER
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the
problem of carry propagation delay by independently generating multiple carries and then select a
carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit
but also less area and low power arithmetic units are needed. The modified CSLA architecture has
developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which
replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in
Xilinx 13.2 with reference to FPGA device XC3S500E.
Enhanced Mobile Node Tracking With Received Signal Strength in Wireless Senso...IOSR Journals
Node localization is important parameter in WSN. Node localization is required to report origin of
events which makes it one of the important challenges in WSN. Received signal strength (RSS) is used to
calculate distance between mobile node and reference node. The position of the mobile node is calculated using
multilateration algorithm (MA). Extended Kalman filter (EKF) is utilized to estimate the actual position. In this
paper, the implementation and enhancement of a tracking system based on RSS indicator with the aid of an
Extended Kalman Filter (EKF) is described and an adaptive filter is derived.
Performance Analysis of Differential Beamforming in Decentralized NetworksIJECEIAES
This paper proposes and analyzes a novel differential distributed beamforming strategy for decentralized two-way relay networks. In our strategy, the phases of the received signals at all relays are synchronized without requiring channel feedback or training symbols. Bit error rate (BER) expressions of the proposed strategy are provided for coherent and differential M-PSK modulation. Upper bounds, lower bounds, and simple approximations of the BER are also derived. Based on the theoretical and simulated BER performance, the proposed strategy offers a high system performance and low decoding complexity and delay without requiring channel state information at any transmitting or receiving antenna. Furthermore, the simple approximation of the BER upper bound shows that the proposed strategy enjoys the full diversity gain which is equal to the number of transmitting antennas.
VLSI Implementation of 32-Bit Unsigned Multiplier Using CSLA & CLAAIJMTST Journal
In this project we are going to compare the performance of different adders implemented to the multipliers based on area and time needed for calculation. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31 % by the CSLA based multiplier to complete the multiplication operation.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Improved Timing Estimation Using Iterative Normalization Technique for OFDM S...IJECEIAES
Conventional timing estimation schemes based on autocorrelation experience perfor- mance degradation in the multipath channel environment with high delay spread. To overcome this problem, we proposed an improvement of the timing estimation for the OFDM system based on statistical change of symmetrical correlator. The new method uses iterative normalization technique to the correlator output before the detection based on statistical change of symmetric correlator is applied. Thus, it increases the detection probability and achieves better performance than previously published methods in the multipath environment. Computer simulation shows that our method is very robust in the fading multipath channel.
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
Multi-core GPU – Fast parallel SAR image generationMahesh Khadatare
This poster presents a design for parallel processing of synthetic
aperture radar (SAR) data using multi-core Graphics Processing
Units (GP-GPUs). In this design a two-dimensional image is
reconstructed from received echo pulses and their corresponding
response values. Then the comparative performance of proposed
parallel algorithm implementation is tabulated using different set of
nvidia GPUs i.e. GT, Tesla and Fermi. Analyzing experimentation
results on image of various size 1,024 x 1,024 pixels to 4,096 x
4,096 pixels led us to the conclusion that that nvidia Fermi S2050 have
maximum performance throughput .
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLIJSRD
All processor consisting ALU and adder plays important role for design of ALU. Design of low area and power efficient adder helps to reduce power consumption and area of any processor. Now a day’s major area of research in VLSI system is design of area, high speed and low power data path logic systems. In digital adders, the speed of addition is restricted by the time necessary to send a carry signal through the adder. The area and power consumption is reduced by modifying regular CSLA architecture. The proposed architecture is developed with the help of a simple ripple carry adder (RCA) and gate-level architecture. It consists of single RCA which improves the performance of the proposed designs then the regular designs in terms of power consumption and area.
128-Bit Area Efficient Reconfigurable Carry Select Adder ijcisjournal
Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall
performance of the system. Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing
processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that
there is scope for reducing the area and power consumption in the CSLA. In this paper, we proposed an
area-efficient carry select adder by sharing the common Boolean logic term. After logic optimization and
sharing partial circuit, we only need one XOR gate and one inverter gate for sum generation. Through the
multiplexer, we can select the final-sum only and for carry selection we need only one AND gate and one
OR gate. Based on this modification 16-, 32-, 64-, and 128-bit CSLA architecture have been developed and
compared with the conventional CSLA architecture. The proposed design greatly reduces the area
compared to other CSLAs. From this improvement, the gate count of a 128-bit carry select adder can be
reduced from 3320 to 1664. The proposed structure is implemented in Artix-7 FPGA. Compared with the
proposed design, the conventional CSLA has 65.80% less area.
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesEditor IJMTER
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the
problem of carry propagation delay by independently generating multiple carries and then select a
carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit
but also less area and low power arithmetic units are needed. The modified CSLA architecture has
developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which
replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in
Xilinx 13.2 with reference to FPGA device XC3S500E.
Enhanced Mobile Node Tracking With Received Signal Strength in Wireless Senso...IOSR Journals
Node localization is important parameter in WSN. Node localization is required to report origin of
events which makes it one of the important challenges in WSN. Received signal strength (RSS) is used to
calculate distance between mobile node and reference node. The position of the mobile node is calculated using
multilateration algorithm (MA). Extended Kalman filter (EKF) is utilized to estimate the actual position. In this
paper, the implementation and enhancement of a tracking system based on RSS indicator with the aid of an
Extended Kalman Filter (EKF) is described and an adaptive filter is derived.
Performance Analysis of Differential Beamforming in Decentralized NetworksIJECEIAES
This paper proposes and analyzes a novel differential distributed beamforming strategy for decentralized two-way relay networks. In our strategy, the phases of the received signals at all relays are synchronized without requiring channel feedback or training symbols. Bit error rate (BER) expressions of the proposed strategy are provided for coherent and differential M-PSK modulation. Upper bounds, lower bounds, and simple approximations of the BER are also derived. Based on the theoretical and simulated BER performance, the proposed strategy offers a high system performance and low decoding complexity and delay without requiring channel state information at any transmitting or receiving antenna. Furthermore, the simple approximation of the BER upper bound shows that the proposed strategy enjoys the full diversity gain which is equal to the number of transmitting antennas.
VLSI Implementation of 32-Bit Unsigned Multiplier Using CSLA & CLAAIJMTST Journal
In this project we are going to compare the performance of different adders implemented to the multipliers based on area and time needed for calculation. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31 % by the CSLA based multiplier to complete the multiplication operation.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Improved Timing Estimation Using Iterative Normalization Technique for OFDM S...IJECEIAES
Conventional timing estimation schemes based on autocorrelation experience perfor- mance degradation in the multipath channel environment with high delay spread. To overcome this problem, we proposed an improvement of the timing estimation for the OFDM system based on statistical change of symmetrical correlator. The new method uses iterative normalization technique to the correlator output before the detection based on statistical change of symmetric correlator is applied. Thus, it increases the detection probability and achieves better performance than previously published methods in the multipath environment. Computer simulation shows that our method is very robust in the fading multipath channel.
Channel Estimation Scheme for the Enhanced Reliability in the Flying Ad-hoc N...IJERA Editor
This paper proposes the improved channel estimation for flying ad-hoc network (FANET). The FANET means the wireless communication network between the unmanned aerial vehicle (UAV). UAVs have unlimited availability not only in war but in various fields such as reconnaissance, observation, exploration. Due to the high-mobility of the UAVs, these channels of the FANET environment are very dynamic and time varying channel. Because the FANET for UAV transfers data such as the information on mission accomplishment, collision prevention, etc., the FANET requires the robust and spectral efficient communication scheme in the fading channel. IEEE 802.11p is considered as a communication method between UAVs. However, IEEE 802.11p suffers from the challenge of robust channel estimation due to rapid time-varying nature of the channel. In the IEEE 802.11p, the long training symbols are used for fine synchronization and channel estimation. This channel estimation scheme isn’t suitable in the time varying channel. This paper proposes the scheme that uses the pilot symbols and recovered symbols to estimate channel. The proposed scheme can provide the reliable wireless communication for the FANET
Multiple Downlink Fair Packet Scheduling Scheme in Wi-MaxEditor IJCATR
IEEE 802.16 is standardization for a broadband wireless access in network metropolitan area network (MAN). IEEE 802.16
standard (Wi-Max) defines the concrete quality of service (QoS) requirement, a scheduling scheme and efficient packet scheduling
scheme which is necessary to achieve the QoS requirement. In this paper, a novel waiting queue based on downlink bandwidth
allocation architecture from a number of rtps schedule has been proposed to improve the performance of nrtPS services without any
impaction to other services. This paper proposes an efficient QoS scheduling scheme that satisfies both throughput and delay guarantee
to various real and non-real applications corresponding to different scheduling schemes for k=1,2,3,4. Simulation results show that
proposed scheduling scheme can provide a tight QoS guarantee in terms of delay for all types of traffic as defined in WiMax standards.
This process results in maintaining the fairness of allocation and helps to eliminate starvation of lower priority class services. The
authors propose a new efficient and generalized scheduling schemes for IEEE 802.16 broadband wireless access system reflecting the
delay requirements.
Area efficient parallel LFSR for cyclic redundancy check IJECEIAES
Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr AlgorithmIJERA Editor
Error correcting codes are used to correct the data from the corrupted signal due to noise and interference. There
are many error correcting codes. Among them turbo codes is considered to be the best because it is very close to
the Shannon theoretical limit. The MAP algorithm is commonly used in the turbo decoder. Among the different
versions of the MAP algorithm Constant log BCJR algorithm have less complexity and good error performance.
The Constant log BCJR algorithm can be easily designed using look up table which reduces the memory
consumption. The proposed Constant log BCJR decoder is designed to decode two blocks of data at a time, this
increases the throughput. The complexity of the decoder is further reduced by the use of the add compare select
(ACS) units and registers. The proposed decoder is simulated using Xilinx ISE and synthesized using Sparten3
FPGA and found out that Constant log BCJR decoder utilized less amount of memory and power than the LUT
log BCJR decoder.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.