A low complexity turbo decoder architecture for energy-efficient wireless sensor networks
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This paper proposes a novel low-complexity architecture for turbo decoders that decomposes lookup table-log-BCJR architectures into their fundamental add compare select (ACS) operations. The paper demonstrates that their ACS unit employs an order of magnitude fewer gates than recent LUT-Log-BCJR architectures, facilitating a 71% reduction in energy consumption. Compared to state-of-the-art maximum logarithmic Bahl-Cocke-Jelinek-Raviv implementations, the approach provides a 10% reduction in overall energy consumption at ranges above 58 meters.
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Design of Low Power Energy Efficient Carry Select Adder Using CMOS Technology
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This paper presents a recursive designing approach for high energy efficient carry select adder (CSA). Nowadays, the portable equipment’s like mobile phones and laptops have higher demands in the market. So, the designers must focus greater attention while designing such devices. Which means that have the devices must have lesser power consumption, low cost and have a better performance. The customers mainly focus on the equipment’s which have lesser power consumption, low cost and better performance. As we all know that the adders are the basic building block of microprocessors. The performance of the adders greatly influences the performance of those processors. The carry select adder is most suitable among other adders which have fast addition operation at low cost. The carry select adder (CSA) consists of chain full adders (FAs) and multiplexers. Here a carry select adder is designed with four FAs and four multiplexers. The proposed structure is assessed by the power consumption of the carry select adder using a 32-nm static CMOS technology for a wide range of supply voltages. The simulation results are obtained using Tanner EDA which reveals that the carry select adder has low power consumption.A Review of Low Power Novel Gate Design
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International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
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structures based upon through put requirements. Due to
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portable devices, low power and high performance designs are of
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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
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This document discusses key characteristics of thermal power plants, including:
1. Input-output characteristics, which is a fundamental curve that plots the plant's fuel input in Btu/hour versus power output in MW.
2. Heat rate characteristics, which is the ratio of fuel input to energy output measured in Btu/KWh, and is the slope of the input-output curve. A lower heat rate means higher fuel efficiency.
3. Incremental fuel rate and cost curves, where incremental fuel rate is the change in fuel input divided by the change in output, and incremental cost is the product of incremental fuel rate and fuel cost per unit.
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International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
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CPUs in general-purpose personal computers, such as desktops and laptops, dissipate significantly more power in the order of few watts because of their higher complexity and speed. ALU is a fundamental building block of CPU. It does all process related to arithmetic and logic operations. As the operations become more complex, the ALU become more complex, more expensive, takes up more space in the CPU and contributes more power dissipation within the CPU. Hence power consumption of ALU is a major issue in the designing of CPU.
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— Parallel Prefix adders have been one of the most
notable among several designs proposed in the past. The
advantage of utilizing the flexibility in implementing these
structures based upon through put requirements. Due to
continuing integrating intensity and the growing needs of
portable devices, low power and high performance designs are of
prime importance. The classical parallel prefix adder structures
presented in the literature over the years optimize for logic depth,
area, and fan-out and interconnect count of logic circuits. In this
proposed system, Kogge-Stone adder which is one of types of
parallel prefix adder is used. Kogge stone is the fastest adder
because of its minimum fan-out. When parallel prefix adder is
compared with classical adders it is advantageous in every aspect.
The study reveals that Parallel Prefix adder has the least power
delay product when compared with its peer existing adder
structures (Ripple carry adder, Carry save adders etc).
Simulation results are verified using Xilinx 10.1 and
MODELSIM 6.4a softwares.What's hot (16)
Implementation of Area Effective Carry Select Adders
Implementation of Area Effective Carry Select Adders
ENERGY EFFICIENT VIRTUAL NETWORK EMBEDDING FOR CLOUD NETWORKS
ENERGY EFFICIENT VIRTUAL NETWORK EMBEDDING FOR CLOUD NETWORKS
Input output , heat rate characteristics and Incremental cost
Input output , heat rate characteristics and Incremental cost
Project report on design & implementation of high speed carry select adder
Project report on design & implementation of high speed carry select adder
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This document describes the design and implementation of a high-speed on-chip monitoring circuit using a SAR-based comparator. It discusses a 10-bit pipelined analog-to-digital converter that uses a pipeline comparator architecture to achieve high speed and resolution. The design uses dynamic amplifiers in the multiplying digital-to-analog converters to enable high-speed operation even at low supply voltages. A 16-bit prototype achieves 160 MS/s conversion rate at 0.55V supply voltage. The document also reviews various comparator architectures and identifies current-mode algorithmic comparators as well as operating transistors in subthreshold region as promising approaches for achieving very low power consumption suitable for applications such as distributed sensor networks.
Low power architecture of logic gates using adiabatic techniques
The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.
A Survey on Low Power VLSI Designs
In today’s modern electronics industries energy or power efficiency is most important feature to increase the speed, portability, reliability, popularity and efficiency of electronic products. Reduction in power consumption or low power requirement for a system adds features of low cost, high speed, more efficiency and reliability. CMOS technology is a popular name in the field of low power systems. In the field of CMOS technology various methods are used to make the systems more power efficient like, use of Sleepy transistors, Stack method in which transistor length or width is increased to get reduction in leakage power, use of pre-computation technique with the use of BDD (Binary Decision Diagram), use of SRAM (Static Random Access Memory) for high speed operations. In this paper we survey low power systems in which various techniques are used to reduce the power consumption in different circuit areas of the system to get more power efficient and cost effective electronic systems.
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This document analyzes the energy dissipation of digital half band filters operated in the sub-threshold region with throughput constraints. It explores various architectures of a 12-bit half band filter including the basic implementation and unfolded structures. Simulation results show that the unfolded by 2 architecture dissipates 22% less energy per sample compared to the original filter, making it the most energy efficient. The unfolded by 4 architecture best meets throughput requirements of 120K-1M samples/sec, dissipating less energy than other implementations in this speed range.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
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reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
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and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
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comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Ultralow energy variation-aware design adder architecture study
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Low Power LC-Quadrature VCO with Superior Phase Noise Performance in 0.13 μmR...
The presented work intends to encounter the challenge of optimizing frequency tracking
in the C-band WLAN spectrum, with a tuning range and phase noise (PN)
performance. A Quadrature Voltage Controlled Oscillator (QVCO) design in 130 nm
CMOS technology has been presented to cover the most sought WLAN/WiFi spectrum
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on-chip inductor implementation. To provide better compensation of LC losses at
reduced power dissipation, a cross-coupled structure combining NMOS and PMOS
has been used.We have run an extensive simulation using the industry-standard ADS
(Keysight technology) platform. The simulation study attributed to the superior phase
noise performance of − 160 dBc/Hz at 1 MHz (near f max) at a power dissipation
of 6.52 mW from 1.2 V supply. With the moderate voltage tuning range, the entire
desired frequency span of 5.400–5.495 GHz was obtained with a fairly high resolution
of 2.375 MHz/1 mV, which allows serving a larger crowd for this spectrum. A
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provides a well-established Figure of Merit (FOM) of − 187 dB. Finally, a comparison
study in terms of power dissipation, phase noise, tuning range, voltage tuning,
and Kvco is performed to demonstrate that the provided work is considerably more
significant than traditional efforts.
Energy Efficient Design of Multiplexer Using Adiabatic logic
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
Ijciet 10 02_068
Programmable reversible logic is growing for a potential logic design type
concerning execution around advanced nanotechnology as well as quantum computing
with minimum effect upon circuit temperature production. Current improvements in
reversible logic utilizing additionally quantum computer calculations permit enhanced
computer structure plus arithmetical logic unit layouts. Since reversible circuits
continue to be fairly unique, the most significant study effect is found on the synthesis
of these circuits. Quantum-dot cellular automata (QCA) can be a promising part of
investigating at reversible computing. QCA-based design of the reversible 1-bit full
adder is using the Toffoli and Feynman gates have been achieved in this study. We
develop an improved reversible full adder with overflow detection to enhance
reliability. This component promises to complete the fundamental mathematical
functions of addition, subtraction alongside overflow detection, comparison, along with
logic procedures such as significance. Thus our design is very efficient and versatile
alongside lower quantity of lines as well as quantum cost. This work understands and
nurtures the necessity of reversible full adder for future revolutionary computing
technologies. In this paper, a reversible 1-bit full adder is proposed and compared with
other reversible full adders. Proposed gate performs better than existing methods and
ensures maximum logical operations like the full adder, full with less quantum cost
where other existing gates are not viable.
Analysis Of Optimization Techniques For Low Power VLSI Design
This document summarizes optimization techniques for low power VLSI design. It discusses that power management is a key challenge in deep sub-micrometer designs due to increased complexity. It surveys state-of-the-art optimization methods at different levels of abstraction that target designing low power digital circuits. These include techniques at the technology level like multi-threshold CMOS and multi-supply voltages. At the circuit level, transistor sizing and at the logic level, techniques like don't-care optimization, path balancing, and factorization are discussed to reduce switching activity and power dissipation.
IRJET- A Novel Design of Hybrid 2 Bit Magnitude Comparator
This document proposes and evaluates several novel hybrid circuit designs for a 2-bit magnitude comparator that aim to reduce power consumption. It first describes existing comparator circuit designs using different logic styles and their limitations. It then introduces four new hybrid designs that combine Pass Transistor Logic (PTL) and Gate Diffusion Input (GDI) styles, and incorporates a Self Controllable Voltage Level (SVL) technique to further reduce power. Simulation results show the PTL-GDI 4 design with SVL achieves the greatest power reduction compared to conventional designs, demonstrating over 50% lower power consumption.
Low Power and Area Efficient Multiplier Layout using Transmission Gate
This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr Algorithm
Error correcting codes are used to correct the data from the corrupted signal due to noise and interference. There
are many error correcting codes. Among them turbo codes is considered to be the best because it is very close to
the Shannon theoretical limit. The MAP algorithm is commonly used in the turbo decoder. Among the different
versions of the MAP algorithm Constant log BCJR algorithm have less complexity and good error performance.
The Constant log BCJR algorithm can be easily designed using look up table which reduces the memory
consumption. The proposed Constant log BCJR decoder is designed to decode two blocks of data at a time, this
increases the throughput. The complexity of the decoder is further reduced by the use of the add compare select
(ACS) units and registers. The proposed decoder is simulated using Xilinx ISE and synthesized using Sparten3
FPGA and found out that Constant log BCJR decoder utilized less amount of memory and power than the LUT
log BCJR decoder.
Modified CSKA Application in the Floating Point Adder using Carry Skip Adder ...
In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy
consumption compared with the conventional one. The speed enhancement is achieved by applying
concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv
CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of
AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure maybe
realized with both fixed stage size and variable stage size styles, wherein the latter further improves the
speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed
structure, which lowers the power consumption without considerably impacting the speed, is presented.
This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling
further voltage reduction. The proposed structures are assessed by comparing their speed, power, and
energy parameters with those of other adders using a 45-nmstatic CMOS technology for a wide range of
supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and
38%improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In
addition, the power–delay product was the lowest among the structures considered in this paper, while its
energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with
considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency
CSKA reveal reduction in the power consumption compared with the latest works in this field while having
a reasonably high speed.
HIGH-SPEED LOW-POWER VITERBI DECODER DESIGN FOR TCM DECODERS
This document presents a design for a high-speed low-power Viterbi decoder for trellis coded modulation decoders. It proposes a precomputation architecture incorporated with the T-algorithm to reduce power consumption without significantly degrading decoding speed. The architecture calculates branch metric minimum values in advance and compares them to path metrics to eliminate unlikely paths early. Implementation in Verilog and synthesis results show the proposed architecture operates at a lower supply voltage for moderate throughput applications, achieving quadratic power reduction over conventional decoders.
DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY
Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in 45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.
DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY
Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in
45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high
threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with
the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The
results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any
penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to
Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.
Research Inventy: International Journal of Engineering and Science
This document summarizes a research paper that presents the design of a digitally controlled current-mode DC-DC converter integrated circuit. Key points:
- A charge-pump digital-to-analog converter (CP-DAC) is used to link the digital voltage control loop to the analog current control loop. This allows a reconfigurable digital compensator without sampling the inductor current.
- Experimental results show the converter achieves a response time of 4 microseconds for a 200mA load step using a 0.18um CMOS process. The active area of the controller is small at 0.077mm^2.
- Analysis is presented on limit-cycle oscillations in current-mode control with mixed-
Design and Implementation of Different types of Carry skip adder
The document describes the design and implementation of different types of carry skip adders. It begins with an introduction to carry skip adders and their advantages over other adder types in terms of speed, area usage, and transistor count. It then reviews existing carry skip adder designs and their limitations. A new design called the Common Boolean Logic (CBL) carry skip adder is proposed that aims to reduce area and power consumption by eliminating redundant adder cells through shared logic. Simulation results show that an 8-bit CBL carry skip adder has 64.6% lower power and 18.7% smaller area than a conventional carry skip adder. In conclusion, the CBL carry skip adder achieves improved performance and efficiency.
Similar to A low complexity turbo decoder architecture for energy-efficient wireless sensor networks (20)
IRJET- A Implementation of High Speed On-Chip Monitoring Circuit by using SAR...
IRJET- A Implementation of High Speed On-Chip Monitoring Circuit by using SAR...
Low power architecture of logic gates using adiabatic techniques
Low power architecture of logic gates using adiabatic techniques
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...
Ultralow energy variation-aware design adder architecture study
Ultralow energy variation-aware design adder architecture study
Ultralow energy variation-aware design; adder architecture study
Ultralow energy variation-aware design; adder architecture study
Low Power LC-Quadrature VCO with Superior Phase Noise Performance in 0.13 μmR...
Low Power LC-Quadrature VCO with Superior Phase Noise Performance in 0.13 μmR...
Energy Efficient Design of Multiplexer Using Adiabatic logic
Energy Efficient Design of Multiplexer Using Adiabatic logic
Analysis Of Optimization Techniques For Low Power VLSI Design
Analysis Of Optimization Techniques For Low Power VLSI Design
IRJET- A Novel Design of Hybrid 2 Bit Magnitude Comparator
IRJET- A Novel Design of Hybrid 2 Bit Magnitude Comparator
Low Power and Area Efficient Multiplier Layout using Transmission Gate
Low Power and Area Efficient Multiplier Layout using Transmission Gate
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr Algorithm
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr Algorithm
Modified CSKA Application in the Floating Point Adder using Carry Skip Adder ...
Modified CSKA Application in the Floating Point Adder using Carry Skip Adder ...
HIGH-SPEED LOW-POWER VITERBI DECODER DESIGN FOR TCM DECODERS
HIGH-SPEED LOW-POWER VITERBI DECODER DESIGN FOR TCM DECODERS
DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY
DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY
DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY
DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY
Research Inventy: International Journal of Engineering and Science
Research Inventy: International Journal of Engineering and Science
Design and Implementation of Different types of Carry skip adder
Design and Implementation of Different types of Carry skip adder
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Cloudsim power allocation for statistical qo s provisioning in opportunistic...
The document proposes a power allocation scheme for statistical quality-of-service provisioning in multi-relay cognitive networks. The scheme first chooses between direct transmission or relay transmission based on channel state information. It then performs efficient power allocation according to the transmission mode and given constraints like quality-of-service requirements, average transmit power limits, and peak interference limits. Simulations show the proposed scheme outperforms max-min criterion and equal power allocation policies by achieving higher throughput while involving at most two relays for transmission.
Cloudsim distributed web systems performance forecasting using turning bands...
The document discusses using the Turning Bands method to forecast the performance of distributed web systems. Real-life data was obtained from an experiment monitoring a group of web servers worldwide using an agent system called MWING located in different parts of Poland. The results showed good quality in predicting web performance when European web servers were monitored from an agent in Gliwice, Poland using the Turning Bands method.
Cloudsim distributed processing of probabilistic top-k queries in wireless s...
This document summarizes a paper on distributed processing of probabilistic top-k queries in wireless sensor networks. It introduces the concepts of sufficient and necessary sets, which can facilitate localized data pruning in clusters. It then describes three algorithms - sufficient set-based, necessary set-based, and boundary-based - for intercluster query processing with bounded communication rounds. Finally, it presents an adaptive algorithm that dynamically switches between the three algorithms to minimize transmission cost, and experimental results showing the algorithms significantly reduce data transmission with small constant communication rounds, with the adaptive algorithm performing near-optimally under various conditions.
Civil 2013 titles
This document contains 15 titles for civil engineering projects related to structural analysis. The titles cover topics like analyzing beams, trusses, bridges, dams, storage racks, and auditorium seating under various loads and conditions using techniques like finite element analysis, static analysis, and blast/dynamic analysis. The analyses will determine factors like deflection, stresses, and performance in applications like buildings, transportation, and temporary structures.
Chopper based dc motor speed control
This document discusses using a chopper circuit to control the speed of a DC motor. A chopper circuit uses MOSFETs to vary the voltage applied to the motor, allowing for remote speed control. This method is more efficient and compact than previous variable resistor and transformer-based controls. Pressing buttons on the chopper circuit varies the MOSFET firing angle, decreasing motor speed as the firing angle increases. The chopper control reduces motor current, losses, temperature, noise, and increases motor lifetime compared to DC operation.
Channel assignment for throughput optimization in multichannel multiradio wir...
ECWAY Technologies provides IEEE projects and software development services from its offices in multiple cities across India. The document discusses channel assignment for throughput optimization in ultichannel multiradio wireless mesh networks using network coding. It formulates the joint problem of random network coding, channel assignment, and broadcast link scheduling taking into account factors like opportunistic overhearing, interference constraints, coding constraints, number of channels, radios per node, and fairness among unicast connections. An auction-based suboptimal solution is developed for overall network throughput optimization. Evaluation shows the algorithm can effectively exploit multiple radios and channels and cope with fairness issues from auctions, with promising gains over traditional routing solutions.
Channel allocation and routing in hybrid multichannel multiradio wireless mes...
The document discusses channel allocation and routing in hybrid multichannel multiradio wireless mesh networks. It proposes an Adaptive Dynamic Channel Allocation (ADCA) protocol that considers both throughput and delay optimization in channel assignment. It also proposes an Interference and Congestion Aware Routing (ICAR) protocol for hybrid networks with static and dynamic links that balances channel usage. Simulation results show that ADCA reduces packet delay significantly without degrading throughput, and the hybrid architecture adapts better to changing traffic than static-only architectures with lower overhead and delay than existing hybrid network approaches.
Casual stereoscopic photo authoring
Ecway Technologies provides software development and IEEE projects services from offices located in multiple cities across India. They can be contacted via phone or email on their website at www.ecwayprojects.com.
The paper presents a method for easy stereoscopic photo authoring using a regular monocular camera. It takes two input images or video frames and transforms them into a stereoscopic image pair for pleasant 3D viewing. This is done through a perceptual-plausible image rectification algorithm that warps the input pairs to meet stereoscopic geometric constraints while avoiding visual distortion. The warping uses spatially-varying mesh-based warps that encode various constraints to best meet the stereoscopic geometry and minimize distortion. Experiments show the
Casual stereoscopic photo authoring
Ecway Technologies provides software development and IEEE projects services from offices located in multiple cities across India. They can be contacted via phone or email on their website at www.ecwayprojects.com.
The paper presents a method for easy stereoscopic photo authoring using a regular monocular camera. It takes two input images or video frames and transforms them into a stereoscopic image pair for pleasant 3D viewing. This is done through a perceptual-plausible image rectification algorithm that warps the input pairs to meet stereoscopic geometric constraints while avoiding visual distortion. The warping uses spatially-varying mesh-based warps that encode various constraints to best meet the stereoscopic geometry and minimize distortion. Experiments show the
Capacity of hybrid wireless mesh networks with random a ps
This paper proposes a hybrid wireless mesh network (WMN) architecture that allows the backbone to utilize random connections to access points (APs) in a wireless local area network (WLAN). Theoretical analysis shows that the capacity of a three-tier hybrid WMN is affected by the number of mesh router cells connected to APs, the ratio of access link bandwidth to backbone link bandwidth, and traffic balance among routers with AP access. Simulation results demonstrate that configuring APs and balancing traffic can significantly improve network capacity in the proposed hybrid architecture by taking advantage of wired connections through APs.
Bomb detection robot with wireless camera
This prototype robot is designed to help bomb squads by remotely detecting bombs and obstacles. It uses sensors to detect metals and obstacles as it moves through an area, sending that information back to operators via a wireless camera and computer. The robot is navigated and directed remotely using the camera while its metal detection, obstacle detection, and location data are sent to a base station for operators to monitor on LED displays and sounds.
Bed side patients monitoring system with emergency alert
The document describes a bedside patient monitoring system that measures temperature data using a portable medical monitoring unit. The unit contains a microcontroller, sensor board, and processing system to manage information, analyze data in real-time, and provide warnings for emergencies or abnormal diagnoses. The system takes a patient's temperature, converts it to digital using an ADC, and sends it to the microcontroller for processing. If the temperature exceeds a threshold, the system sounds a buzzer for notification.
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Coloring based inter-wban scheduling for mobile wireless body area networks
Coloring based inter-wban scheduling for mobile wireless body area networks
Code modulation based encryption & decryption technique for secure communicat...
Code modulation based encryption & decryption technique for secure communicat...
Clustering sentence level text using a novel fuzzy relational clustering algo...
Clustering sentence level text using a novel fuzzy relational clustering algo...
Cloudsim t-drive enhancing driving directions with taxi drivers’ intelligence
Cloudsim t-drive enhancing driving directions with taxi drivers’ intelligence
Cloudsim ranking on data manifold with sink points
Cloudsim ranking on data manifold with sink points
Cloudsim quality-differentiated video multicast in multirate wireless networks
Cloudsim quality-differentiated video multicast in multirate wireless networks
Cloudsim power allocation for statistical qo s provisioning in opportunistic...
Cloudsim power allocation for statistical qo s provisioning in opportunistic...
Cloudsim distributed web systems performance forecasting using turning bands...
Cloudsim distributed web systems performance forecasting using turning bands...
Cloudsim distributed processing of probabilistic top-k queries in wireless s...
Cloudsim distributed processing of probabilistic top-k queries in wireless s...
Channel assignment for throughput optimization in multichannel multiradio wir...
Channel assignment for throughput optimization in multichannel multiradio wir...
Channel allocation and routing in hybrid multichannel multiradio wireless mes...
Channel allocation and routing in hybrid multichannel multiradio wireless mes...
Capacity of hybrid wireless mesh networks with random a ps
Capacity of hybrid wireless mesh networks with random a ps
Bed side patients monitoring system with emergency alert
Bed side patients monitoring system with emergency alert
A low complexity turbo decoder architecture for energy-efficient wireless sensor networks
- 1. LOW-COMPLEXITY TURBO DECODER ARCHITECTURE FOR ENERGY-EFFICIENT WIRELESS SENSOR NETWORKS ABSTRACT: Turbo codes have recently been considered for energy-constrained wireless communication applications, since they facilitate low transmission energy consumption. However, in order to reduce the overall energy consumption, lookup table-log-BCJR (LUTLog-BCJR) architectures having low processing energy consumption are required. In this paper, we decompose the LUT-Log-BCJR architecture into its most fundamental add compare select (ACS) operations and perform them using a novel low-complexity ACS unit. We demonstrate that our architecture employs an order of magnitude fewer gates than the most recent LUT-Log-BCJR architectures, facilitating a 71% energy consumption reduction. Compared to state-of-the-art maximum logarithmic Bahl-Cocke-Jelinek-Raviv implementations, our approach facilitates a 10% reduction in the overall energy consumption at ranges above 58 m.