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VHDL 360©

by: Mohamed Samy
  Samer El-Saadany
Copyrights
Copyright © 2010 to authors. All rights reserved
• All content in this presentation, including charts, data, artwork and
  logos (from here on, "the Content"), is the property of Mohamed
  Samy and Samer El-Saadany or the corresponding owners,
  depending on the circumstances of publication, and is protected by
  national and international copyright laws.
• Authors are not personally liable for your usage of the Content that
  entailed casual or indirect destruction of anything or actions entailed
  to information profit loss or other losses.
• Users are granted to access, display, download and print portions of
  this presentation, solely for their own personal non-commercial use,
  provided that all proprietary notices are kept intact.
• Product names and trademarks mentioned in this presentation
  belong to their respective owners.


                                 VHDL 360 ©                    2
Module 3

Data Types and Operators
Objective
• Introducing Data Types & Operators
• Skills gained:
  – Familiarity with data types
  – Modeling Memories
  – More on Expressions & Operators




                    VHDL 360 ©         4
Outline
• Data Types
    – Scalar types
    – Composite types
•   Modeling Memories
•   Expressions & Operators
•   Aggregate
•   Attributes
•   Lab

                        VHDL 360 ©   5
Data Types
• A type is characterized by a set of values and operations
• Type declaration is made inside architecture
  declaration, package, entity
  declaration, subprogram, process declaration
• Types
   – Scalar types
       •   integer types
       •   floating point types
       •   enumerated types
       •   physical types
   – Composite types
       • array types: Multiple elements of the same type
       • record types: Multiple elements of different types


• VHDL offers other types like File types, Access types & Protected
  types, that will be discussed later


                                             VHDL 360 ©        6
Data Types
• VHDL also offers “Subtype” definitions
• Subtypes
     – Type together with a constraint
     – Can use operations defined to its base type
     – Can specify its own set of operations


Golden rules of thumb
VHDL is strongly typed language
i.e. The LHS & RHS of the assignment must match in:
     –   Base type
     –   Size




                                              VHDL 360 ©   7
Scalar Types
• Integer types
    –   <Range> can be one of the following
         <integer> to <integer>
                                                              Syntax:
         <integer> downto <integer>                              type <type_name> is range <range>;
• Predefined integer types:
    – integer type            -2147483648 to 2147483648       Syntax:
    – natural subtype         0 to 2147483648                   subtype <subtype_name> is
                                                                        <basetype_name> range <range>;
    – positive subtype        1 to 2147483648

 Example 1:
PROCESS (X)
  variable a: integer;                                 -- -2147483648 to 2147483648;
  variable b: integer range 0 to 15;                   -- constraints possible values
  type int is range -10 to 10;                         -- defining new integer type
  variable d: int;
  subtype sint is integer range 50 to 127;             -- defining new integer subtype
  variable c: sint;
BEGIN
  a := -1;    c := 100;          -- OK
  b := -1;   d := -12;           -- illegal
  a := 1.0;                      -- illegal
  a := 57;   b := 10; c := a;    -- OK
  c := b;                        -- illegal (current value of b is outside c range)
  d := a;                        -- illegal (two different types)
END PROCESS;
                                                VHDL 360 ©                            8
Scalar Types
• Floating point types
   –   <Range> can be one of the following                    Syntax:
        <floating point> to < floating point >                 type <type_name> is range <range>;
        < floating point > downto < floating point >
• Predefined Floating Point types:                            Syntax:
   – real type             -1.0E308 to 1.0E308                 subtype <subtype_name> is
                                                                       <basetype_name> range <range>;


Example 2:
 PROCESS (X)
   variable a: real;
   type posreal is range 0.0 to 1.0E308;
   variable b: posreal;
 BEGIN
   a := 1.3;    a := -7.5; -- OK
   b := -4.5;   a := 1;     -- illegal
   a := 1.7E13; b := 11.4; -- OK
 END PROCESS;




                                                 VHDL 360 ©                         9
• Enumerated types
                                     Scalar Types
    – specifies list of possible values
                                                                     Syntax:
    – value1, … : identifiers or characters
                                                                      Type <type_name> is (value1, value2, …)
• Predefined Enumerated types:
    – character type                  „a‟, „b‟, …etc*
    – bit type                       „0‟ or „1‟
    – boolean type                   TRUE or FALSE

Example 3:
 ARCHITECTURE test_enum OF test IS
   Type states is (idle, fetch, decode, execute);
   Signal B: states;
 BEGIN
   PROCESS (X)
     TYPE binary IS ( ONN, OFF );
     variable a: binary;
   BEGIN
     a := ONN;       -- ok
     B <= decode;    -- ok
     a := OFF;       -- ok
     B <= halt;      -- illegal
     states <= idle; -- illegal
 END PROCESS;
 END ARCHITECTURE;

   * The 256 characters of the ISO 8859-1: 1987 [B4] character set


                                                        VHDL 360 ©                        10
Reference page

                               Scalar Types
• Physical types represent measurements of                        Syntax:
  some quantity                                                    type <type_name> is range <range>
   –   <primary_unit> an identifier for the primary unit of           units
       measurement for that type                                        <primary_unit>;
   –   <secondary_unit> an integer multiple of the primary unit         <secondary_unit> =
                                                                               <integer> <primary_unit>;
                                                                         …
• Predefined physical types:                                       end units;
   – time type
   – delay_length subtype

Example 4:
 TYPE resistance IS RANGE 0 TO 10000000
 UNITS
   ohm;                   Primary unit
   Kohm = 1000 ohm;
   Mohm = 1000 kohm;     Secondary units
 END UNITS;




                                               VHDL 360 ©                               11
Composite Types
• Array types group elements of the same type
• Arrays can be defined as                   Syntax:
     – Constrained                      <range is specified>
           •   <Range> :   <integer> to <integer>                    Type <type_name> is array <range>
                           <integer> downto <integer>                  of <data_type>;
     – Unconstrained                    <No range is specified>
           •   <Range> : (indexType range <>)

• Multidimensional arrays are created by specifying multiple ranges
Example 5:
                                                                        0                     31
-- constrained array types
type word is array (0 to 31) of bit;                                    7            0
type byte is array (7 downto 0) of bit;
-- constrained multidimensional array type definition
type miniram is array (0 to 15) of std_logic_vector(7 downto 0);
Type matrix is array (0 to 15, 3 downto 0) of std_logic_vector(7 downto 0);
                                                                                 7                 2 1 0
                                                                                                           0
-- unconstrained multidimensional array type definition
type memory is array (INTEGER range <>) of word;                                                           1
                                                                                         .
signal D_bus : word; signal mem1 : miniram;
                                                                                         .
variable x : byte; variable y : bit;
variable my_mem : memory (0 to 1023) ;                                                                     15
my_mem (63) := X"0F58E230";
mem1 (5) <= "10010110" ;
mem1 (15)(4) <= '1' ;
y := x(5);                  -- y gets value of element at index 5
                                                        VHDL 360 ©                       12
Reference page

                     Composite Types
• Record types:                                   Syntax:
   – group elements of possibly different types   type <type_name> is record
                                                     identifier: type;
   – elements are indexed via field names            …
                                                  end record;
Example 6:
 type mycell is record
   rec1 : std_logic_vector( 7 downto 0);
   rec2 : integer;
   rec3 : std_logic;
   rec4 : std_logic_vector( 7 downto 0);
 end record;
 type binary IS ( ONN, OFF );
 type switch_info IS record
   state : BINARY;
   id    : INTEGER;
 end record;

 signal cell : mycell;
 variable switch : switch_info;

 cell.rec1 <=   "11000110";
 cell.rec2 <=   6;
 switch.state   := ONN;
 switch.id :=   30;

                                    VHDL 360 ©                13
Exercise 1 (Modeling Memories)
•     Complete the below code to model a 16x16 ROM by doing the following
       –   Add a rom_type definition which is an array of std_logic_vector
       –   Assign “data” with the proper value of the ROM pointed out by the address

    library ieee;
    use ieee.std_logic_1164.all;
    <Extra packages?>

    entity rom_example is
      port (clk, en : in std_logic;
            addr : in std_logic_vector(3 downto 0);
            data : out std_logic_vector(15 downto 0));
    end entity;
    architecture rtl of rom_example is
      <Add type definition here>
      constant ROM : rom_type:= (X"200A", X"0300", X"0801",   X"0025",
                                 X"0828", X"BCF2", X"0110",   X"1555",
                                 X"3504", X"023B”, X"FFFE",   X"0402",
                                 X"0501", X"0326", X"1300",   X"FFFA");
    begin
    process (clk)
      begin
        if (rising_edge(clk)) then
          if (en = '1') then
            <Add the assignment statement>
          end if;
        end if;
      end process;
    end rtl;




                                                    VHDL 360 ©                         14
Exercise 1 (Soln.)
•   Complete the below code to model a 16x16 ROM by doing the following
     –   Add a rom_type definition which is an array of std_logic_vector
     –   Assign “data” with the proper value of the ROM pointed out by the address

     library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_unsigned.all;
     entity rom_example is
       port (clk, en : in std_logic;
              addr : in std_logic_vector(3 downto 0);
              data : out std_logic_vector(15 downto 0));
     end entity;
     architecture rtl of rom_example is
       type rom_type is array (15 downto 0) of std_logic_vector (15 downto 0);
       constant ROM : rom_type:= (X"200A", X"0300", X"0801", X"0025",
                                   X"0828", X"BCF2", X"0110", X"1555",
                                   X"3504", X"023B", X"FFFE", X"0402",
                                   X"0501", X"0326", X"1300", X"FFFA");
     begin
     process (clk)
       begin
         if (clk'event and clk = '1') then
           if (EN = '1') then
              data <= ROM(conv_integer(ADDR));
           end if;
         end if;
       end process;
     end rtl;




                                                  VHDL 360 ©                         15
•
      Exercise 2 (Modeling Memories)
      Complete the below code to model a 1024x8 RAM by doing the following
       –   Define a ram_type definition which is an array of std_logic_vector
       –   Write data in the RAM in the (we = 1) condition
       –   Read data stored in the RAM location pointed by addr
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    entity mem_example is
    port (clk, we, en : in std_logic;
          addr : in std_logic_vector(9 downto 0);
          data_in : in std_logic_vector(7 downto 0);
          data_out : out std_logic_vector(7 downto 0));
    end entity;
    architecture rtl of mem_example is
      <Add type definition here>
      signal RAM: ram_type;
    begin
      process (clk)
      begin
        if rising_edge(clk) then
          if en = '1' then
             if we = '1' then
               <Add assignment here>
             end if;
             <Add assignment here>
          end if;
        end if;
      end process;
    end rtl;
                                                     VHDL 360 ©                 16
•
                             Exercise 2 (Soln.)
      Complete the below code to model a 1024x8 RAM by doing the following
       –   Define a ram_type definition which is an array of std_logic_vector
       –   Write data in the RAM in the (we = 1) condition pointed by the addr
       –   Read data stored in the RAM location pointed by addr

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    entity mem_example is
    port (clk, we, en : in std_logic;
          addr : in std_logic_vector(9 downto 0);
          data_in : in std_logic_vector(7 downto 0);
          data_out : out std_logic_vector(7 downto 0));
    end entity;
    architecture rtl of mem_example is
      type ram_type is array (1023 downto 0) of std_logic_vector (7 downto 0);
      signal RAM: ram_type;
    begin
      process (clk)
      begin
        if rising_edge(clk) then
          if en = '1' then
             if we = '1' then
               RAM(conv_integer(ADDR)) <= data_in;
             end if;
             Data_out <= RAM(conv_integer(addr)) ;
          end if;
        end if;
      end process;
    end rtl;
                                                     VHDL 360 ©                  17
Contacts
• You can contact us at:
  – http://www.embedded-tips.blogspot.com/




                     VHDL 360 ©         18

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Data types and Operators

  • 1. VHDL 360© by: Mohamed Samy Samer El-Saadany
  • 2. Copyrights Copyright © 2010 to authors. All rights reserved • All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws. • Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses. • Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. • Product names and trademarks mentioned in this presentation belong to their respective owners. VHDL 360 © 2
  • 3. Module 3 Data Types and Operators
  • 4. Objective • Introducing Data Types & Operators • Skills gained: – Familiarity with data types – Modeling Memories – More on Expressions & Operators VHDL 360 © 4
  • 5. Outline • Data Types – Scalar types – Composite types • Modeling Memories • Expressions & Operators • Aggregate • Attributes • Lab VHDL 360 © 5
  • 6. Data Types • A type is characterized by a set of values and operations • Type declaration is made inside architecture declaration, package, entity declaration, subprogram, process declaration • Types – Scalar types • integer types • floating point types • enumerated types • physical types – Composite types • array types: Multiple elements of the same type • record types: Multiple elements of different types • VHDL offers other types like File types, Access types & Protected types, that will be discussed later VHDL 360 © 6
  • 7. Data Types • VHDL also offers “Subtype” definitions • Subtypes – Type together with a constraint – Can use operations defined to its base type – Can specify its own set of operations Golden rules of thumb VHDL is strongly typed language i.e. The LHS & RHS of the assignment must match in: – Base type – Size VHDL 360 © 7
  • 8. Scalar Types • Integer types – <Range> can be one of the following <integer> to <integer> Syntax: <integer> downto <integer> type <type_name> is range <range>; • Predefined integer types: – integer type -2147483648 to 2147483648 Syntax: – natural subtype 0 to 2147483648 subtype <subtype_name> is <basetype_name> range <range>; – positive subtype 1 to 2147483648 Example 1: PROCESS (X) variable a: integer; -- -2147483648 to 2147483648; variable b: integer range 0 to 15; -- constraints possible values type int is range -10 to 10; -- defining new integer type variable d: int; subtype sint is integer range 50 to 127; -- defining new integer subtype variable c: sint; BEGIN a := -1; c := 100; -- OK b := -1; d := -12; -- illegal a := 1.0; -- illegal a := 57; b := 10; c := a; -- OK c := b; -- illegal (current value of b is outside c range) d := a; -- illegal (two different types) END PROCESS; VHDL 360 © 8
  • 9. Scalar Types • Floating point types – <Range> can be one of the following Syntax: <floating point> to < floating point > type <type_name> is range <range>; < floating point > downto < floating point > • Predefined Floating Point types: Syntax: – real type -1.0E308 to 1.0E308 subtype <subtype_name> is <basetype_name> range <range>; Example 2: PROCESS (X) variable a: real; type posreal is range 0.0 to 1.0E308; variable b: posreal; BEGIN a := 1.3; a := -7.5; -- OK b := -4.5; a := 1; -- illegal a := 1.7E13; b := 11.4; -- OK END PROCESS; VHDL 360 © 9
  • 10. • Enumerated types Scalar Types – specifies list of possible values Syntax: – value1, … : identifiers or characters Type <type_name> is (value1, value2, …) • Predefined Enumerated types: – character type „a‟, „b‟, …etc* – bit type „0‟ or „1‟ – boolean type TRUE or FALSE Example 3: ARCHITECTURE test_enum OF test IS Type states is (idle, fetch, decode, execute); Signal B: states; BEGIN PROCESS (X) TYPE binary IS ( ONN, OFF ); variable a: binary; BEGIN a := ONN; -- ok B <= decode; -- ok a := OFF; -- ok B <= halt; -- illegal states <= idle; -- illegal END PROCESS; END ARCHITECTURE; * The 256 characters of the ISO 8859-1: 1987 [B4] character set VHDL 360 © 10
  • 11. Reference page Scalar Types • Physical types represent measurements of Syntax: some quantity type <type_name> is range <range> – <primary_unit> an identifier for the primary unit of units measurement for that type <primary_unit>; – <secondary_unit> an integer multiple of the primary unit <secondary_unit> = <integer> <primary_unit>; … • Predefined physical types: end units; – time type – delay_length subtype Example 4: TYPE resistance IS RANGE 0 TO 10000000 UNITS ohm; Primary unit Kohm = 1000 ohm; Mohm = 1000 kohm; Secondary units END UNITS; VHDL 360 © 11
  • 12. Composite Types • Array types group elements of the same type • Arrays can be defined as Syntax: – Constrained <range is specified> • <Range> : <integer> to <integer> Type <type_name> is array <range> <integer> downto <integer> of <data_type>; – Unconstrained <No range is specified> • <Range> : (indexType range <>) • Multidimensional arrays are created by specifying multiple ranges Example 5: 0 31 -- constrained array types type word is array (0 to 31) of bit; 7 0 type byte is array (7 downto 0) of bit; -- constrained multidimensional array type definition type miniram is array (0 to 15) of std_logic_vector(7 downto 0); Type matrix is array (0 to 15, 3 downto 0) of std_logic_vector(7 downto 0); 7 2 1 0 0 -- unconstrained multidimensional array type definition type memory is array (INTEGER range <>) of word; 1 . signal D_bus : word; signal mem1 : miniram; . variable x : byte; variable y : bit; variable my_mem : memory (0 to 1023) ; 15 my_mem (63) := X"0F58E230"; mem1 (5) <= "10010110" ; mem1 (15)(4) <= '1' ; y := x(5); -- y gets value of element at index 5 VHDL 360 © 12
  • 13. Reference page Composite Types • Record types: Syntax: – group elements of possibly different types type <type_name> is record identifier: type; – elements are indexed via field names … end record; Example 6: type mycell is record rec1 : std_logic_vector( 7 downto 0); rec2 : integer; rec3 : std_logic; rec4 : std_logic_vector( 7 downto 0); end record; type binary IS ( ONN, OFF ); type switch_info IS record state : BINARY; id : INTEGER; end record; signal cell : mycell; variable switch : switch_info; cell.rec1 <= "11000110"; cell.rec2 <= 6; switch.state := ONN; switch.id := 30; VHDL 360 © 13
  • 14. Exercise 1 (Modeling Memories) • Complete the below code to model a 16x16 ROM by doing the following – Add a rom_type definition which is an array of std_logic_vector – Assign “data” with the proper value of the ROM pointed out by the address library ieee; use ieee.std_logic_1164.all; <Extra packages?> entity rom_example is port (clk, en : in std_logic; addr : in std_logic_vector(3 downto 0); data : out std_logic_vector(15 downto 0)); end entity; architecture rtl of rom_example is <Add type definition here> constant ROM : rom_type:= (X"200A", X"0300", X"0801", X"0025", X"0828", X"BCF2", X"0110", X"1555", X"3504", X"023B”, X"FFFE", X"0402", X"0501", X"0326", X"1300", X"FFFA"); begin process (clk) begin if (rising_edge(clk)) then if (en = '1') then <Add the assignment statement> end if; end if; end process; end rtl; VHDL 360 © 14
  • 15. Exercise 1 (Soln.) • Complete the below code to model a 16x16 ROM by doing the following – Add a rom_type definition which is an array of std_logic_vector – Assign “data” with the proper value of the ROM pointed out by the address library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity rom_example is port (clk, en : in std_logic; addr : in std_logic_vector(3 downto 0); data : out std_logic_vector(15 downto 0)); end entity; architecture rtl of rom_example is type rom_type is array (15 downto 0) of std_logic_vector (15 downto 0); constant ROM : rom_type:= (X"200A", X"0300", X"0801", X"0025", X"0828", X"BCF2", X"0110", X"1555", X"3504", X"023B", X"FFFE", X"0402", X"0501", X"0326", X"1300", X"FFFA"); begin process (clk) begin if (clk'event and clk = '1') then if (EN = '1') then data <= ROM(conv_integer(ADDR)); end if; end if; end process; end rtl; VHDL 360 © 15
  • 16. Exercise 2 (Modeling Memories) Complete the below code to model a 1024x8 RAM by doing the following – Define a ram_type definition which is an array of std_logic_vector – Write data in the RAM in the (we = 1) condition – Read data stored in the RAM location pointed by addr library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mem_example is port (clk, we, en : in std_logic; addr : in std_logic_vector(9 downto 0); data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0)); end entity; architecture rtl of mem_example is <Add type definition here> signal RAM: ram_type; begin process (clk) begin if rising_edge(clk) then if en = '1' then if we = '1' then <Add assignment here> end if; <Add assignment here> end if; end if; end process; end rtl; VHDL 360 © 16
  • 17. Exercise 2 (Soln.) Complete the below code to model a 1024x8 RAM by doing the following – Define a ram_type definition which is an array of std_logic_vector – Write data in the RAM in the (we = 1) condition pointed by the addr – Read data stored in the RAM location pointed by addr library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mem_example is port (clk, we, en : in std_logic; addr : in std_logic_vector(9 downto 0); data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0)); end entity; architecture rtl of mem_example is type ram_type is array (1023 downto 0) of std_logic_vector (7 downto 0); signal RAM: ram_type; begin process (clk) begin if rising_edge(clk) then if en = '1' then if we = '1' then RAM(conv_integer(ADDR)) <= data_in; end if; Data_out <= RAM(conv_integer(addr)) ; end if; end if; end process; end rtl; VHDL 360 © 17
  • 18. Contacts • You can contact us at: – http://www.embedded-tips.blogspot.com/ VHDL 360 © 18