1. UNIT I
Basic Language Elements
 Identifiers
 Comments
 Data Objects
 Data Types
 Operators
Delays in VHDL
 Inertial delay
 Transport delay
 Delta delay
VHDL – Basic Language Elements
Identifiers
- Identifiers are used to name items in a VHDL model.
Basic identifier: composed ofa sequence of one or more characters
A basic identifier maycontainonlycapital ‘A’ - ’Z’ , ‘a’ - ’z’,
‘0’ - ’9’, underscore character ‘_’
• first character must be a letter, last character must NOT be anunderscore
• Two underscores cannot occur concurrently
• case insensitive: COUNT, count, Count, counT are all the same
Extended identifier: sequence of characters writtenbetweentwo backslashes
• Anyprintable characters canbe usedincluding %, $, *, etc.
• lower case andupper case are distinct
• examples: 2FOR$, countNow!, &#$(@#&!!!
Keywords can not be usedas basic identifiers

2. Comments
 Its nonexecutable or readable parameter for understandingpurpose.
 The comments to be proceeded bytwo consecutive
hyphens(--)
Data Objects
– holda value ofa specifiedtype
constant:holds a single value of a specifiedtype andcannot be changed throughout the simulatio
constant declaration:
• constant RESULT:BIT:=1; constant FALL_TIME:TIME:=10ns
variable:
holds a single value ofa specifiedtype but can be changed throughout the simulation
• variable ABAR:BIT;variable STATUS:BIT_VECTOR(3 downto0);
signal:
holds a list of values including current value and a list of possible future values
• typicallyusedto model wires andflip-flops
• signal DATA_BUS:BIT_VECTOR(0 to 31)
file:
same as withanycomputer file, contains data
Data Types
– Is a name whichis associatedwith a set of values anda set ofoperations.
 Major types:
• ScalarType
• Composite Type
• Access Type
• File Type
There canalsobe user-definedtypes andsubtypes
A subtype is a type witha (possibly) added constraint
syntax: subtype subtype_name is base_type range range_constraint;
example: subtype DIGITS is integer range 0 to 9;

3. Scalar types
Enumeration – defines a type that hasa set of user-defined values
type std_logic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’,’-’);
‘u’ unspecified, ‘x’ unknown, ‘0’ strong zero, ‘1’ strong one
‘z’ high impedance, ‘w’ weak unknown, ‘l’ weak zero, ‘h’ weakone, ‘-’ don’t care
Integer – valuesfall within the specified integer range
• type REG_SIZEis range 0 to 31
• subtype WORDis REG_SIZE range 0 to 15
Floating Point –real decimaltypes
Physical – represent measurement of some physical quantitylike time, voltage, or current
Composite Types
– a collection ofvalues
Array Types – collectionof values all belonging to a single type
• BIT_VECTOR andSTRING are pre-defined one-dimensional arraytypes
• type DATA_BYTE is array(0 to 7) of BIT;
• type MEMORY is array(0 to 127) of DATA_BYTE;
Record Types – collectionof values that maybelong to different types
type MODULE is
record
SUM:BIT_VECTOR(0 to 7);
COUT:BIT;
end record
Access Type
 Valuesbelonging to anaccess type are pointers to a allocatedobject of some other type.
 Example :
type PTR is access MODULE;

4. File Type
 Objects of file type represent files in the host environment.
 Syntax :
type file_type_name is file of type_name;
Operators
logical operators
• and, or, nand, nor, xor, xnor, not
relational operators
• <, >, =, <=, >=, /= -- /= means not equal to
shift operators
• sll, srl, sla, sra, rol, ror
adding operators
• +, -, & -- & is concatenation
multiplying operators
• *, /, mod, rem
miscellaneous operators
• abs, ** -- ** is exponentiation

5. DELAYS IN VHDL
 VHDL allows signal assignments to include delayspecifications, inthe formof an‘after’ clause.
 The ‘after’ clause allows you to model the behavior of gate anddelays.
 Delay’s are useful insimulation models to estimate delays in synthesizable design.
 Three fundamental delays are
• Inertial delay.
• Transport Delay.
• Delta Delay.
INERTIAL DELAY
 Inertial Delaymodels the delays oftenfoundinswitching circuits (component delays).
 These are default delays.
 Spikes are not propagatedif after clause is used.
 An input value must be stable for an specifiedpulse rejectionlimit durationbefore the value is allowed to propagate
to the output.
 Inertial delayis usedto model component delay.
 Spike of 2ns incmos component withdelayof 10ns is normallynot seen at the output.
 Problemarises ifwe want to model a component withdelayof 10ns, but allspikes at input > 5 ns are visible output.
 Above problemcanbe solvedbyintroducingreject & modelingas follows:
 outp <= reject 5 ns inertial Inp after 10 ns;
TRANSPORT DELAY
 Transport delaymodels the behavior ofa wire, inwhich all pulses (events)are propagated.
 Pulses are propagated irrespective ofwidth.
 Good for interconnect delays.
 Models delays in hardware that doesnot exhibit anyinertial delay.
 Represents pure propagation delay
 Routing delays canbe modeledusing transport delay
Z<= transport a after 10 ns;

6. Delta Delay
 Deltadelayneededtoprovide supportforconcurrentoperationswithzerodelay
 Schedulingof zerodelay devicesrequiresthe delta delay.
 A deltadelayisnecessaryif nootherdelayisspecified.