Getting familiar with code changes' impact on synthesis Skills gained: 1- Writing synthesis friendly code This is part of VHDL 360 course

1. VHDL 360© by: Mohamed Samy Samer El-Saadany

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3. Module 4 Synthesis Examples

4. Objective Getting familiar with code changes' impact on synthesis Skills gained: Writing synthesis friendly code VHDL 360 © 4

5. Outline Introduction Synthesize and Learn Combinational Logic Latch Inference Sequential Logic Flip-Flop Inference VHDL 360 © 5

6. Introduction VHDL 360 © 6 VHDL is a H/W modeling language used to model digital circuits Digital circuits can be either Combinational or Sequential Combinational Logic circuits: Implement Boolean functions whose output is only dependant on the present inputs Sequential Logic circuits: Implement circuits whose output depends on the present inputs & the history of the inputs. i.e. Circuits having storage elements

7. Introduction VHDL 360 © 7 VHDL Standard Synthesizable VHDL Synthesis tools translate the VHDL code to a gate level netlist representing the actual H/W gates [and, or, not, Flip-Flops…etc] Only a subset of the language is synthesizable A model can be either Synthesizable: Used for both Simulation & Synthesis Non-Synthesizable: Used for Simulation only

8. Synthesize And Learn 8

9. Synthesize and Learn In the next slides we will use examples from the previous modules to demonstrate synthesis and study the synthesized logic We will also modify these examples and observe the impact on the synthesized logic 9 VHDL 360 ©

10. Combinational Logic libraryIEEE; useIEEE.std_logic_1164.all; Entitymux_caseis Port(a, b, c, d:instd_logic; Sel:instd_logic_vector(1downto0); F:outstd_logic); Endentity; Architecture rtl ofmux_caseis begin process(a,b,c,d,sel)is begin Caseselis When"00"=> f <= a; When"01"=> f <= b; When"10"=> f <= c; When"11"=> f <= d; whenothers=> f <= a; Endcase; Endprocess; Endarchitecture; VHDL 360 © 10 Example 1: 4x1 Multiplexer

13. Synthesis tools don’t use the sensitivity list to determine the logic, but simulation tools depend on the sensitivity list to execute the process

14. Example 2 suffers a problem called “Simulation – Synthesis mismatch”Example 1: 4x1 Multiplexer Example 2: 4x1 Multiplexer Architecture rtl ofmux_caseis begin process(a, sel)is begin Caseselis When"00"=> f <= a; When"01"=> f <= b; When"10"=> f <= c; When"11"=> f <= d; whenothers=> f <= a; Endcase; Endprocess; Endarchitecture;

16. Combinational Logic 14 VHDL 360 © Example 4: Adder-Subtractor LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITYadd_subIS port(a, b :ininteger; result :outinteger; operation:instd_logic); ENDENTITY; ARCHITECTURE behave OFadd_subIS BEGIN process(a, b, operation) begin if(operation = '1')then result <= a + b; else result <= a - b; endif; endprocess; ENDARCHITECTURE;

17. Combinational Logic 15 VHDL 360 © Consider that someone tries to re-use that code to implement an adder with an enable  He modifies the add_sub example; removes the else branch & renames the “operation” port to “enable” as shown below, How would these changes affect the logic? Example 5: LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY adder IS port(a, b :ininteger; result :outinteger; enable:instd_logic); ENDENTITY adder; ARCHITECTURE behave OF adder IS BEGIN process(a, b, enable) begin if(enable = '1')then result <= a + b; endif; endprocess; ENDARCHITECTURE;

18. Combinational Logic 16 VHDL 360 © This will infer a latch, because we didn’t specify what should happen to “result” when “enable” isn’t equal to '1' Simulation & synthesis tools will just keep the value as is…i.e. It latches the last value Example 5: LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY adder IS port(a, b :ininteger; result :outinteger; enable:instd_logic); ENDENTITY adder; ARCHITECTURE behave OF adder IS BEGIN process(a, b, enable) begin if(enable = '1')then result <= a + b; endif; endprocess; ENDARCHITECTURE;

19. Combinational Logic In the below example, the "11" value of "sel" signal is not listed as a case choice, hence signal "F" is not assigned a value in this case A Latch is inferred in this example  Probably that wasn’t needed Example 6: LIBRARYieee; USEieee.std_logic_1164.all; ENTITYincomplete_caseIS port(sel:std_logic_vector(1downto0); A, B:std_logic; F :outstd_logic); ENDENTITY; ARCHITECTURE rtl OFincomplete_caseIS BEGIN process(sel, A, B) begin case(sel)is when"00"=> F <= A; when"01"=> F <= B; when"10"=> F <= A xor B; whenothers=>null; endcase; endprocess; ENDARCHITECTURE; 17 VHDL 360 ©

20. Skills Check Do you think a Latch would be inferred in the below example? Example 7: LIBRARYieee; USEieee.std_logic_1164.all; ENTITYincomplete_assignmentIS port(sel:instd_logic_vector(1downto0); A, B :instd_logic; O1, O2:outstd_logic); ENDENTITY; ARCHITECTURE rtl OFincomplete_assignmentIS BEGIN process(sel, A, B)begin case(sel)is when"00"=> O1 <= A; O2 <= A and B; when"01"=> O1 <= B; O2 <= A xor B; when"10"=> O1 <= A xor B; when"11"=> O2 <= A or B; whenothers=> O1 <= '0'; O2 <= '0'; endcase; endprocess; ENDARCHITECTURE; 18 VHDL 360 ©

23. Enough CombinationalLet's Go Sequential 21

28. Sequential Logic Example 11: 8-bit Shift Register (Shift right) Libraryieee; useieee.std_logic_1164.all; entity shift_register is Port( clk, D, enable :inSTD_LOGIC; Q :outSTD_LOGIC); endentity; architecture Behavioral of shift_register is begin process(clk) variable reg:std_logic_vector(7downto0); begin ifrising_edge(clk)then if enable = '1' then for i in1to7loop reg(i-1):= reg(i); endloop; reg(7):= d; endif; endif; Q <= reg(0); endprocess; end Behavioral; 7 6 5 4 3 2 1 0 VHDL 360 © 26

29. Flip-Flop Inference Assignments under clock edge where the object value needs to be remembered across multiple process invocations  Flip-Flop Signal assignment under clock edge will always infer a Flip-Flop Variable assignment under clock edge will infer Flip-Flop only when its value ought to be remembered across process invocations 27 VHDL 360 ©

30. Exercise 1 LIBRARYieee; USEieee.std_logic_1164.all; Entity unknown is port(x:outstd_logic; y:instd_logic_vector(3downto0); c:ininteger); Endentity; Architecture behave of unknown is Begin x <= y(c); End behave; VHDL 360 © 28 Deduce what the below code models Use synthesis tool to validate your answer

31. Contacts You can contact us at: http://www.embedded-tips.blogspot.com/ VHDL 360 © 29