This document discusses various counter circuits including decade counters, presettable counters, and counter design using hardware description languages. It provides state tables and circuit diagrams for a decade counter, MOD-5 counter, presettable MOD-8 counter, and asynchronous decade counter. It also discusses using counters to build a digital clock and provides a block diagram. Verilog code is given for a MOD-8 up counter and down counter. The last pages cover important questions on designing various counters.

1. ADE Module-5
Kishore Kumar R RLJIT Page 1
Module-5
Chapter 1: Counters
1.1 Decade Counter
1.2 Presettable Counter
1.3 Counter Design as Synthesis problem
1.4 A Digital Clock
1.5 Counter Design using HDL

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Decade Counter or MOD-10 counter:
A decade counter counts in a sequence of ten and returns back to 0 after the count of
nine. Decade counter can be designed by using MOD-5 and MOD-2 counters.
Designing Mod-5 Counter:
State table
C B A C+1 B+1 A+1 JC KC JB KB JA KB
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
0 0 1
0 1 0
0 1 1
1 0 0
0 0 0
0 ×
0 ×
0 ×
1 ×
× 1
0 ×
1 ×
× 0
× 1
0 ×
1 ×
× 1
1 ×
× 1
0 ×

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MOD-5 Counter Circuit:
Decade Counter (MOD-10):
MOD-10 counter can be designed by cascading MOD-5 counter and adding additional
flip-flop as shown below

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MOD-10 Counter circuit:
Truth table: Timing Waveform:
D C B A Count
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
0
1
2
3
4
8
9
10
11
12
Note: this MOD-10 counter has 10 different states, but count is not in straight sequence
MOD-10 Counter:
To get a count in straight sequence, Decade counter can be designed as shown below.

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Circuit:
Truth Table: Timing Waveforms:
Note: This mod-10 counter has 10 different states, count is in straight sequence
Presettable Counter:
In Presettable counter, user can set initial state of the counter, after initial state, counter
can be made to count either UP or Down.
MOD-8 Presettable counter with initial state =101 (5):
Figure below shows, MOD-8 counter, to set the initial state 101 (5), apply 101 to parallel
inputs P2P1P0 =101, and apply parallel load =0, hence inversion of parallel load 1 will be applied
to one of inputs of all NAND gates, at flip-flop inputs for NAND gate are 11 hence its output 0 is
applied to PRESET of FF-A, hence output of a FF-A is 1, similarly at FF-B PRESET=1 and
CLR=0, hence output of FF-B is 0, and at FF-C PRESET=0 and CLR=1, hence FF-C output is 1,
now state of counter QCQBQA=101, after this state if Parallel Load is made 1, hence all

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PRESET and RESET inputs are deactivated, since counter is designed as UP-counter, it
increments the count by 1 on every negative clock cycle.
Truth Table:
PL P2 P1 P0 QC QB QA
0
1
1
1
1
1
1
1
1 0 1
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0

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Counter Design as Synthesis Problem:
Designing MOD-6 Counter:
State table:
JA =1 and KA=1

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MOD-6 Circuit-Diagram:
Problem: Design self-correcting MOD-6 counter in which all the unused states leads to
state CBA=000
State Table:
Cn Bn An Cn+1 Bn+1 An+1 JC KC JB KB JA KA
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
0 0 0
0 0 0
0 0 0
0 ×
0 ×
0 ×
1 ×
× 0
× 1
× 1
× 1
0 ×
1 ×
× 0
× 1
0 ×
0 ×
× 1
× 1
1 ×
× 1
1 ×
× 1
1 ×
× 1
0 ×
× 1

9. ADE Module-5
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Mod-6 self-correcting circuit:
Problem: Design Self-correcting MOD-5 Synchronous Down counter using JK Flip-Flops,
Assume 100 as next state for all unused states.

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Problem: Design and explain working of Asynchronous decade counter with a suitable
diagram.
To design decade counter which has 10 states, four flip-flops are required, for
Asynchronous UP-counter, output of flip-flop is connected to clock input of next flip-flop, to
have 10 states (0-9), after the state 9(1001) counter should get reset, resetting of counter can be
done using RESET inputs of all flip-flops, in decade counter, RESET input is activated using
NAND gates when state 10 (QDQCQBQA = 1010) occurs.

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Truth table:
Timing waveform:

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Define Counter. Design a synchronous counter for the Sequence 0412604
Using JK Flip-Flop.
State table:
C B A C+1 B+1 A+1 Jc Kc JB KB JA KA
0 0 0
1 0 0
0 0 1
0 1 0
1 1 0
1 0 0
0 0 1
0 1 0
1 1 0
0 0 0
1 X
X 1
0 X
1 X
X 1
0 X
0 X
1 X
X 0
X 1
0 X
1 X
X 1
0 X
0 X

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Circuit:
Problem: Design Modulo-4 irregular counter with following sequence using D-Flip-Flop
Digital Clock:
Counters can be used to construct an ordinary clock which displays hours, minutes and
seconds, power supply to the counter is usually 60Hz 120V ac, when this signal frequency is
divided by 60 we get a clock signal with one cycle per sec, if resulting waveform is divided by
60 again we get one clock cycle per minute, if this resulting waveform is divided by 60 again we
get one cycle per hour,

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Block diagram of digital clock:
The first divide by 60 counter divides 60Hz power signal to 1Hz square waveform, the
second divide by 60 counter changes state on every second, and has 60 discrete states, it can be
used to display seconds and hence referred as seconds counter,
Third divide by 60 counter changes state on every minute, and 60 discrete states, it can be
used to display minutes, and referred as minutes counter.
The last counter changes state on every 60 minutes(hour), if it is divided by 12 it will
have 12 states, that can be decoded to provide signals to display correct hour, this is referred to
as Hours counter.
Counter Design Using HDL:
Program: Write Verilog code for MOD-8 Up counter

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Program: Write Verilog code for MOD-8 down counter
module DC (CLK, PRESET, Q);
input CLK,PRESET;
output [2:0]Q;
reg [2:0]Q;
always @ (negedge clk or negedge PRESET)
If (~PRESET) Q=3’b111;
else Q=Q – 1;
endmodule
Important Questions
1. Define Counter. Design a synchronous counter for the sequence 0412604 using
JK Flip-Flop JAN-17 (12 M)
2. Explain Digital clock with neat diagram JAN&JUL-17 (4 M)
3. Define Counter. Design a synchronous counter for the sequence 0412604 using
SR Flip-Flop JUL-17 (12 M)
4. Design self-correcting MOD-6 Counter.
5. Explain Presettable MOD-8 counter
6. Design and explain working of Decade counter
7. Write Verilog code for MOD-8 Up counter
8. Design MOD-3 counter
9. Design Modulo-4 irregular counter with following sequence using D-Flip-Flop