This document contains the resume of Silpa Pushpan, seeking a job in physical design in ASIC field. It lists her educational qualifications including a postgraduate diploma in ASIC physical design and BTech in electronics and communication. It details her core competencies in areas like ASIC flow, logic design, floorplanning, timing closure etc. It also provides details of her project experience in areas like block implementation, static timing analysis, automation using TCL during her internship.
1. SILPA PUSHPAN
#3, 2nd,5th cross, Maruthi Nagar
Email-id: silpapushpan@gmail.com Madiwala, Bangalore-68
Mobile No. : 9400450514 Pin: 560068
CAREER OBJECTIVE
Seeking a challenging and responsible job in the field of Physical design that will enable
to use my strong skills, knowledge and ability to work well with people, to pave best way for
achieving company's goal.
CORE COMPITANCIES
Basic knowledge in ASIC flow and importance of each block in the flow.
Good knowledge in logic design and the operation and functionality of CMOS and
Transistor
Implemented ASIC flow (netlist to GDSii) at block level with critical power, area and
timing budget.
Designed floor-plans with high macro count and power-planned with strict IR drops
and power budgets.
Synthesized clock tree (CTS) while meeting targets like max skew and min/max
insertion delay.
Generated and analyzed timing reports of per-layout and post-layout STA on Prime
Time with OCV and Xtalk, and resolved timing violations.
Optimized the design for multiple modes and multiple corners (MCMM).
Performed timing closure on technologies with aggressive timing and power budgets.
Good knowledge in logic design and the operation and functionality of CMOS and
Transistor
Knowledge in Verilog and TCL scripting
EDUCATION DETAILS
COURSE INSTITUTION BOARD/UNIVERSITY YEAR OF
COMPLETION
MARK
PG Diploma
(ASIC Physical
Design)
RV-VLSI Design
Center - 2017 -
B.Tech
(Electronics and
Communication
Engineering)
College of
Engineering
Poonjar, Kottayam
Kerala
Cochin University of
Science and
Technology
Kerala
2016 7.5
Diploma in
Engineering
Govt. Polytechnic
College, Palakkad
Board of Technical
education
Kerala
2012 64
Tenth
Darunnajath
English Medium
School
Kerala State Board 2009 94
2. Experience Details
Company Name Designation From To
RV-VLSI Design
Center
Physical Design
Engineer Trainee
July 2016 January 2017
PROJECT DETAILS
Project Title Block level implementation of Torpedo sub-system
Institution Name RV-VLSI Design Center
Project Description Technology node : 180nm
Macros : 32
Standard cells : 43,234
Clocks : 5 (3 Propagated, 2 generated)
Operating frequency : 400MHz
Operating voltage : 1.8V
Max IR Drop : (Vdd+Vss) 5% of Operating Voltage (90mV)
Power budget : 300mW
Metal layers: 6
Tools Used Synopsys IC Compiler for complete PD flow
Synopsys Prime Time for STA
Challenges Creating a floor-plan, keeping in mind its effects on further
steps.
Adjusting power straps to fix various bugs.
Fixing various violations, using automation and not manually.
Finding a common source for several violations.
Project Title Static Timing Analysis (STA) on block level design
Institution Name RV-VLSI Design Center
Project Description Performed and the STA on various test cases of both Flip-flops and
latches which comprise of setup and hold timing reports and there by
understanding the Slack.
Tools Used Synopsys Prime Time
Challenges Generating correct reports for OCV, MCMM and Xtalk, and
fixing violated paths such that it doesn’t cause more violations.
Fixing hold violation without causing a setup violation or vice
versa.
Understanding latch based designs and fixing violations using
concept of borrowed time.
3. Project Title Automation using TCL scripting
Institution Name RV-VLSI Design Center
Project Description Automated various manual and tool driven processes using TCL
scripting to make chip designing faster
Tools Used TCL scripting
Challenges Extracting the necessary information from reports to fix
violations.
Faced few challenges with files and regular expression.
Writing a completely automated script which works on many
designs and not just the current design.
Project Name Synchronous Distributed Clocking System
Institution Name College of Engineering Poonjar
Project Description The development of an ARM microcontroller based digital clock that
has the combined feature of a real time clock (RTC) and a global
system for mobile communication (GSM). We can achieve time
synchronization among all clocks positioned in different places and
also send message to all the clocks by simply writing in the central
system. The central clock automatically sends the messages to all
other clocks. We also provide a belling system so that it rings the bell
in a time as we set.
Tools Used Hardware : Microcontroller (ARM LPC2148), LCD with Driver,
Electric bell with relay, Crystal
oscillator, RTC ,GSM, MAX 232, Regulated Power Supply
Software : Keil embedded development tool, proteus
Challenges Since we required a communication medium for data
transmission and reception for the clocks without having any
range limit , we ended up by choosing GSM instead of RF
transmitter or Zigbee Module.
Project Name Accident zone Detecting System for Vehicles
Institution Name Govt. Polytechnic College Palakkad
Project Description The main objective of this project is to help the person who met an
vehicle accident. By the help of GPS and GSM, this model can track
the specific location of accident and send this attribute to the nearest
hospital and police station.
Tools Used Hardware: PIC Microcontroler, Emergency switch, Vibrating sensor,
Ignition off controller, Switch selector, GPS, GSM, LCD
Software: MP Lab Simulator, Proteus
Challenges While the vehicle met an accident, there is a chances of fire
hazards due to some spark, this is solved providing the Ignition
off controller in the fuel reservoir.
To make nearby people get to know about the accident, we
provide a buzzer so that it will rings the bell when the vibrating
sensor senses a vibration above the normal level
.While met an accident, there will be chances of passenger fall
away, this problem is solved by tightens the side belt if the
vibrating sensor is ON