Resume

1. SUDHEER VADDI
1140 E Orange St, Tempe, AZ. Cell: +1 480 274 4842 sudheer.vaddi@asu.edu
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Summary: Graduate student specializing in VLSI seeking full-time opportunity that will utilize and enhance my skills in the field of Physical
Design, Hardware Design, Computer Architecture, ASIC Design/Verification and applications.
Education:
Master of Science, Electrical Engineering (MSEE) CGPA:3.5
Arizona State University, Tempe, AZ, USA (Jan`15 - Dec`16)
Bachelor of Technology in Electrical Engineering CGPA:3.7
SRM University, Chennai, India (Apr’08 – May’12)
Work Experience:
ATE Test Intern, FINISAR (Jul’16 – Oct’16)
 Actively contributed to Post-Silicon Validation and test time reduction to help with time to market.
 Working knowledge of Continuity, SCAN Tests.Hands on experience in Test program simulation and debug.
 Automated data analysis and test file generation using Perl script. Worked on Teradyne Catalyst Tester.
Graduate Intern, Analog Rails (Mar’16 – June’16)
 Building and characterization of standard library cells. Worked on setting up Yosys tool which is a framework for RTL synthesis tools.
Yosys is an open source Verilog HDL synthesis tool.
System Engineer, Tata Consultancy Services (Sep’12 – Dec’14)
 Developed Unix shell script and Perl script which runs database jobs.Good team player and self-starter. Involved in Clients technology
transfer and got appreciation from the VP of the company. Awarded best performer award for my good work ethics.
Skills:
Tools: Cadence Spectre, Virtuoso, Encounter, Matlab, Xilinx Vivado, Synopsys PrimeTime, Yosys, RTL Compiler, Modelsim, Teradyne Image,
Synopsys VCS, DC | Programming Language: C, C++, Verilog, SystemVerilog, |Scripting Languages: Perl | Operating System: Ubuntu,
Unix, Linux, | Applicationsoftware: MS Word, MS Excel, MS Powerpoint, | Technology nodes : 7nm (FinFETs) and 32nm
Academic Projects:
Verification of 4 port Super Switch using System Verilog:
 Designed Super Switch with one input port and 4 output ports using System Verilog constructs.
 Developed verification plan with layered test-bench incorporating mailboxes.
 Verified Packet routing between input and output ports using constraint-based randomization.
RTL Design and Verification of different components of the microprocessor using System Verilog:
 Designed and verified the following microprocessor components with minimum area and power constraints.Sequential Multiplier,
Sequential Divider, FIFO, Finite Impulse Response (FIR) filter, Sequential square root.
 Developed RTL and testbench using SystemVerilog. Synthesized using Design Compiler (DC).
RTL Design, Verification and Place & Route of Convolution and Max-pooling Engine (ASIC Design):
 Designed Convolution and Max-pooling engine with minimum latency, power and area constraints from RTL to the layout.
 Developed RTL and testbench using Verilog. Synthesized using RTL Compiler. Encounter for floor planning(FP), clock tree
synthesis(CTS), Place and Route (P&R). Primetime for average power consumption. PDK used is 32 nm technology.
 Layout is generated in Virtuoso (GDS import) and DRC/LVS are verified.
Latency Measurement for different levels of Memory Hierarchy using C code:
 Latency of L1, L2, L3 cache and main memory is measured by using different array sizes.
 The effect of the temporal and spatial locality was analyzed.
 Latency of TLB miss was also analyzed.
Design of 32x32 Custom SRAM Register File:
 Circuit Design of a 32 entry, 32bit wide Register File (RF) with one read port and one write port from schematic to layout.
 EDA tool flows like simulation (SPICE), Parasitic Extraction (PEX) are used.DRC/LVS are verified.
Design of 8-bit Modulo Adder:
 Mirror Adder Logic is used in the design of 1-bit adder. Used pipelined approach to improve Energy Delay Product (EDP).
 Hspice simulations are used to verify the functionality. Layout is DRC/LVS verified.
Course Work:
Digital Systems and Circuits, Computer Architecture, VLSI Design, System-Level Design for Multicore Architecture, Fundamentals of the Solid
States, Hardware Design Languages and Programmable Logic, Advance Analog Integrated Circuits, Construction Approach to Microprocessor
Design