1. Sudhakar Margondla
Mobile: +91-8179391095 E-mail: sudhakar.ms06@gmail.com
Career Objective
To work in a challenging environment in a leading organization where I can apply and enhance my skill set
in the field of Hardware and Software Design Engineering with a strong intention in meeting the
organizations business, quality objectives and providing me opportunities in enabling my career
advancement and professional growth.
Professional Summary
Having 10 years of experience in the field of FPGA Design and development , Physical
Designing, Hardware designing in high speed board and mixed signal design.
Associated with safety critical and defense oriented projects using RTL coding with Xilinx, Altera,
lattices high end tools.
 Worked onsite at Koda systems, Korea for a period of 6 months.
 Currently working as a TEAM LEAD at Cognizant Technology Solutions, Hyderabad
 Expertise in Embedded software development using C, VHDL, Verilog and Assembly
 Experienced in Firmware Development and debugging of 8-bit, 16-bit and 32-bit
microcontrollers, soft-core and hard-core processors using C language
 Extensive knowledge of analog hardware design, digital hardware design, Digital signal
processing, signal conditioning, voltage scaling design, power supply design and system
design
 Familiar with PCB board layout and schematics, ADC, DAC and DDS design, Ethernet,
DDR3, USB, Small Form-Factor Pluggable (SFP), S/PDIF, HDMI Analog and digital design
and transmission lines and Guiding hardware engineer, PCB designer engineer while
designing with high speed boards
 Worked on Spartan, Virtex, Kintex and Artix families devices of Xilinx, Startix and Cyclone
families devices of Altera, and different families devices of lattices
 Experience in DFT/DFM techniques for reducing the defects and increasing the productivity
 Experience DRC/DFM Signoff during Physical Design for Provides Faster Time to Closure
 Good knowledge in static timing analysis, clock domain crossing, synchronizers and
timing constraints, place and route, translate
 Hands on experience on logic analyzers, oscilloscopes, spectrum analyzers, RTCS(Radio
Communication Test Set) debuggers and protocol analyzers
 Experience in implementing Digital filters, DUC(Digital up converters), DDC(digital down
converters), Under Sampling, FFT, Noise Cancellation filters, Squelch circuit and Digital
signal processing algorithms
 Extensive experience in simulation using Matlab, Simulink and PSPICE
 Experience in development of GUI based applications using VB and Matlab.
 Attended training sessions on Signal Integrity, Thermal Analysis, Digital Image Processing at
DRDO and on Xilinx at Sandeepani school of VLSI design, Hyderabad

2.  Work experience in all phases of Hardware/Software Development life cycle
 Expertise in Documentation including design, development and execution of Test plans, Test
Strategy and Test cases.
 Ability to learn new technologies in short span and implement independently, good functional and
technical documentation skills.
 A team player with strong organizational abilities and prioritizing skills
 Provided technical and functional trainings to the new joiners at RCI and SRM Technologies
 Guided Juniors while on work on both technical and functional fronts
Technical Skills
 Languages : C, VHDL, Verilog, ASSEMBLY and MATLAB
 Hardware Design : Analog and Digital Circuits.
 Bus and serial Protocols : USART, GPIB, SPI, I2C, Ethernet, SERDES, DDR, HDLC, OPB,
AMBA, Avalon, Arnic 429 and 1553B.
 Tools and Utilities
Processors : ZYNQ, Micro Blaze, Nios, power pc, ARM,8085.
controllers : PIC, MSP430, AVR, ST controllers and 8051(µC).
Compilers : MPLAB, CCS, Turbo C and ANSI C.
Debuggers : GDB (GNU Debugger) XMD prompt, BFM, ModelSim, Chip Scope,
Signal tap, System Vision and Constraints.
Scripting Languages : Tcl, perl, Matlab and Visual basic
RTOS : XilKernel (POSIX).
IDE : Xilinx tools (EDK, ISE, Chip scope & system Generator), Altera
tools(Quartus, Qsys, SDK), lattice tools, Simulink, Cadence
Allegro, Concept HDL, Dx designer, Altium and CADSTAR
IP cores development : 82c54 Timer chip
Education
 M.Tech (Electronics & Communications Engineering) - 2011 from JNTU, Hyderabad.
 M.Sc (Electronics) - 2006 from Pune University, Pune.
 B.Sc (M.E.C.S) - 2004 from Osmania University, Hyderabad.
Experience Summary
RCI, Hyderabad - DRDO Lab
Senior Research Fellow, (July 2006 – April 2012)
SRM Technologies, Chennai
System Analyst (April 2012 – SEPTEMBER 2014)
UURMI SYSTEM, Hyderabad
TEAM LEAD, (SEPTEMBER 2014 – March 2015)
Cognizant Technology Solutions, Hyderabad
TEAM LEAD, (March 2015 – till date)

3. Project Summary
Project #1: Software Defined Radio
Client: DRDO
Location: Hyderabad
Role: Team lead
Duration: Sep 2014 – March 2015
Organization: Uurmi Systems
Project Description: The signal from the antenna is given to Low Noise Amplifier to reduce the
noise in the signal and then fed to a band pass filter; this removes unwanted frequency in the
signal. Signal conditioning circuit is designed which converts the incoming signal to ADC
standards then this signal is then passed to ADC. The digital data from the ADC is given to the
ZYNQ FPGA which is Xilinx make for data processing and brings the signal to base band. (The
signal processing work like filtering, decimation, interpolation, FFT and Etc. is done to bring the
signal to base band) The phase of the demodulated signal is found and by differentiating the
phase information gives the original signal. This signal is passed to low pass filter which is a
digital filter of higher order to remove the harmonics and given to DAC. The output signal is
given to an Analog Low pass filter followed by preamplifier and speaker.
Responsibilities:
 Simulation and development of DSP algorithms using Matlab, Simulink.
 Firmware development of peripherals like ADC, DAC, Ethernet, Memory, LCD.
 Design and development of digital filters, numerically controlled oscillator.
 Digital and Analog hardware designing, board bring up and validation
 Design and stimulation of preamplifier, filters using PSPICE.
 Designing of schematics using Cadence Allegro.
 schematics designing using Orcad
 PCB routing using Cadence Allegro and Signal Integrity using Hyperlinks software.
Tools Used: Xilinx ISE, chip scope, Matlab, Simulink, PSPICE and Cadence Allegro
Project #2: RECEIVER TRANSMITTER INTERFACE CARD FOR CONTROL RADAR. -
DRDO.
Client: DRDO, Bangalore
Location: SRM, Chennai
Role: Team lead and Developer
Duration: may 2012 - July 2014
Organization: SRM Technologies
Project Description: The signals from the Receiver and Transmitter are sampled; the sampled
information is packed in the frame and sent to the Radar Controller at a frequency of 1 Minute.
The signals are fixed - which means the signals coming from drivers and receivers are
transferred to RC through RTI card. None of the signals comes back from RC to RTI.

4. The RTI card contains FPGA, micro controller, ADC, Drivers-Receivers, Buffers and UART. The
processed signals in micro controller are transferred to RC through RS422 line. The Receiver-
Transmitter signals are differential signals and they reach FPGA (VIRTEX II) on the VME back
plane. They are then received by differential receivers, converted into single ended signals and
given to the FPGA.
The required inputs for framing the status message are given by the Radar Controller. The FPGA
takes both the Inputs i.e. one input from driver-receiver through VME back plane and other
input from Radar Controller, frames the status word as required by the Radar Controller and
gives it back to Radar Controller on RS422 lines.
The ADC AD872AJD present on the board will convert the analog Input of IFF video to Digital.
Along with the timing bits, the Digital IFF data will be sent to DIC card, which in turn sends to
Console to Display on the optical link. The SFPDP (Serial Front Panel Data Protocol) protocol is
used for data transfer between DIC card and the Console end.
Responsibilities:
 Simulation and development of DSP algorithms using Matlab, Simulink
 Firmware development of peripherals.
 Gathering the requirements on the basis of functionality from the client directly
 Involved in HDL Coding for the calculation of the speed in KnM/hr using the incoming
Log Data
 Interfacing of timing and status signals from this card to other cards
 Guiding PCB team with placement, routing guide line
 Involved in real time system level testing in Radars
Tools Used: Xilinx ISE, chip scope, Matlab, Simulink, PSPICE and Cadence Allegro
Project #3: Design and Development of Integrated Seeker Electronics.
Client: Defense Ministry, Indian Govt.
Location: DRDO, Hyderabad
Role: Developer
Duration: Aug 2009 – Dec 2011 (29 months)
Organization: RCI - DRDO
Project Description: This ISE card has two FPGAs one is used for signal processing and other
for controlling the sub systems. The azimuth, elevation and sum channel signals from the IF
unit are fed to three high speed ADCs. signal conditioning is done before feed to ADC then
Signal processing job, that is - filtering, decimation, FFT and extraction of final data from the
signal is done in the FPGA (virtex5 SX95T). This data is written in the dual port memory present
in the other FPGA (Virtex5 FX130T) which has two hard core power PCs (440) in which one is
used for controlling all the sub systems, calculating Doppler tracking, range tracking and other
algorithms and other is used for handling avionics protocols. The data is shared between the
two processors using a shared memory controller. PRF (Pulse Reputation Frequency) is
generated using glue logic and it is controlled and selected using the first processor.

5. Tools: Xilinx EDK (Embedded Development Kit), Xilinx SDK (Software Development Kit) and
XilKernel, chip scope, Matlab and Orcad.
Responsibilities:
 Implemented XilKernel (POSIX Compliant) to have Real-Time control on process using
ROUND ROBBIN AND PRORITY SCHEDULING CONCEPTS, MULTITHREADING concepts in
FPGA.
 Implemented DUAL PROCESSOR and Multicore processor.
 Implemented range tracking, Doppler tracking algorithms and firmware of peripherals.
 Interfacing of various peripherals using different Busses (AXI, PLB4.6, PLB3.4 and OPB
bus).
 Implemented Dynamic Allocation for Scratch-Pad Memory (at run time).
 static timing analysis, clock domain crossing, synchronizers and constraints
 Design and development of pulse repetition frequency.
 Physical design of Block level synthesis and analysis for meeting timings
 Digital and Analog hardware designing, board bring up and validation
 Designing of schematics using Cadence Allegro.
 Simulation of DSP concepts using Matlab
Project #4: Digital Receiver
Client: koda systems, Korea (internal projects)
Location: Koda Systems, Korea
Role: Developer
Duration: Oct 2008 – July 2009 (10 months)
Organization: RCI - DRDO
Project Description: The signal from the antenna is given to Low Noise Amplifier to reduce the
noise in the signal then this signal is mixed local oscillator (LO). When this is mixed with the
local oscillator it produce two signals one is sum of the incoming signal and Local Oscillator
signal and other is the difference of the incoming signal and Local Oscillator signal. Then the
signal is fed to a band pass filter the band pass filter to removes unwanted frequency from the
incoming signal (Band pass filter is designed in the range for difference signal) the difference
signal is passed and the sum signal is filtered out. Signal conditioning circuit is provided which
converts the incoming signal to ADC standards then this signal is then passed to high speed
ADC for data processing and the signal is base band processed to extract the information. (The
signal processing work like filtering, decimation and FFT is done to bring the signal to base
band) the extracted data is output to file using Rs232 and also stored in the mass storage
device finally the stored data in the file is taken and ploted as a graph a front ended GUI is
designed using in visual basic software
Responsibilities:
 Simulation and development of DSP algorithms using Matlab, Simulink.
 Firmware development of peripherals.
 Coding using VHDL and c language

6.  GUI development using visual basic
 Design and development of digital filters, numerically controlled oscillator
 Digital and Analog hardware designing, board bring up and validation
 Design and stimulation of preamplifier, filters using PSPICE
 Designing of schematics using Cadence Allegro
 schematics designing using Orcad
 PCB routing using Cadence Allegro and Signal Integrity using Hyperlinks software
Tools Used: Xilinx ISE, EDK, chip scope, Matlab, Simulink, Visual Basic, PSPICE and Cadence
Allegro
Project #5: Design of RADAR Control Computer and Simulator for Controlling the
RADAR Computer.
Client: Defense Ministry, Indian Govt.
Location: DRDO, Hyderabad
Role: Developer
Duration: Sep 2006 – Oct 2008 (26 months)
Organization: RCI - DRDO
Project Description: The aim of the project is to design a RADAR control computer and Real
Time software, which runs on the control computer using 32-bit Xilinx Micro Blaze Soft-Core
Processor. This computer communicates with different sub systems, does the required data
processing and furnishes data to sub systems upon requests. This acts as a supervisor among
all the sub-systems. The debugging of RADAR controller can be done with simulator using a RS-
232 communication. Simulator and GUI can be used in in-house testing of the controller with
other sub systems. This board can be used as a simulator card for Avionics protocol (1553B and
Arinc 429).
Tools: Xilinx EDK (Embedded Development Kit), Xilinx SDK (Software Development Kit) and
Xilkernel, chip scope, Matlab and Orcad.
Responsibilities:
 Developed C-Language programs in Xilinx SDK, to interface sub-systems with radar
control computer.
 Interfaced Components ADC, DAC, DDR, Ethernet, SDRAM, FLASH and DDS with Micro
Blaze processor (Developed firm ware for these peripherals) and did performance
testing.
 Development of algorithms for the seeker computer to interface with digital signal
processing unit.
 Developed a GUI to check the performance of the system and to interact with radar
controller using Visual Basic.
 Design and Development of hardware for RADAR Controller and Simulator.
 Designing of schematics of simulator using Orcad.
 Simulation and analysis at block level has been done for meeting the timing.

7. Project #6: FCP 280 (Field Control Processor 280) Cost Reduction
Client: Schneider electric
Location: Hyderabad
Role: Team lead
Duration: March 2016 – Till Date
Organization: cognizant technologies solutions
Project Description: FCP 280 consists of two cards one is the processor card and other is IO
card . the processor card has Altera FPGA with dual ARM core processor and IO card consist of
one more FPGA. the communication between this two FPGA is taken care through PCI ex link
the Glue logic and other custom IP cores are designed to interact with other peripherals.
Ethernet is used to exchange data to the external world from the processor card FPGA.
Responsibilities:
 Development and Simulation of custom cores.
 Design and development of wrapper logic for handling the low speed peripherals.
 Designing of schematics using Cadence Allegro.
 Schematics designing using Orcad
 PCB routing using Cadence Allegro and Signal Integrity using Hyperlinks software.
Tools Used: Altera Quartus ii 14.1, ModelSim, Qsys and Cadence Allegro
Project #7: Development of simulator for universal IO
Client: Schneider electric
Location: Hyderabad
Role: Team lead
Duration: April 2015 – Oct 2015
Organization: cognizant technologies solutions
Project Description: These simulator is used test and validate the functionality of the ASIC
chips connected in the field boards. Glue logic is developed in such way that it can detect the
number of ASIC chip present in board.
commands are passed through the Ethernet link to the board. Micro blaze(software processor)
is developed to decode the commands and to interact with HART protocol, Glue logic.
Responsibilities:
 development and Simulation of Glue logic using ModelSim.
 Firmware development of peripherals like, RTC, Ethernet.
 Design and development of digital filters, FFT.
 Digital and Analog hardware designing, board bring up and validation
 Designing of schematics using Cadence Allegro.
Tools Used: Xilinx ISE, EDK, chip scope, ModelSim and Cadence Allegro

8. Project #8: Development of 82c54 core and stretch logic for SCADA6000 card
Client: Schneider electric
Location: Hyderabad
Role: Team lead
Duration: Oct 2015 – March 2016
Organization: cognizant technologies solutions
Project Description: Replacing the 82c54 chip and stretch Logic chip by glue logic cores for
SCADA6000 card Xilinx FPGA.
82c54 consists of three identical counters. each Timer can be used to configure the frequency
and duty cycle indepently using the configuration registers. these timer are used to control
electro bus and optonet protocols in the SCADA6000 card. the stretch logic chip take the input
and stretch the signal for the desired amount of time using the RC constant the circuit is
developed using the glue logic.
Responsibilities:
 development and Simulation of Glue logic using ModelSim.
 Digital and Analog hardware designing, board bring up and validation
 Designing of schematics using Cadence Allegro.
Tools Used: Xilinx ISE, EDK, chip scope, ModelSim
Trainings & Recognition:
 Attended training sessions on Signal Integrity, Thermal Analysis, Digital Image Processing at
DRDO
 Attended training session on Xilinx at Sandeepani school of VLSI design, Hyderabad
 Received appreciation from the Project head several times for working on and successfully
completing multiple projects within the given time limit.
Core Strengths:
 Very good Knowledge on High speed board Designing and Debugging
 Very good Knowledge on hardware development cycle and software development cycle.
 Expertise in handling High ended Lab equipments such as Signal generators, function Generators,
Logic Analyzers, MSOs, Spectrum Analyzers.
 Strong coding skills using C Language, VHDL and simulation using Matlab
 Good at analyzing requirements specifications and preparing corresponding Schematics
Personal Particulars
Date of Birth : 03-Aug-1983
Languages : Telugu, English, Hindi, Tamil and German
Passport Details : H2246944
Contact Address : Plot No. 79, Hastinapuram, Phase 2 Central, N.S. Road,

9. Hyderabad - 500079
Phone No : +91-9791070620, +91-8179391095
Email Id : sudhakar.ms06@gmail.com
(Sudhakar M)