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MELDIYA THOMAS
meldiatms@gmail.com, 8281455045
Bangalore-560068, Karnataka
Career Objective
Looking for an opportunity to work as a Physical Design Engineer with a view to enhance my
skills towards professional growth in your organization.
Core Competancy
Good Knowledge about ASIC design flow.
Comprehensive knowledge and hands on experience in STA, OCV, CRPR, interpreting timing
reports and fixing Setup and Hold violations.
Proficient in Physical Design flow involving Floor planning, Power planning, IR drop analysis,
Automatic P&R, Clock Tree Synthesis and Timing Analysis at each stage.
Familiar with Signal Integrity(Crosstalk) concept and Physical Verification (DRC, LVS,
Antenna fixing) & Parasitic Extraction.
Have exposure on industry standard EDA tools like IC Compiler, PrimeTime from Synopsys.
Automate P&R flow using TCL script.
Good Knowledge on Digital design concepts & fundamentals of CMOS concepts.
Well versed with Netlist - GDS II Flow.
Have working experience on Linux operating system.
Education Details
Advanced Diploma in ASIC Design - Physical Design 2017
RV-VLSI Design Center
Bachelor Degree in Electronics and Communication 2016
College of Engineering Poonjar,Kottayam, with 7.14 CGPA
PUC / 12th 2012
St.Sebastian's Higher Secondary School, Koodaranjhi,Kozhikode , with 86 %
SSLC 2010
St.Sebastian's Higher Secondary School, Koodaranjhi,Kozhikode , with 93 %

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Domain Specific Project
RV-VLSI Design Center
Physical Design Trainee Engineer Oct-2016 to Jan-2017
Block level implementation Torpedo sub-system
Description
Torpedo Sub-System implemented in 180nm Technology with 32 macros, 43275 standard cells,
Supply Voltage of 1.8V, consumes 300mW of Power and works at operating frequency
400MHz.It has 5 clocks and IR drop budget is 5%of (VDD+VSS).
Tools
IC Compiler from synopsys
Challenges
Efficient floorplan by placing the macros to achieve maximum contagious space for standard
cells.
Also done various iterations for metal widths, number of straps and offsets values to achieve
IR drop as per specification.
Reducing congestion, avoiding floating nets, creation of hard blockages and route guide
during placement.
Efficient Clock Tree Building by implementing optimization techniques to fix hold violations.
RV-VLSI Design Center
Physical Design Trainee Enggineer Sep-2016 to Oct-2016
Static Timing Analysis for various Timing Path
Description
The aim of this project is to perform STA and to analyse timing reports for different designs
which consists of all kinds of timing paths for flipflop and latch based designs by giving Design
Constraints, GLN and Timing libraries as inputs.
Tools
Prime Time from synopsys
Challenges
Interpreting and visualise the circuit from the timing report.
Analysing timing reports for Register-to-Register, Register-to-Output timing paths when clock
uncertainty, latency, derate factors, multi-cycle path and CRPR are included.
Understanding Time-borrow concept, analysing timing reports for Latch based designs.

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B.E / B.Tech Academic Project
College of Engineering Poonjar,Kottayam
Colour detection and sorting using sigma delta ADC
Description
The colour of objects with primary colours and secondary colours are detected and are sorted
according to colours. Sigma delta ADC is implemented on PIC16F877A which is of high
resolution and accuracy.
Tools
MP lab is used to programming PIC16F877A and Proteus used for schematic and PCB design.
Hardwares used are PIC16F877A microcontroller,LCD Display, Servo Motor, DC Motor, LDR
and LEDs.
Challenges
Difficulty faced while detecting the secondary colour cyan & during calibration setting