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DEEKSHA ANANDANI
Contact Address Mail Id daanandani@gmail.com
Deeksha Anandani
Matri kripa,
Beh. Vidhya Niketan School,
Kargeta,
Salumber, Udaipur,
RAJASTHAN-313027
Contact Phone
(+91) 9414685347
(+91) 9480215025
Date of Birth 25th
AUG1994
CAREER PROFILE
Objective
To build a career that offers challenge and growth to enrich my knowledge and skills that
contributes towards the achievement of the mission and values of the organization.
INDUSTRIAL PROJECT
Title Margin analysis of SRAM and ROM compilers
Company NXP Semiconductors, Bangalore
Duration July 2015 to Dec 2015
Tools Cadence Spectre, Variation Designer by Solido design automation
Scripting
Language
Korn shell (KSH )
Guide Rajat Kohli and Syed A. Murtaza
Project
Description
1. Enhancement of Margin analysis methodology in statistical domain.
2. Automation of Critical path modeling for memory Complier.
3. Statistical analysis using cadence Spectre (Montecarlo analysis).
4. High sigma Montecarlo analysis using Variation-designer by Solido
design automation tool.
Title Bitcell analysis automation flow.
Company NXP Semiconductors, Bangalore
Duration Jan 2016 to June 2016
Scripting
Language
Korn shell (KSH) , PERL
Guide Rajat Kohli and Syed A. Murtaza
Project
Description
1. Complete understanding of SRAM bitcell.
2. Bitcell analysis automation flow for SRAM and ROM.
3. Technology independent Bitcell flow.
4. Applicable for any type of bitcell architecture (such as high density,
high speed, dual port, single port etc.).
5. Measurement of Ion, Ioff, SNM, RNM, Write margin, Read time and
Write time.

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IEEE PUBLICATION
Title Gating techniques for 6T SRAM cell using different modes of FinFET
Guide Dr. V S Kanchana Bhaaskaran, Dean, SENSE Dept., VIT, Chennai
Tools Cadence virtuoso
Project
Description
In this project we incorporated fine grain and coarse grain power
gating techniques for the SRAM cell and SRAM array respectively.
The leakage power, stability (SNM) and delay is found by simulating
different modes of FinFET which are 1.Tied gate FinFET
2.Independent gate FinFET 3.Independent gate FinFET using pass
gate feedback. It was found that Independent gate FinFET using pass
gate feedback consumes lowest of all three that is 2.23uW of power
during the hold operation. When power gating is applied power
dissipation of 27.67pW is achieved. The simulations are carried out
using Cadence® Virtuoso tool, using 32nm Predictive Technology
Model (PTM) files for the MOS devices and 32nm BPTM files for the
FinFET.
Title Novel 6T SRAM design for high speed and low power
Guide Dr. V S Kanchana Bhaaskaran, Dean, SENSE Dept., VIT, Chennai
Tools Cadence virtuoso
Project
Description
Design of SRAM cell using multi threshold voltage schemes provided
by UMC 90nm technology file. The access of SRAM cell is made
faster by using low threshold transistors at access site at the same time
the leakage is also controlled by using high threshold transistors at
storage sites. It is found that the speed for read and write operation is
doubled as well as 70% leakage suppression is achieved without
affecting the stability (SNM) criteria. The simulations are carried out
using Cadence® Virtuoso tools, employing the UMC 90 nm
technology.
Under graduate project
Title Intelligent Energy Saving System
Duration Jan 2013 to May 2013
Language Embedded C
Project
Description
This project is based on power grade failure problem. The main aim is
to switch on and off the appliances like fans, lamps etc. automatically
according to entry and exit of person.AT89C51 microcontroller is
used in the project. The secondary application is to count the number
of people, display the result and ring the alarm.
ACADEMICS
Course Board/University Year of Completion
Percentage
/CGPA
M.Tech
(VLSI design)
VIT University,
Chennai
Pursuing 4th
Semester
9.02
B.Tech(Electroni
cs and
Communication
Engineering)
Rajasthan Technical
University (RTU)
2013 75.86 %
HSC
Board of Secondary
Education, Rajasthan
2009 76.37 %
SSC
Board of Secondary
Education, Rajasthan
2007 73.17 %

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TECHNICAL SKILLS
EDA Tools
Cadence EDA Tools:
 ASIC Design Tools
 NC Sim
 Encounter RTL Compiler
 Encounter Digital Implementation
 Full Custom Design Tools
 Virtuoso ADE
 Layout XL
 Assura DRC, LVS
Technology Nodes UMC 90nm, GPDK 45nm, GPDK 180nm, PTM 32nm
Methodologies
Full Custom Design and Semi-Custom ASIC Design
Hardware Description
Languages
Verilog
Programming Languages C, C++
Scripting languages Basics of Perl and TCL
CO-CURRICULAR ACTIVITIES
 Participated in the paper presentation contest on Appropriate Climate Responsive
technologies for inclusive growth and sustainable development.
 Attended National Symposium on Aerospace Technologies in Defense.
 Participated in two day workshop on “Hands on training in TCAD”.
ACHIEVEMENTS
 Qualified GATE exam in 2014.
 Got honors degree in B.Tech (75.86%).
 Won 1st
Runner up prize in robotics event organized by IIT Delhi.
 Won 1st
prize in singing competition at school level.
Personal Details
Name DEEKSHA ANANDANI
Father’s Name PRAKASH CHANDRA ANANDANI
Nationality INDIAN
Languages Known HINDI,ENGLISH,SINDHI
“I hereby declare that the above information is true to best of my knowledge.”
Date:-
Place: - Chennai DEEKSHA ANANDANI