Resume Physical Design

1. Prince Kumar
princerana08@gmail.com, 7508435907
Bangalore-560068, Karnataka
Career Objective
To work with reputed organization, which maintains its Employee’s Enthusiasm thereby
making them work excellently towards common objectives. Work in a progressive manner to
provide benefit to organization.
Core Competancy
 Proficient in ASIC/PD Flow from Netlist to GDSII and hands-on experience in one of the APR
tools.
 Workable experience in Floorplan, Power Plan, Placement, CTS, Routing, Physical Verifcation
(DRC/ LVS checks).
 Power Plan: to connect all pins of macros and standard cells to the Power nets without any
floating wire and DRC errors within IR Drop limit.
 Good understanding of Primetime STA tool and timing closure methodologies and implementing
timing ECOs including effect on congestion/routing/power.
 Understanding of Design constraints to specify OCV , AOCV PVT Corners, false Paths, half
cycle paths, CRPR etc.
 Understanding of Power grid, clock Tree and low power reduction implementation methods.
 Familiar with scripting languages like TCL, Perl, Linux Shell scripting.
 Adequate knowledge of Digital Design, CMOS, Verilog, Shell scripting, C.
 Tools: Synopsys - ICC2, PrimeTime, Mentor Graphics: Calibre, Questasim.
 Good communication skills and ability & desire to work in a cross functional team.
Education Details
Advanced Diploma in ASIC Design - Physical Design 2020
RV-VLSI Design Center
Bachelor Degree in Electronics and Communication 2016
Indus International University Una , with 9.01 CGPA
Diploma 2013
Indus International University Una H.P, with 79.4 %
SSLC 2010
Punjab State Education Board Mohali, with 70 %
Domain Specific Project
RV-VLSI Design Center, Bangalore
Graduate Trainee Engineer Aug-2019 to Feb-2020
Analysing, Writing and debugging TCL Scripts
Description
Analysing, Writing and debugging TCL Scripts to automate operations and extract information
from ICC2 database.
Tools
Tclsh, TCL Tutor, Linux, Synopsys ICC2
Challenges
 Debugging TCL Scripts and syntactical errors.
 Use of ICC2 Tool commands with script logic.
 Fetching and filtering of required data to make it compatible with icc2_shell tool
commands.

2. RV-VLSI Design Center, Bangalore
Graduate Trainee Engineer Aug-2019 to Feb-2020
Floor planning & Power planning
Description
Technology - 40nm, Macro count - 34, Standard cell count - 40K, Area - 4.2 mm2, Supply -
1.1V, Clock frequency - 1 GHz, Metal layers - 7, Power Budget - 600 mW, IR drop < 55 mV.
Tools
Synopsys ICC2, Linux
Challenges
Understanding the Design setup scripts, manual placement of macros based on data flow lines,
macro family and ports.
Optimal spacing in between macros to avoid congestion and better routability for next PD flow
steps.
Iterations in adjusting the offset and number of power straps, pitch and their width to meet the
IR drop target.
Ensuring that design to be free from DRC violations, floating pins, floating wires by
aligning the macros and giving placement and Routing blockages.
RV-VLSI Design Center, Bangalore
Graduate Trainee Engineer Aug-2019 to Feb-2020
Placement and Clock Tree Synthesis
Description
Analize design with acceptable congestion and distributed power with minimum timing. DRC's
and building clock tree with optimized clock skew.
Tools
Synopsys ICC2
Challenges
Understanding the timing reports after each step of APR flow and different placement
switches for optimisation.
Achieving congestion free placement to have good routability for DFT aware placement.
Design setup for CTS: cell purpose definition, clock buffers/inverters, don't touch cells.
Understanding the tool behavior while Clock tree building and optimization of clock & data
paths for fixing timing violations by balancing the skew.
RV-VLSI Design Center, Bangalore
Graduate Trainee Engineer Aug-2019 to Feb-2020
Analysis of Timing Reports (STA)
Description
Detailed analysis of Timing constraints and Timing reports of the design under analysis to
understand the concepts related to constraints in (.sdc) file.
Tools
Synopsys: PrimeTime, ICC2
Challenges

3. Proper understanding of basic concepts and terms related to STA was necessary for accurate
analysis of timing reports.
Aknow-how of cell delays, Deratefactors,Setuptimeand Holdtime, MCMM, OCV/AOCV,
PVT, CRPR, Timing exceptions(false path & multi cycle path).
Identification of over pessimistic constrained paths and constraint modification.
Clock definitions and parameters like uncertainty, latency, skew, jitters and synchroniser
(FIFO depth) concept.
B.E / B.Tech Academic Project
Indus International University Una
Data Fusion on Sled Boun Application
Description
During Ground testing of Rocket on Rail Track. It's difficult to analysis the Data as decided
target due to Friction on Track. So We placed some Sensor and near the Track to analysis the
Data.
Tools
Hardware used: ATmega328P, Software used: Arduino IDE
Challenges
It's difficult place the Sensors on the Track and communicate with Laptop and after testing
analysis we have to fusion the data.