Accurate Synchronization of EtherCAT
Systems Using Distributed Clocks
Before We Start
 This webinar will be available afterwards at
designworldonline.com & via email
 Q&A at the end of the p...
Moderator

Presenter

Leslie Langnau

Joey Stubbs

Design World

EtherCAT Technology Group
Accurate Synchronization of EtherCAT
Systems Using Distributed Clocks

Joseph E Stubbs, PE, PMP
EtherCAT Technology Group
Purpose of this presentation
• Gain a basic understanding of how the Distributed Clocks
(DC) synchronization method of Eth...
Agenda
•
•
•
•

“Distributed Clocks” definition
Important EtherCAT functional principles
Overview of DC functionality
How ...
DCs definition
• In EtherCAT terminology the term “Distributed Clocks”
(DCs) refers to a logical network of synchronized,
...
Why Synchronize a Network?
• Common time value in all devices allows synchronous gathering
of input data from devices
o Ex...
Functional Principles
• EtherCAT utilizes several important operating principles
allowing DCs to be implemented efficientl...
Functional Principle: Ethernet “on the Fly”
Slave Device

Slave Device

EtherCAT Slave
Controller

EtherCAT Slave
Controll...
Frame Processing within each node
Master

EtherCAT Segment (Slaves)

IPC

..
..

DVI

From Master
To Master
Topology
• Flexible Topology
• Any number of physical layer changes possible
• Up to 65,535 devices within one EtherCAT ne...
Frame Processing
Auto Forwarder and Loop Back
1

Port 3
AutoForwarder

port 3 open

EtherCAT
Processing Unit

port 3 close...
Important things to keep in mind
• Only the EtherCAT master (controller) can create a frame
• Slaves can only modify the f...
Frame Processing Order on the System
EtherCAT Segment

Master

Cable

EtherCAT Frame Path
EtherCAT Commands
• Broadcast Read Actions
o Individual Bits of a Byte will be added with a bitwise OR operation between
i...
Distributed Clocks Unit
SPI / µC parallel
Digital I/O
EtherCAT Address Space

IRQ

Sync1 / Latch1
Sync0 / Latch0

Process ...
• The following must be handled by the distributed clock
control in the EtherCAT master:
o Propagation delay measurement: ...
Distributed Clocks – Features
• Definition of a System Time
o
o
o
o

Beginning on Jan. 1, 2000 at 0:00h on power-up
Base u...
Propagation Delay Measurement
• Determine differences between the Ref clock and each DC
Ref
slave Port 0 time
S

∆t

IPC

...
DC – Propagation Delay Measurement
• EtherCAT Node measures time difference between leaving and
returning frame

EtherCAT ...
Propagation Delay Measurement
•

Registers:
o
o
o
o
o

•

(ADO: 0x0900:0x0903)
(ADO: 0x0904:0x0907)
(ADO: 0x0908:0x090B)
(...
DC – Propagation Delay Measurement
• EtherCAT Node measures time difference between leaving and
returning frame
IPC
Propagation Delay Measurement
The differences between the Reference Clock and each DC slave “In” port
is Propagation Delay...
Binding Reference Clock to RTC
• Registers:
o System Time Offset
(ADO: 0x0920:0x927, small systems 0x0920:0x0923)

• Diffe...
Binding Reference Clock to RTC
Master sets Reference clock to RTC (or other source)
RTC

Ref

S

IPC

S

S

S

S

S

S
Offset Compensation
• Registers:
o System Time Offset
(ADO: 0x0920:0x927, small systems 0x0920:0x0923)

• Difference betwe...
Setting individual slaves to Reference Clock
Master calculates offset between Ref Clock and individual local clocks.
Ref
T...
Drift Compensation – DC Control
• RMW command (read – multiple write) allows the
master to read System Time of the referen...
Drift Compensation
Master commands the Reference clock to distribute its local
time to all nodes occasionally.
Ref

The fr...
Drift Compensation – DC Control
Because the RMW instruction distributes the reference
clock time each time the instruction...
Long Term Scope View of Two Separated Devices
• 300 Nodes in between, 120m Cable Length
Interrupt
Node 1

Simultaneousness...
Synchronization of multiple networks
Via boundary clock

M1

M2

M3
External Synchronization
Via 1588 Boundary Clock
M Boundary
Clock

S

Master

S

S

S

S

S

S

IEEE 1588
Grandmaster
Example features of EtherCAT DCs
• Clock synchronization between the EtherCAT slaves and
the master
• Synchronous generati...
Action based on specified time: Sync 0/1
• The distributed clock unit in the ESC
usually features 2 pins that can be
trigg...
Reaction to an external signal - Latch 0/1
• If an ESC is configured accordingly it can store
the current local time if an...
Example of Latch and Sync Use
1 + Tx 1 +Ty
1 + T1 1 +T2

IN
Latch
Timestamp

Constant

OUT
Timestamp

?
OUT
“Classical
Con...
Connection to an External Logic - SPI/µC
Parallel/IO/IRQ
PDI IRQ

•

•

•

An ESC can not only be used as a stand-alone
un...
Example of IRQ Use with a µC -- Oversampling
Oversampling – fast measurements
Measurement cycle

Base Network cycle

23.10...
Distributed Clock shift in Master to Ensure
Frame Arrives Prior to Sync Signal Generation
Local Timer

Local Timer

Applic...
Summary
• Tight clock synchronization between the EtherCAT slaves and
the master is possible without the use of a special ...
Please visit

www.ethercat.org
for more information
EtherCAT Technology Group
Headquarters
Ostendstraße 196
90482 Nurember...
Questions?
Design World

Leslie Langnau
llangnau@wtwhmedia.com
Phone: 440.234.4531
Twitter: @DW_RapidMfg

EtherCAT Technol...
Thank You
 This webinar will be available at designworldonline.com & via
email

 Tweet with hashtag #DWwebinar
 Connect...
Accurate Synchronization of EtherCAT Systems Using Distributed Clocks
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Accurate Synchronization of EtherCAT Systems Using Distributed Clocks

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Synchronization and determinism are important considerations when selecting an industrial control system and the associated fieldbus. Additionally, it’s important for field devices to have network-wide interrupts for activating outputs, capturing input data, oversampling or latching events. These are all significant facets in the overall network synchronization scheme.
This webinar on Tuesday, Oct. 23 at 2 PM EST will explain how the Distributed Clock mechanism in EtherCAT works to meet all of these functions using properties inherent to the protocol. This can be done using a standard Ethernet network adaptor, all without the overhead of IEEE 1588.
Attend this webinar to learn:
How Distributed Clocks (DCs) in EtherCAT facilitate measurement of propagation delay throughout the system and synchronize network devices to a single time value
What EtherCAT slave devices can do to facilitate temporal behavior for outputs and inputs as well as implementing data oversampling
More about some of the concepts that enable EtherCAT to have a high scan rate as well as high levels of synchronization

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Accurate Synchronization of EtherCAT Systems Using Distributed Clocks

  1. 1. Accurate Synchronization of EtherCAT Systems Using Distributed Clocks
  2. 2. Before We Start  This webinar will be available afterwards at designworldonline.com & via email  Q&A at the end of the presentation  Hashtag for this webinar: #DWwebinar
  3. 3. Moderator Presenter Leslie Langnau Joey Stubbs Design World EtherCAT Technology Group
  4. 4. Accurate Synchronization of EtherCAT Systems Using Distributed Clocks Joseph E Stubbs, PE, PMP EtherCAT Technology Group
  5. 5. Purpose of this presentation • Gain a basic understanding of how the Distributed Clocks (DC) synchronization method of EtherCAT works. • Understand how devices designed with EtherCAT DCs can benefit the user.
  6. 6. Agenda • • • • “Distributed Clocks” definition Important EtherCAT functional principles Overview of DC functionality How it works o o o o o Propagation delay measurement Setting of Reference Clock Setting of Slave Clocks Drift compensation Master compensation (shift time) • Practical applications of DCs in slave devices
  7. 7. DCs definition • In EtherCAT terminology the term “Distributed Clocks” (DCs) refers to a logical network of synchronized, distributed local clocks in the EtherCAT fieldbus system. • By using distributed clocks, EtherCAT, the real-time Ethernet protocol is able to synchronize the time in all local bus devices within a very narrow tolerance range, typically within 100ns.
  8. 8. Why Synchronize a Network? • Common time value in all devices allows synchronous gathering of input data from devices o Example -- When device 1 was at position X, device 2 was at position Z. • Cyclic behavior with tight temporal tolerances o Example – position control of a drive. Exact position input for each time slice produces tighter coordinated motion or speed. o Example – data acquisition at high data rates • Response to external event o Example -- Exact time alarm when received can be used to reject bad product downstream with respect to conveyor speed with little loss of good product o Example -- “Seeing” events that would be missed in classical scanning of I/O systems • Response at exact future time o Example -- All drives begin execution of new command at exact time o Example -- Simultaneous outputs for devices separated by long distances in same network
  9. 9. Functional Principles • EtherCAT utilizes several important operating principles allowing DCs to be implemented efficiently and elegantly Processing “On the Fly” Protocol processed in hardware Fixed frame path for all frames in network in a given topology Latching of receive times in slave ports and logical processing unit Instruction set that lends itself to distributing times and offsets easily A DC unit built-in to the EtherCAT Slave Controller (ESC), which facilitates many of the functions in hardware o External interfaces from the DC unit o o o o o o
  10. 10. Functional Principle: Ethernet “on the Fly” Slave Device Slave Device EtherCAT Slave Controller EtherCAT Slave Controller •Process data is extracted and inserted on the fly •Compilation of process data can change in each cycle, e.g. ultra short cycle time for axis, and longer cycles for I/O update possible •In addition asynchronous, event triggered communication
  11. 11. Frame Processing within each node Master EtherCAT Segment (Slaves) IPC .. .. DVI From Master To Master
  12. 12. Topology • Flexible Topology • Any number of physical layer changes possible • Up to 65,535 devices within one EtherCAT network possible Line Master Star/Tree Drop Line
  13. 13. Frame Processing Auto Forwarder and Loop Back 1 Port 3 AutoForwarder port 3 open EtherCAT Processing Unit port 3 closed Loopback function port 2 closed port 2 open AutoForwarder Port 2 AutoForwarder port 1 open ET1100 ESC port 1 closed Loopback function Loopback function port 0 closed port 0 open or all ports closed Port 0 AutoForwarder Loopback function 1 Port 1
  14. 14. Important things to keep in mind • Only the EtherCAT master (controller) can create a frame • Slaves can only modify the frame(s) • The frame is not actively routed to a particular node. The frame travels through the entire network regardless of which node is addressed within the frame. • One frame can service an entire network. Multiple frames can be sent out back-to-back to service larger networks which exceed 1500 bytes in data length.
  15. 15. Frame Processing Order on the System EtherCAT Segment Master Cable EtherCAT Frame Path
  16. 16. EtherCAT Commands • Broadcast Read Actions o Individual Bits of a Byte will be added with a bitwise OR operation between incoming data and local data • Read Write Actions o Exchange of incoming data and local data (exception: Broadcast – see broadcast read) • Read Multiple Write Actions (RMW) o Addressed Station will read, the others will write
  17. 17. Distributed Clocks Unit SPI / µC parallel Digital I/O EtherCAT Address Space IRQ Sync1 / Latch1 Sync0 / Latch0 Process Data Interface (PDI) FMMU n Sync / Latch Unit SyncMan DC Control EtherCAT Processing Unit and Auto-Forwarder with Loop Back Mag PHY Port 2 RJ45 PHY Port 1 Mag RJ45 Port 0 Port 3 Offset System Time Delay Distributed Clocks EtherCAT Slave Controller (ESC)
  18. 18. • The following must be handled by the distributed clock control in the EtherCAT master: o Propagation delay measurement: Measurement of the offset times depending on the number of devices, cable lengths, dynamic changes in the configuration, etc. o Offset compensation of the reference clock relative to the master clock. This is taken into account during system start-up. o Offset compensation of each slave relative to the reference clock. After system startup the local clocks may start with different start values. o Drift compensation/drift correction. Each slave clock usually has its own source (quartz, PLL, ...), which means that offset times do not remain constant over a prolonged period (minutes, days). Drift correction deals with this irregularity.
  19. 19. Distributed Clocks – Features • Definition of a System Time o o o o Beginning on Jan. 1, 2000 at 0:00h on power-up Base unit is 1 ns 64 bit value (enough for more than 500 years) Lower 32 bits spans over 4.2 seconds • Normally enough for communication and time stamping • Definition of a Reference Clock o One EtherCAT Slave will be used as a Reference Clock o Reference Clock distributes its Clock cyclically o Reference Clock adjustable from a “global” Reference Clock – IEEE 1588
  20. 20. Propagation Delay Measurement • Determine differences between the Ref clock and each DC Ref slave Port 0 time S ∆t IPC S S S S S S
  21. 21. DC – Propagation Delay Measurement • EtherCAT Node measures time difference between leaving and returning frame EtherCAT Frame Processing Direction EtherCAT Frame Forwarding Direction
  22. 22. Propagation Delay Measurement • Registers: o o o o o • (ADO: 0x0900:0x0903) (ADO: 0x0904:0x0907) (ADO: 0x0908:0x090B) (ADO: 0x090C:0x090F) (ADO: 0x0928:0x092B) Write access to Receive Time Port 0 activates latch o o • • • • Receive Time Port 0 Receive Time Port 1 Receive Time Port 2 Receive Time Port 3 System Time Delay Latch local time of SOF (Start of Frame) At EOF (End of Frame) SOF time is copied to Receive Time Port X Receive Time Port X in local clock units (controlled) SOF time of all frames are latched on all ports internally Master reads all time stamps and calculates the delay times with respect to the topology. Individual delay time is written to register System Time Delay
  23. 23. DC – Propagation Delay Measurement • EtherCAT Node measures time difference between leaving and returning frame IPC
  24. 24. Propagation Delay Measurement The differences between the Reference Clock and each DC slave “In” port is Propagation Delay, called “System Time Delay”. Ref This value is distributed by the master stored in the slave for drift compensation calculations later. S ∆t IPC S S S S S S
  25. 25. Binding Reference Clock to RTC • Registers: o System Time Offset (ADO: 0x0920:0x927, small systems 0x0920:0x0923) • Difference between the Master RTC and Reference Clock is calculated by the master. • This time is written to register System Time Offset of the Reference Clock only.
  26. 26. Binding Reference Clock to RTC Master sets Reference clock to RTC (or other source) RTC Ref S IPC S S S S S S
  27. 27. Offset Compensation • Registers: o System Time Offset (ADO: 0x0920:0x927, small systems 0x0920:0x0923) • Difference between the Reference Clock and every slave device's clock is calculated by the master. • The offset time is written to register System Time Offset • Each slave calculates its local copy of the System time using its local time and the local offset value: • tLocal copy of System Time = tLocal time + tOffset
  28. 28. Setting individual slaves to Reference Clock Master calculates offset between Ref Clock and individual local clocks. Ref This value is distributed by the master and written to each slave in order to bring all local times to the same exact time. S IPC S S S S S S
  29. 29. Drift Compensation – DC Control • RMW command (read – multiple write) allows the master to read System Time of the reference clock and write it to all slave clocks within a single frame using the same frame route and therefore the same propagation delay as the initial measurement. • DC Control o Write access to System Time compares received Time with local time t = (tLocal time + tOffset - tPropagationDelay) – tReceived System Time o If (t > 0) then decelerate local clock (each tick counts as less time) else if (t < 0) accelerate local clock (each tick counts as more time)
  30. 30. Drift Compensation Master commands the Reference clock to distribute its local time to all nodes occasionally. Ref The frequency of issuing the RMW command determines the amount of drift allowed in the system clocks S IPC S S S S S S
  31. 31. Drift Compensation – DC Control Because the RMW instruction distributes the reference clock time each time the instruction is called… …and because the propagation delay of the system does not change… …we do not need to have jitter-free frames to have a jitter free system! Therefore, no special master card is required, the master can be a software stack even for the most tightly synchronized applications.
  32. 32. Long Term Scope View of Two Separated Devices • 300 Nodes in between, 120m Cable Length Interrupt Node 1 Simultaneousness: ~15 ns Interrupt Node 300 Jitter: ~ +/-20ns
  33. 33. Synchronization of multiple networks Via boundary clock M1 M2 M3
  34. 34. External Synchronization Via 1588 Boundary Clock M Boundary Clock S Master S S S S S S IEEE 1588 Grandmaster
  35. 35. Example features of EtherCAT DCs • Clock synchronization between the EtherCAT slaves and the master • Synchronous generation of local output signals (Sync signals) • Precise time stamping of input signals (Latch signals) • Generation of synchronous interrupts to local microprocessors (IRQ signals)
  36. 36. Action based on specified time: Sync 0/1 • The distributed clock unit in the ESC usually features 2 pins that can be triggered time-controlled. SYNC0 and SYNC1. • In this case the compare unit in the ESC would be active: If the local distributed clock time matches a user-defined enable time the ESC triggers the associated Sync pin(s). • This behaviour can be set up to be single shot or cyclic, with or without an acknowledge. PDI IRQ Sync0 Sync1 Sync Unit Latch Unit DC Control Offset System Time Delay Distributed Clocks
  37. 37. Reaction to an external signal - Latch 0/1 • If an ESC is configured accordingly it can store the current local time if an external event occurs, i.e. it can place it into a buffer without delay using a capture unit. • Can be configured for rising and/or falling edge, and single event or continuous latch • Examples for such external events are edge on a dedicated pin of the ESC (Latch 0/1), arrival of the EtherCAT frame, end of the EtherCAT frame, communication with a connected microcontroller, and a wide range of other options. Latch0 Latch1 Sync Unit Latch Unit DC Control Offset System Time Delay Distributed Clocks
  38. 38. Example of Latch and Sync Use 1 + Tx 1 +Ty 1 + T1 1 +T2 IN Latch Timestamp Constant OUT Timestamp ? OUT “Classical Controls” Constant 1 + Tz 1 + T3
  39. 39. Connection to an External Logic - SPI/µC Parallel/IO/IRQ PDI IRQ • • • An ESC can not only be used as a stand-alone unit, it also has interfaces for communicating with other electronic units such as a microcontroller or other driver circuitry. Communication via these interfaces can also be controlled via distributed clocks in order to ensure synchronous, high-precision sampling of input parameters, or cyclic interrupts based on a multiple of the base scan rate. Examples for this use include interfacing to a microprocessor controlling a power drive, electronic shaft encoder analyzer, or data acquisition slaves for condition monitoring. Sync1 Sync0 Sync Unit Latch Unit DC Control Offset System Time Delay Distributed Clocks
  40. 40. Example of IRQ Use with a µC -- Oversampling Oversampling – fast measurements Measurement cycle Base Network cycle 23.10.2012 41 o Fast signal sampling o Analog value recording (input) o Analog value generation (output) Base Network cycle
  41. 41. Distributed Clock shift in Master to Ensure Frame Arrives Prior to Sync Signal Generation Local Timer Local Timer Application Application Master Shift User Shift Master Frame D U Frame D DC Base U Frame Delay Fixed Shift (precalc.) Master Slave Sync0 Shift S0 S0 Sync0 Sync0
  42. 42. Summary • Tight clock synchronization between the EtherCAT slaves and the master is possible without the use of a special fieldbus card • The DC features of devices are enabled by both the unique communication principles of EtherCAT and built-in features of the ESCs. • Some of the common behaviors built in to devices are: o Synchronous reading of input signals o Precise time stamping of input signals (Latch signals) o Generation of synchronous interrupts to local microprocessors (IRQ signals)
  43. 43. Please visit www.ethercat.org for more information EtherCAT Technology Group Headquarters Ostendstraße 196 90482 Nuremberg, Germany Phone: +49 911 54056 20 Email: info@ethercat.org EtherCAT Technology Group North America PO Box 1305 Port Orchard, WA 98366 Phone: 1-877-384-3722 Email: j.stubbs@ethercat.org
  44. 44. Questions? Design World Leslie Langnau llangnau@wtwhmedia.com Phone: 440.234.4531 Twitter: @DW_RapidMfg EtherCAT Technology Group Joey Stubbs j.stubbs@ethercat.org info@ethercat.org Phone: 1-877-384-3722
  45. 45. Thank You  This webinar will be available at designworldonline.com & via email  Tweet with hashtag #DWwebinar  Connect with  Twitter: @DesignWorld  Facebook: facebook.com/engineeringexchange  LinkedIn: Design World Group  YouTube: youtube.com/designworldvideo  Discuss this on EngineeringExchange.com

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