Submit Search
Upload
IRJET - High Speed Approximation Error Tolerance Adders for Image Processing Applications
•
0 likes
•
85 views
IRJET Journal
Follow
https://www.irjet.net/archives/V7/i4/IRJET-V7I4232.pdf
Read less
Read more
Engineering
Report
Share
Report
Share
1 of 7
Download now
Download to read offline
Recommended
IRJET - A Speculative Approximate Adder for Error Recovery Unit
IRJET - A Speculative Approximate Adder for Error Recovery Unit
IRJET Journal
IRJET- A Review of Approximate Adders for Energy-Efficient Digital Signal Pro...
IRJET- A Review of Approximate Adders for Energy-Efficient Digital Signal Pro...
IRJET Journal
IRJET- Accuracy Configurable Adder
IRJET- Accuracy Configurable Adder
IRJET Journal
Fa35880883
Fa35880883
IJERA Editor
IRJET- Asic Implementation of Efficient Error Detection for Floating Poin...
IRJET- Asic Implementation of Efficient Error Detection for Floating Poin...
IRJET Journal
ApproxBioWear: Approximating Additions for Efficient Biomedical Wearable Comp...
ApproxBioWear: Approximating Additions for Efficient Biomedical Wearable Comp...
Subhajit Sahu
IRJET- Arithmetic Logic Unit Design with Comparison Power Consumption on Diff...
IRJET- Arithmetic Logic Unit Design with Comparison Power Consumption on Diff...
IRJET Journal
IRJET-Hardware Co-Simulation of Classical Edge Detection Algorithms using Xil...
IRJET-Hardware Co-Simulation of Classical Edge Detection Algorithms using Xil...
IRJET Journal
Recommended
IRJET - A Speculative Approximate Adder for Error Recovery Unit
IRJET - A Speculative Approximate Adder for Error Recovery Unit
IRJET Journal
IRJET- A Review of Approximate Adders for Energy-Efficient Digital Signal Pro...
IRJET- A Review of Approximate Adders for Energy-Efficient Digital Signal Pro...
IRJET Journal
IRJET- Accuracy Configurable Adder
IRJET- Accuracy Configurable Adder
IRJET Journal
Fa35880883
Fa35880883
IJERA Editor
IRJET- Asic Implementation of Efficient Error Detection for Floating Poin...
IRJET- Asic Implementation of Efficient Error Detection for Floating Poin...
IRJET Journal
ApproxBioWear: Approximating Additions for Efficient Biomedical Wearable Comp...
ApproxBioWear: Approximating Additions for Efficient Biomedical Wearable Comp...
Subhajit Sahu
IRJET- Arithmetic Logic Unit Design with Comparison Power Consumption on Diff...
IRJET- Arithmetic Logic Unit Design with Comparison Power Consumption on Diff...
IRJET Journal
IRJET-Hardware Co-Simulation of Classical Edge Detection Algorithms using Xil...
IRJET-Hardware Co-Simulation of Classical Edge Detection Algorithms using Xil...
IRJET Journal
IRJET- Smart Wiper System for Skyscrapers
IRJET- Smart Wiper System for Skyscrapers
IRJET Journal
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...
iosrjce
IRJET- Design of 16 Bit Low Power Vedic Architecture using CSA & UTS
IRJET- Design of 16 Bit Low Power Vedic Architecture using CSA & UTS
IRJET Journal
Comparative study to realize an automatic speaker recognition system
Comparative study to realize an automatic speaker recognition system
IJECEIAES
SFQ MULTIPLIER
SFQ MULTIPLIER
Darshan B B
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
IRJET Journal
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
IRJET Journal
Mixed approach for scheduling process in wimax for high qos
Mixed approach for scheduling process in wimax for high qos
eSAT Journals
Motion compensation for hand held camera devices
Motion compensation for hand held camera devices
eSAT Journals
Building impedance matching network based on s parameter from manufacturer
Building impedance matching network based on s parameter from manufacturer
Journal Papers
Design of a Novel Multiplier and Accumulator using Modified Booth Algorithm w...
Design of a Novel Multiplier and Accumulator using Modified Booth Algorithm w...
IRJET Journal
M367578
M367578
IJERA Editor
High performance parallel prefix adders with fast carry chain logic
High performance parallel prefix adders with fast carry chain logic
iaemedu
Optimized Carry Speculative Adder
Optimized Carry Speculative Adder
ijtsrd
Floating point units
Floating point units
dipugovind
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...
Silicon Mentor
Clock Gating of Streaming Applications for Power Minimization on FPGA’s
Clock Gating of Streaming Applications for Power Minimization on FPGA’s
IRJET Journal
Enhanced low power, fast and area efficient carry select adder
Enhanced low power, fast and area efficient carry select adder
eSAT Publishing House
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...
IRJET Journal
IRJET - Approximate Unsigned Multiplier with Varied Error Rate
IRJET - Approximate Unsigned Multiplier with Varied Error Rate
IRJET Journal
IRJET- Implementation and Analysis of Hybridization in Modified Parallel Adde...
IRJET- Implementation and Analysis of Hybridization in Modified Parallel Adde...
IRJET Journal
MODIFIED CARRY SELECT ADDER WITH BKA AND MGDI TECHNIQUE
MODIFIED CARRY SELECT ADDER WITH BKA AND MGDI TECHNIQUE
IRJET Journal
More Related Content
What's hot
IRJET- Smart Wiper System for Skyscrapers
IRJET- Smart Wiper System for Skyscrapers
IRJET Journal
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...
iosrjce
IRJET- Design of 16 Bit Low Power Vedic Architecture using CSA & UTS
IRJET- Design of 16 Bit Low Power Vedic Architecture using CSA & UTS
IRJET Journal
Comparative study to realize an automatic speaker recognition system
Comparative study to realize an automatic speaker recognition system
IJECEIAES
SFQ MULTIPLIER
SFQ MULTIPLIER
Darshan B B
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
IRJET Journal
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
IRJET Journal
Mixed approach for scheduling process in wimax for high qos
Mixed approach for scheduling process in wimax for high qos
eSAT Journals
Motion compensation for hand held camera devices
Motion compensation for hand held camera devices
eSAT Journals
Building impedance matching network based on s parameter from manufacturer
Building impedance matching network based on s parameter from manufacturer
Journal Papers
Design of a Novel Multiplier and Accumulator using Modified Booth Algorithm w...
Design of a Novel Multiplier and Accumulator using Modified Booth Algorithm w...
IRJET Journal
M367578
M367578
IJERA Editor
High performance parallel prefix adders with fast carry chain logic
High performance parallel prefix adders with fast carry chain logic
iaemedu
Optimized Carry Speculative Adder
Optimized Carry Speculative Adder
ijtsrd
Floating point units
Floating point units
dipugovind
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...
Silicon Mentor
Clock Gating of Streaming Applications for Power Minimization on FPGA’s
Clock Gating of Streaming Applications for Power Minimization on FPGA’s
IRJET Journal
Enhanced low power, fast and area efficient carry select adder
Enhanced low power, fast and area efficient carry select adder
eSAT Publishing House
What's hot
(18)
IRJET- Smart Wiper System for Skyscrapers
IRJET- Smart Wiper System for Skyscrapers
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...
IRJET- Design of 16 Bit Low Power Vedic Architecture using CSA & UTS
IRJET- Design of 16 Bit Low Power Vedic Architecture using CSA & UTS
Comparative study to realize an automatic speaker recognition system
Comparative study to realize an automatic speaker recognition system
SFQ MULTIPLIER
SFQ MULTIPLIER
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
Mixed approach for scheduling process in wimax for high qos
Mixed approach for scheduling process in wimax for high qos
Motion compensation for hand held camera devices
Motion compensation for hand held camera devices
Building impedance matching network based on s parameter from manufacturer
Building impedance matching network based on s parameter from manufacturer
Design of a Novel Multiplier and Accumulator using Modified Booth Algorithm w...
Design of a Novel Multiplier and Accumulator using Modified Booth Algorithm w...
M367578
M367578
High performance parallel prefix adders with fast carry chain logic
High performance parallel prefix adders with fast carry chain logic
Optimized Carry Speculative Adder
Optimized Carry Speculative Adder
Floating point units
Floating point units
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...
Clock Gating of Streaming Applications for Power Minimization on FPGA’s
Clock Gating of Streaming Applications for Power Minimization on FPGA’s
Enhanced low power, fast and area efficient carry select adder
Enhanced low power, fast and area efficient carry select adder
Similar to IRJET - High Speed Approximation Error Tolerance Adders for Image Processing Applications
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...
IRJET Journal
IRJET - Approximate Unsigned Multiplier with Varied Error Rate
IRJET - Approximate Unsigned Multiplier with Varied Error Rate
IRJET Journal
IRJET- Implementation and Analysis of Hybridization in Modified Parallel Adde...
IRJET- Implementation and Analysis of Hybridization in Modified Parallel Adde...
IRJET Journal
MODIFIED CARRY SELECT ADDER WITH BKA AND MGDI TECHNIQUE
MODIFIED CARRY SELECT ADDER WITH BKA AND MGDI TECHNIQUE
IRJET Journal
IRJET- FPGA Implementation of High Speed and Low Power Speculative Adder
IRJET- FPGA Implementation of High Speed and Low Power Speculative Adder
IRJET Journal
IRJET- Design of 1 Bit ALU using Various Full Adder Circuits
IRJET- Design of 1 Bit ALU using Various Full Adder Circuits
IRJET Journal
IRJET - Distributed Arithmetic Method for Complex Multiplication
IRJET - Distributed Arithmetic Method for Complex Multiplication
IRJET Journal
IRJET - Comparison of Vedic, Wallac Tree and Array Multipliers
IRJET - Comparison of Vedic, Wallac Tree and Array Multipliers
IRJET Journal
Design of an Efficient Reconfigurable Fir Filter for Multi Standard Digital u...
Design of an Efficient Reconfigurable Fir Filter for Multi Standard Digital u...
IRJET Journal
Design of 64 bit error tolerant adder
Design of 64 bit error tolerant adder
iaemedu
Design of 64 bit error tolerant adder
Design of 64 bit error tolerant adder
iaemedu
Design of 64 bit error tolerant adder
Design of 64 bit error tolerant adder
IAEME Publication
Design and Implementation of Test Vector Generation using Random Forest Techn...
Design and Implementation of Test Vector Generation using Random Forest Techn...
IRJET Journal
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...
IOSR Journals
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Sravankumar Samboju
Hardware Implementation of Two’s Compliment Multiplier with Partial Product b...
Hardware Implementation of Two’s Compliment Multiplier with Partial Product b...
IJERA Editor
High Speed and Area Efficient Matrix Multiplication using Radix-4 Booth Multi...
High Speed and Area Efficient Matrix Multiplication using Radix-4 Booth Multi...
IRJET Journal
Analysis of low pdp using SPST in bilateral filter
Analysis of low pdp using SPST in bilateral filter
IJTET Journal
IRJET- Development of General Purpose Controller Board
IRJET- Development of General Purpose Controller Board
IRJET Journal
Comparison and Simulation of Digital Adders
Comparison and Simulation of Digital Adders
IRJET Journal
Similar to IRJET - High Speed Approximation Error Tolerance Adders for Image Processing Applications
(20)
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...
IRJET - High Speed Inexact Speculative Adder using Carry Look Ahead Adder...
IRJET - Approximate Unsigned Multiplier with Varied Error Rate
IRJET - Approximate Unsigned Multiplier with Varied Error Rate
IRJET- Implementation and Analysis of Hybridization in Modified Parallel Adde...
IRJET- Implementation and Analysis of Hybridization in Modified Parallel Adde...
MODIFIED CARRY SELECT ADDER WITH BKA AND MGDI TECHNIQUE
MODIFIED CARRY SELECT ADDER WITH BKA AND MGDI TECHNIQUE
IRJET- FPGA Implementation of High Speed and Low Power Speculative Adder
IRJET- FPGA Implementation of High Speed and Low Power Speculative Adder
IRJET- Design of 1 Bit ALU using Various Full Adder Circuits
IRJET- Design of 1 Bit ALU using Various Full Adder Circuits
IRJET - Distributed Arithmetic Method for Complex Multiplication
IRJET - Distributed Arithmetic Method for Complex Multiplication
IRJET - Comparison of Vedic, Wallac Tree and Array Multipliers
IRJET - Comparison of Vedic, Wallac Tree and Array Multipliers
Design of an Efficient Reconfigurable Fir Filter for Multi Standard Digital u...
Design of an Efficient Reconfigurable Fir Filter for Multi Standard Digital u...
Design of 64 bit error tolerant adder
Design of 64 bit error tolerant adder
Design of 64 bit error tolerant adder
Design of 64 bit error tolerant adder
Design of 64 bit error tolerant adder
Design of 64 bit error tolerant adder
Design and Implementation of Test Vector Generation using Random Forest Techn...
Design and Implementation of Test Vector Generation using Random Forest Techn...
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Hardware Implementation of Two’s Compliment Multiplier with Partial Product b...
Hardware Implementation of Two’s Compliment Multiplier with Partial Product b...
High Speed and Area Efficient Matrix Multiplication using Radix-4 Booth Multi...
High Speed and Area Efficient Matrix Multiplication using Radix-4 Booth Multi...
Analysis of low pdp using SPST in bilateral filter
Analysis of low pdp using SPST in bilateral filter
IRJET- Development of General Purpose Controller Board
IRJET- Development of General Purpose Controller Board
Comparison and Simulation of Digital Adders
Comparison and Simulation of Digital Adders
More from IRJET Journal
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
IRJET Journal
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
IRJET Journal
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
IRJET Journal
Effect of Camber and Angles of Attack on Airfoil Characteristics
Effect of Camber and Angles of Attack on Airfoil Characteristics
IRJET Journal
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
IRJET Journal
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
IRJET Journal
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
IRJET Journal
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
IRJET Journal
A REVIEW ON MACHINE LEARNING IN ADAS
A REVIEW ON MACHINE LEARNING IN ADAS
IRJET Journal
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
IRJET Journal
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
IRJET Journal
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
IRJET Journal
Survey Paper on Cloud-Based Secured Healthcare System
Survey Paper on Cloud-Based Secured Healthcare System
IRJET Journal
Review on studies and research on widening of existing concrete bridges
Review on studies and research on widening of existing concrete bridges
IRJET Journal
React based fullstack edtech web application
React based fullstack edtech web application
IRJET Journal
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
IRJET Journal
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
IRJET Journal
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
IRJET Journal
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
IRJET Journal
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
IRJET Journal
More from IRJET Journal
(20)
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
Effect of Camber and Angles of Attack on Airfoil Characteristics
Effect of Camber and Angles of Attack on Airfoil Characteristics
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
A REVIEW ON MACHINE LEARNING IN ADAS
A REVIEW ON MACHINE LEARNING IN ADAS
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
Survey Paper on Cloud-Based Secured Healthcare System
Survey Paper on Cloud-Based Secured Healthcare System
Review on studies and research on widening of existing concrete bridges
Review on studies and research on widening of existing concrete bridges
React based fullstack edtech web application
React based fullstack edtech web application
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
Recently uploaded
Churning of Butter, Factors affecting .
Churning of Butter, Factors affecting .
Satyam Kumar
young call girls in Green Park🔝 9953056974 🔝 escort Service
young call girls in Green Park🔝 9953056974 🔝 escort Service
9953056974 Low Rate Call Girls In Saket, Delhi NCR
HARMONY IN THE HUMAN BEING - Unit-II UHV-2
HARMONY IN THE HUMAN BEING - Unit-II UHV-2
RajaP95
★ CALL US 9953330565 ( HOT Young Call Girls In Badarpur delhi NCR
★ CALL US 9953330565 ( HOT Young Call Girls In Badarpur delhi NCR
9953056974 Low Rate Call Girls In Saket, Delhi NCR
complete construction, environmental and economics information of biomass com...
complete construction, environmental and economics information of biomass com...
asadnawaz62
🔝9953056974🔝!!-YOUNG call girls in Rajendra Nagar Escort rvice Shot 2000 nigh...
🔝9953056974🔝!!-YOUNG call girls in Rajendra Nagar Escort rvice Shot 2000 nigh...
9953056974 Low Rate Call Girls In Saket, Delhi NCR
Oxy acetylene welding presentation note.
Oxy acetylene welding presentation note.
eptoze12
INFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETE
INFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETE
roselinkalist12
Artificial-Intelligence-in-Electronics (K).pptx
Artificial-Intelligence-in-Electronics (K).pptx
britheesh05
What are the advantages and disadvantages of membrane structures.pptx
What are the advantages and disadvantages of membrane structures.pptx
wendy cai
Design and analysis of solar grass cutter.pdf
Design and analysis of solar grass cutter.pdf
Tagore Institute of Engineering And Technology
Architect Hassan Khalil Portfolio for 2024
Architect Hassan Khalil Portfolio for 2024
hassan khalil
GDSC ASEB Gen AI study jams presentation
GDSC ASEB Gen AI study jams presentation
GDSCAESB
chaitra-1.pptx fake news detection using machine learning
chaitra-1.pptx fake news detection using machine learning
misbanausheenparvam
IVE Industry Focused Event - Defence Sector 2024
IVE Industry Focused Event - Defence Sector 2024
Mark Billinghurst
9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf
9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf
9953056974 Low Rate Call Girls In Saket, Delhi NCR
young call girls in Rajiv Chowk🔝 9953056974 🔝 Delhi escort Service
young call girls in Rajiv Chowk🔝 9953056974 🔝 Delhi escort Service
9953056974 Low Rate Call Girls In Saket, Delhi NCR
Gurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort service
Gurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort service
jennyeacort
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
VICTOR MAESTRE RAMIREZ
Call Us -/9953056974- Call Girls In Vikaspuri-/- Delhi NCR
Call Us -/9953056974- Call Girls In Vikaspuri-/- Delhi NCR
9953056974 Low Rate Call Girls In Saket, Delhi NCR
Recently uploaded
(20)
Churning of Butter, Factors affecting .
Churning of Butter, Factors affecting .
young call girls in Green Park🔝 9953056974 🔝 escort Service
young call girls in Green Park🔝 9953056974 🔝 escort Service
HARMONY IN THE HUMAN BEING - Unit-II UHV-2
HARMONY IN THE HUMAN BEING - Unit-II UHV-2
★ CALL US 9953330565 ( HOT Young Call Girls In Badarpur delhi NCR
★ CALL US 9953330565 ( HOT Young Call Girls In Badarpur delhi NCR
complete construction, environmental and economics information of biomass com...
complete construction, environmental and economics information of biomass com...
🔝9953056974🔝!!-YOUNG call girls in Rajendra Nagar Escort rvice Shot 2000 nigh...
🔝9953056974🔝!!-YOUNG call girls in Rajendra Nagar Escort rvice Shot 2000 nigh...
Oxy acetylene welding presentation note.
Oxy acetylene welding presentation note.
INFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETE
INFLUENCE OF NANOSILICA ON THE PROPERTIES OF CONCRETE
Artificial-Intelligence-in-Electronics (K).pptx
Artificial-Intelligence-in-Electronics (K).pptx
What are the advantages and disadvantages of membrane structures.pptx
What are the advantages and disadvantages of membrane structures.pptx
Design and analysis of solar grass cutter.pdf
Design and analysis of solar grass cutter.pdf
Architect Hassan Khalil Portfolio for 2024
Architect Hassan Khalil Portfolio for 2024
GDSC ASEB Gen AI study jams presentation
GDSC ASEB Gen AI study jams presentation
chaitra-1.pptx fake news detection using machine learning
chaitra-1.pptx fake news detection using machine learning
IVE Industry Focused Event - Defence Sector 2024
IVE Industry Focused Event - Defence Sector 2024
9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf
9953056974 Call Girls In South Ex, Escorts (Delhi) NCR.pdf
young call girls in Rajiv Chowk🔝 9953056974 🔝 Delhi escort Service
young call girls in Rajiv Chowk🔝 9953056974 🔝 Delhi escort Service
Gurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort service
Gurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort service
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
VICTOR MAESTRE RAMIREZ - Planetary Defender on NASA's Double Asteroid Redirec...
Call Us -/9953056974- Call Girls In Vikaspuri-/- Delhi NCR
Call Us -/9953056974- Call Girls In Vikaspuri-/- Delhi NCR
IRJET - High Speed Approximation Error Tolerance Adders for Image Processing Applications
1.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 04 | Apr 2020 www.irjet.net p-ISSN: 2395-0072 © 2020, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1241 HIGH SPEED APPROXIMATION ERROR TOLERANCE ADDERS FOR IMAGE PROCESSING APPLICATIONS L. Prasanna mariya1, K B Sangavi2 1PG Graduate, Department of Electronics and Communication Engineering, Sri Shakthi Institute of Engineering and Technology, Coimbatore-641062, Tamilnadu, India. 2Assistant Professor, Department of Electronics and Communication Engineering, Sri Shakthi Institute of Engineering and Technology, Coimbatore-641062, Tamilnadu, India. ---------------------------------------------------------------------***---------------------------------------------------------------------------- Abstract: Addition is the one of the basic arithmetic operations, which are used in many VLSI systems like microprocessors and application specific DSP architectures .The approximation error tolerance adders are efficient in terms of area, power and accuracy while considering the basic structure of adders. In this paper, proposes a design of adder, which improves the overall performance based on static segmentation and accuracy adjustment logic (AAL) methods. During this implementation SAET adder is meant using full adder and approximation full adder cells with reduced complexity at gate level. In this paper, the performance of 8 bit conventional and proposed adders are explained. Area, power and delay analysis are compared for various adders using approximation adder technique. KEYWORDS: Significance approximation(SA), Error tolerance(ET), Digital signal processing (DSP), Image blending, static segment adder(SSA), Accuracy adjustment logic (AAL) , VLSI . 1. INTRODUCTION The functional unit of VLSI systems and application specific DSP architectures performance is totally depends upon adders. The filters are widely used in DSP for removing unwanted features from a signal in order to improve the quality of the signal and it is used in communication system applications such as echo cancellation, noise reduction, speech and waveform synthesis etc.. Adders are widely used in the different types of the digital filter applications. The design performance will be degraded, when adders are consumes large energy (or) processed as too slow. Approximation addition has been carried out for achieving area, power and speed improvements at the accuracy in the field. This paper proposes a design of approximation adder, which improves the overall performance based on static segmentation and (AAL) method to improve the accuracy derived from negating lower bytes of input operands. The content of the paper is organized as follows, Section 2 discuss about the conventional and error tolerant adder theory. Section 3 explains about the proposed significance approximation error tolerant carry select adder. Sections 4 presents comparison of simulation results and chapter 5 deals with image processing application using proposed SAET- CSLA. Finally conclusion. 2. CONVENTIONAL AND ERROR TOLERANT ADDERS THEORY 2.1 CONVENTIONAL 8 BIT CSLA Ripple carry adder is that each adder has to wait for the arrival of its carry input signal before the actual addition starts. In carry select adder is to use blocks of two ripple carry adder, one of which is fed with a constant ‘0’ carry in, while the other is fed with constant ‘1’ carry in. Both blocks can calculate in parallel. Multiplexers are used to select the correct one of both partial sums of the carry in signal. The resulting carryout is selected and propagated to the next carry select block .for addition full adder is beneficial that have multiple bits in each of its operands. Three inputs are taken and produce a sum and a carryout as outputs[6,8,11,14]. Full adder logic has 13 basic logic gates (AND, OR and NOT gates), which are wont to implement the primarily gate level structure (2 Exor gates (2*5) +3) and 6 logic delays. The inputs have an equivalent weight 2i, the sum output features a weight of 2i, and therefore the carryout output features a weight of 2(i+1) . The truth table and k map minimization of full adder is shown Table 1 and Fig. 1 respectively. From k map, the minimized expression is obtained. The sum and carry expression of the logical gate implementation is shown in Fig. 2. Using Full adder truth table (Table 1), the approximation logic comparisons are done. TABLE 1 TRUTH TABLE FOR FULL ADDER
2.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 04 | Apr 2020 www.irjet.net p-ISSN: 2395-0072 © 2020, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1242 Fig .1 KMAP MINIMIZATION OF FULL ADDER Fig .2 LOGIC IMPLEMENTATION OF FULL ADDER 2.2 8 BIT ERROR TOLERANT CSLA Approximation adders are derived from accurate adders based on various approximation which have incorrect outputs for sum and carryout for more input combinations. The input is considered only with the uniform distribution for simplicity[5]. Approximation addition is used for low power and high speed circuit design. This technique specially developed for the DSP for increase the throughput (or)to reduce the power consumption in image processing systems .a lot of the design methods of the low power approximation adders were proposed in the literatures[5,16].some applications need an approximation adder to operate at high frequencies such as video processing .in this approximation full adder are constructed by modifying the conventional full adder in the gate level of carry signal is independent of carry input. Within the approximation logic, approximation is chosen since it gives minimum errors in comparison to other approximations. In Sum it shows only 2 errors and for carry, there is no error as shown in Table.2. K map minimization for approximation Full adder gate level implementation is completed and represented in Fig.3. Approximation Full adder logic has 2 errors in sum output and no error in carry output, where all the input bits are either ‘0’s or ‘1’s. Whereas for all other sum and carry values, there's no change in outputs TABLE: 2 TRUTH TABLE FOR APPROXIMATION FULL ADDER Fig .3 K MAP OF APPROXIMATION FULL ADDER Fig.4 LOGIC IMPLEMENTATION OF APPROXIMATION FULL ADDER Logic implementation of Approximation full adder shown in Fig.1.4, has 6 basic logic gates and 4 delays rather than 13 basic logic gates and 6 delays of conventional full adder. . When the approximation is applied, only the 2 combinations (000 or 111) of inputs end in error, all the remaining combinations are correct. When all the inputs are 1 then sum is an error (i.e., rather than 1 sum is 0) and when all the inputs are 0 then sum is a mistake (i.e., rather than 0 sum is 1). 3. PROPOSED SIGNIFICANCE APPROXIMATION ERROR TOLERANT ADDER Error-tolerance (ET) deals with the use of defective circuitry that occasionally produces an errors. This proposed significance approximation error concept is an integration of conventional CSLA and ET-CSLA for the system which improve accuracy of the output results. Error can be tolerated at some threshold for approximation result in approximation adder [7, 11].
3.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 04 | Apr 2020 www.irjet.net p-ISSN: 2395-0072 © 2020, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1243 3.1 SEGMENTATION AND AAL Segmentation based ETA the input operands are divided into accurate part and inaccurate parts. The 8 bit adder is divided by 4bit accurate part and 4 bit inaccurate part. Normal addition is used for higher order bits of the input operands .ripple carry adder is choose as accurate part. In accurate part divided into carry free addition block and control block. If input values are ‘1’, control signal is high. If both values are different (or) ‘0’, normal XOR is performed and proceeding the operation. AAL is enable for higher order segment selection of input operands and lower order segment is selected for SSA. Accuracy increased by static segment method with AAL. Addition techniques for SSA, Two 8-bit input operands are: Augend (A) = 1000 0101 Addend (B) = 0000 0001 Addition (conventional sum) = 134 The addition technique used in SSA method is given in steps as follows: Step 1: Segmentation A = 1000 01011111 1111 100001012 (4 bit) B = 0000 0001 1111 1111 000000012 (4 bit) Step 2: 4-bit Addition Now we have; Aseg ½ 1012 Bseg ½ 0012 Let Z = Aseg + Bseg =0101 + 0001 +1(Accuracy adjustment logic) Thus, Z ({C,Sum}) = 00111 (5 bit) Step 3: With AAL output ,the addition is expanded and ones are padded. Thus, SSA Out =001111111 (9 bit) = 135 OE= |134-135|=1 OE Tolerance (%) = (1/134) *100% = 0.01% Accuracy = (1 - (1/134)) *100%= 99.9% 3.2 ACCURATE PART In this part, the traditional 8 bit conventional Carry select adder is applied to preserve its correctness since the upper order bits play a crucial role than lower order bits for better accuracy. 3.3 INACCURATE PART In this part, 8 bit ET-Carry select adder is chosen for inaccurate a part of circuit since it's simplest one for many power saving and requires less hardware circuitry. The proposed SAET-CSLA adder has gates which are considerably fewer than conventional CSLA and slightly quite ET-CSLA. In 8 Bit dual ripple carry accurate part, adder requires (2 RCA* 4FA in each RCA) 2*4*13 = 104 gates, inaccurate a part of adder requires (1 RCA* 4 AFA in each RCA) 1*4*6 = 24 and for multiplexer it requires gates. Hence a neighborhood reduction of 19.81 what's obtained for proposed SAET-CSLA adder in comparison with conventional CSLA. 3.4 ACCURACY CALCULATION The addition should actually yield from two operands, if normal arithmetic has been applied. The various terminologies utilized in this work are as Follows: 1. Overall error (OE) is the difference between the outputs of conventional adder (Rc) and approximation adder (RE). 2. Percentage of error Tolerance = [OE/R c]*100% (the results are represented in decimal numbers). 3. Accuracy (ACC) of an adder indicates the correctness of the adder output for a particular input. ACC = (1-(OE/ Rc))*100%. 4. Minimum Acceptable Accuracy (MAA) is defined as some errors lower than a threshold value are allowed to exist at the output of adder to meet the requirement of whole system. 5. Acceptance Probability (AP): The probability that the adder accuracy is above the minimum acceptable accuracy. 6. Minimum Accuracy of an adder is higher than the minimum acceptable accuracy. The total error generated are often computed by the subsequent equation [1]: Overall Error (OE) = | Rc– Re | -----------------------[1] Where, Re is that the result obtain from SAET-CSLA adder and Rc denotes the right result. OE, OE Tolerance, Accuracy = 99:927% (Accuracy of an adder with reference to the 2 input operands) are derived.
4.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 04 | Apr 2020 www.irjet.net p-ISSN: 2395-0072 © 2020, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1244 Fig.5 8BIT PROPOSED SAET-CSLA 4. SIMULATION RESULT COMPARISION 4.1 SIMULATION RESULT Xilinx ISE design suite 14.7 software is used to design the conventional and proposed adders for analyze the performance. The proposed SSA adder accuracy is greatly increased by using AAL and static segment method. The worst case accuracy range can varies from 50% to 94%. SSA achieves 13.84%, 50.06%, and 13.13% computational speed improvement when compared to existing conventional CSLA, conventional RCA. It consumes more area (8 LUTs) than existing ETA. Whereas, the proposed SSA consumes less energy using multiplexer switching. In this proposed adder design, from 0 to 255 range of input operands are playing a important role in the contrast digital signal(high, low and medium) are represented. But for improved ET- CSLA is kind of 50% accurate for upper input operands. In SSA design, it considered all the input operands to achieve high performance and this design can be better solution to get high accuracy for all the error tolerant applications like image blending, defect detection machine in vision applications, contrast stretching in image processing applications , audio and video processing, etc. One of the applications is implemented and presented in the following section. That the error tolerance performance of the adder for all input operands are greatly improved using SAET-CSLA. Fig.6 8 BIT CARRY LOOK AHEAD ADDER SIMULATION OUTPUT Fig .7 8 BIT APPROXIMATION CARRY LOOK AHEAD ADDER Fig .8 8 BIT RIPPLE CARRY ADDER SIMULATION OUTPUT Fig .9 APPROXIMATION RCA SIMULATIONS
5.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 04 | Apr 2020 www.irjet.net p-ISSN: 2395-0072 © 2020, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1245 OUTPUT Fig .10 8 BIT CSA SIMULATION OUTPUT Fig 11 8BIT APPROXIMATION CSA OUTPUT From the simulation result the report analysis are tabulated for conventional and error tolerant approximation adder of RCA, CLA and CSLA adders .This technique reduces the propagation delay and power consumption .And also improves the overall performance accuracy of the circuit. TABLE . 3 COMPARISON OF ADDERS FOR CSLA TABLE .4 COMPARISION OF ADDERS 5. FUTURE APPLICATION OF PROPOSED SAET-CSLA IN IMAGE PROCESSING In image processing image blending operation is performed supported image addition principle, but different weights are to tend for images in order that it gives a sense of blending or transparency. As per the equation in below the images were added G(X,Y)=(1- α)F1(X,Y)+ α F2(X,Y) where, α is that the blending ratio which determines the influence of every input image within the output. By varying the values of α from 0 to 1, a cool transition between one image to a different is performed. This operator forms a mix of two input images of an equivalent size. Almost like pixel addition, the worth of every pixel within the output image may be a linear combination of the corresponding pixel values within the input images. The coefficients are user-specified and before combining them, the ratio is defined by scaling each image. These proportions are applied such the output pixel values don't exceed the utmost pixel value. Image blending using 8 bit proposed SAET -CSLA f1 and f2 are the 2 input images. In some applications f2 also can be a continuing, thus allowing a continuing offset
6.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 04 | Apr 2020 www.irjet.net p-ISSN: 2395-0072 © 2020, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1246 value to be added to one image. Α can either be a continuing factor for all pixels within the image or are often determined for every pixel separately employing a mask. The dimensions of the mask must then be identical with the dimensions of the pictures. Architecture of image blending is shown in fig.12. F1 and f2 are the 2 input images (255 × 255) are separately given to 2 different partition blocks. By a multiplication factor the partitioned images are multiplied. One among the pictures is multiplied by the factor α and other by the factor( 1-α). The multiplied images are then added with the proposed 8 bit SAET-CSLA. Α is that the variable which determines the measure of blending of output resolution. Image blending application is performed using proposed SAET-CSLA and therefore the input and outputs are shown in fig.13. Verilog code is employed to construct the adders and therefore the image blending operation is performed in mat lab using proposed SAET- CSLA by varying the intensity factor to urge the high accuracy images. Variation in α alters the foreground and background pixels of blended image parameters like sharpness, brightness and contrast. From the fig.5.2. It’s noted that increasing the worth of α enhances the standard of the blended image. Fig. 12 ARCHITECTURE OF IMAGE BLENDING USING PROPOSED 8 BIT SAET-CSLA Fig. 13 F1 AND F2 IMAGES BLENDING AND FOR 6. CONCLUSION SAET-CSLA adder structure is applicable to general purpose design, with a couple of exceptions. The necessary for the quick response for increasingly the large data sets, the adder should be high accuracy and fast. During this proposed adder, minimum error tolerance is obtained by conventional full adder logic within the accurate part so as to extend the accuracy at the foremost significance level. The error tolerant adder is meant using approximate full adder cells with reduced complexity at the gate level within the inaccurate part. 8 bit conventional, ET and proposed 8 bit adders are implemented. For all possible 216 input combinations, performance analysis is completed and the average error computed smaller amount than I chronicles. The error of the proposed adder are often reduced by analyzing the relation between the input bit patterns and approximation logic. The SAET for CSA design has possible solution to attain high accuracy image outputs for all the range of input operands in image processing applications. The ET-CSLA can attain an improvement in both the facility in consumption also as well as speed and area efficient performance. By accuracy adjustment logic and static segment method the accuracy and speed are increased in the proposed adder. Performance analysis is carried out and the worst case error is computed for all the possible input combinations. When compared with conventional ETA, proposed method of adders consumes less energy and notable high speed with computational accuracy error 0.64%.so thus proposed method of approximate adders will result in higher quality for all the kinds of error tolerant applications. REFERENCES [1] Gupta V, Mohapatra D, Park SP, Raghunathan A, Roy K (2011) IMPACT: “imprecise adders for low-power approximate computing”. Proc IEEE/ACM International Symposium on Low-Power Electronics and Design 409– 414 . [2] He Y, Chang CH, Gu J (2005) “An area efficient 64-bit square root carry-select adder for low power applications”. Proc IEEE Int Symp Circ S 4:4082–4085. [3] Hegde R, Shanbhag N (1999) “Energy-efficient signal processing via algorithmic noise-tolerance”. Proc IEEE/ACM Int Symp Low Power Electron Des 30–35. [4] Jayanthi AN, Ravichandran CS (2012)” Design of error tolerant adder”. American Journal of Applied Sci 9(6):818–824. [5] Kim Y, Kim L-S (2001) “A low power carry select adder with reduced area”. Proc IEEE Int Symp Circ S 4:218–221.
7.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 07 Issue: 04 | Apr 2020 www.irjet.net p-ISSN: 2395-0072 © 2020, IRJET | Impact Factor value: 7.34 | ISO 9001:2008 Certified Journal | Page 1247 [6] V Muralidharan, M Jagadeeswari (2012) “ An enhanced Carry elimination adder for low power VLSI applications”. Int J Eng Res Appl 2(2) 1477–1482. [7] Neeharika R, Venkanna, Kavitha M (2012) “Design of low power high-speed truncation-error tolerant adder and its application in digital signal processing”. Int Eng Res Appl 2(2): 939–944. [8] Parhi KK (2007) “VLSI digital signal processing systems: design and implementation”, 255–279, Wiley. [9] Rawat K, Darwish T, BayoumiM (2002) “ A low power and reduced area Carry select adder”. Proc 45th Midwest Symp Circuit 1:467–470. [10] Saeed V (2007) Vaseghi. Wiley, “Multimedia Signal Processing”. [11] Saxena P, Purohit U, Joshi P (2013) “ Analysis of low power, area efficient and high speed fast adder”. Int J Adv Res Comput Commun Eng 2(9):356–375. [12] Shim B, Sridhara S, Shanbhag N (2004) “Reliable low-power digital signal processing via reduced precision redundancy”. Proc IEEE Trans Very Large Scale Integration Syst 12(no. 5):497–510. [13] Singh S, Kumar D (2011) “Design of area and power efficient modified carry select adder”. Int J Comput Appl 33(No. 3):975–987. [14]Varatkar G, Shanbhag N (2006) “Energy-efficient motion estimation using error-tolerance”. Proc IEEE/ACM Int Symp Low Power Electron Des 113–118.
Download now