A FPGA Implementation of a bilateral filter for image processing is given which does spatial averaging without smoothing edges. Kernel based processing is possible, which means that processing of the entire filter window at one pixel clock cycle. It is also supported by the arrangement of the input data into groups and applied a single clock cycle for a group of pixels. Based on these features, a technique called Spurious Power Suppression Technique (SPST) is implemented in Bilateral Filter to minimize Power Delay Product (PDP). SPST can also dramatically reduce the power by turn off its MSP (Most significant bit) without compromising the computational results to achieve the target parameters. Furthermore, an Original Glitch Diminishing technique is proposed to filter out useless switching power by asserting signals after the data transient period. The SPST can be expanded to a Fine-grain scheme in which the combinational circuits are divided into more than two parts. In Bilateral Filter a kernel of different size can be implemented using SPST which achieve good performance.

1. INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY
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71
Analysis of low pdp using SPST in bilateral
filter
S.ANITHA, B.HEMA,
PG scholar, Kalasalingam Institute of Technology Assp.prof, Kalasalingam Institute of Technology,
Krishnankovil-626126, Virudhunagar(D.T), Krishnankovil-626126, Virudhunagar(D.T),
Email id: anithavasagan@gmail.com Email id: hema.shivam@gmail.com.
Abstract -- A FPGA Implementation of a bilateral filter for image processing is given which does spatial
averaging without smoothing edges. Kernel based processing is possible, which means that processing of the
entire filter window at one pixel clock cycle. It is also supported by the arrangement of the input data into
groups and applied a single clock cycle for a group of pixels. Based on these features, a technique called
Spurious Power Suppression Technique (SPST) is implemented in Bilateral Filter to minimize Power Delay
Product (PDP). SPST can also dramatically reduce the power by turn off its MSP (Most significant bit) without
compromising the computational results to achieve the target parameters. Furthermore, an Original Glitch
Diminishing technique is proposed to filter out useless switching power by asserting signals after the data
transient period. The SPST can be expanded to a Fine-grain scheme in which the combinational circuits are
divided into more than two parts. In Bilateral Filter a kernel of different size can be implemented using SPST
which achieve good performance.
Index Terms -- Bilateral filter, SPST, Image processing, noise reduction, PDP
I. INTRODUCTION
BILATERAL FILTER has a feature of
noise reduction, in addition to improve the visual
quality and allows improving the compressibility of
the image. Bilateral filter [1] consists of two types.
First one is non linear component, second one is linear
component. If both the types are adjusted to reduce
the noise via selective averaging and the amount of
blurring via low pass filter. The bilateral filter is
applied for noise reduction for local tone mapping
method [2], which maps high dynamic range image to
low dynamic range image. The bilateral filter can be
used to medical image processing [3] and non-
destructive testing. The detailed description of a
paper, bilateral filter based on Register Transfer Level
(RTL). The advantages of bilateral filter,
1) The input data are divided into equal groups to
assigned individual pipelines.
2) To increase the internal clock frequency based on
Data flow
3) Reduce the external memory storage.
Various technique have been developed for
reducing the power consumption of VLSI designs,
including voltage scaling, switched capacitance
reduction, power down techniques, dynamic voltage
frequency scaling[4]-[7]. SPST to provide high
accuracy and achieves both power consumption and
average case performance. The existing work dynamic
power consumption by minimizing the switching
capacitance PGC [8] technique was used. In previous
Works, many high quality interpolation based
methods have been [9] proposed. Image scaling
algorithm, cost of hardware and memory also reduced.
For real time applications, less complexity image
scaling processor algorithms are needed for VLSI
implementations [10] – [12].
II. BILATERAL FILTER
Bilateral filter [1] is an edge preserving and
noise reducing smoothing filter for images. The
intensity value at each pixel of an image is replaced
by a weighted average of intensity value from nearby
pixel.
Fig 1: block diagram of bilateral filter
Bilateral filter is a combination of linear
and non linear component. The bilateral filter is
subdivided into three parts. Three parts are register
matrix, photometric filter, geometric filter. Fig.1
presents three parts and their order in the concept.
First the image is converted into pixel value. The pixel
value is given into the register matrix. It reads the data
line by line and arranged for further processing in
Register matrix. The second part is the photometric
filter, which weights the input data according to the
Register
Matrix
Photometric
filter
Geometric
Filter
Data
in
Data out

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intensity of the processed pixels. The filtering process
completed by the geometric filter, and the final output
marked by “Data_out”.
(a) Register matrix:
In register matrix fig.2 kernel based design
concept is applied. As the pixel value is shifted from
one stage to next stage simultaneously. It processes all
25 pixels in one pixel cycle in order to keep reading of
the input lines into the register matrix. The output of
the register matrix is sorted into six groups for one
cycle, fed into the photometric filter component with
the quadruple clock frequency synchronously.
Quadruplication means four pixels per clock signal.
(b) Photometric filter:
After the register matrix process completed,
the six grouped image data are applied to the
photometric filter component fig.3. In photometric
filter look up table created by using photometric
coefficients. The photometric coefficients calculated
by using this formula,
S(ø(m0),ø(m)=exp((-0.5)( ІІø(m0)-ø(m) ІІ/σ ph)2
To avoid the calculation of the expensive
exponential, all possible values of the function
precalculated and stored in the LUT [14]. The
difference of the gray values calculated and directly
interpreted as the address of the corresponding weight
coefficient in the LUT.
Fig 2: Register matrix of the kernel-based
Design
If the gray value difference is greater than the limit,
the weight coefficients set to zero otherwise
corresponding coefficients readout the LUT.
(c) Geometric filter:
Separabilty and symmetry property can be used
for geometric filter component. Because of the
separabilty, the geometric filter is split into vertical
and horizontal parts. The geometric coefficients can
be calculated by using this formula,
C (m0, m) = exp ((-0.5) (ІІm0-mІІ /σ c)2
The coefficients of the geometric component are
labelled “C_0, C_1, and C_2”. Due to the symmetry
of the weight coefficients of the geometric
component, the order of multiplication and addition is
swapped in both the filter parts.
Fig 3: block diagram of photometric filter
C.1 Vertical component part:
The output of photometric filter is coefficients,
mid_pix; pixel weights are given to the geometric
filter. The groups 0,1,3,4,5 and mid_pix 2 are
processed as shown fig 5. The geometrically
symmetrical pixels are accumulated at first and then
multiplied by geometric weight ccoefficients. In this
method the binary adder can be replaced by SPST
adder.

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Fig4: Processing order in photometric filter
Fig 5: vertical part of the geometric filter
Component
All the coefficients for the geometric filter are
constant for the chosen filter window size. Due to the
scaling of the geometric coefficients, it is assured that
the accumulation does not result in a carry. The REG
cols 0, 1, 2 in this part of the design are used to delay
weighted data to maintain synchronicity. After the
multiplication, the weighted values are summed up by
the adder tree to one value bat each internal clock
event. The processing of center column in fig5. The
cantered pixel is weighted and delayed by “Recent” so
this pixel and the remaining pixels in the cantered
column can be fed to the input of the adder tree
simultaneously.
Fig 6: Horizontal part of the geometric filter
Component
C.2 Horizontal component part:
After processing in the vertical dimension,
the filter window is reduced to one row, and its
elements are computed at one internal clock event
each. In order to able to reuse the symmetrical design,
the values of the filtered columns 0, 1, 2, 3, 4 are
stored in the shift registers scoring to the order of their
reception.
Fig7: block diagram of SPST
It consists of two important parts: 1) detection
logic unit 2) adder/subtractor. Example for spurious
transitions demonstrates two negative operands
without and with carry in from the LSP, respectively.
In this case, the results of MSB are predictable;

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therefore, the computations in MSP are useless and
can be neglected. More than two parts by using fine
grain scheme.
Fig8: example for spurious computations
To eliminating the spurious computations not
only can save the power consumption inside the
adder/subtractor in the current stage but also decrease
the glitching noises which cause power wastage inside
the arithmetic circuits in the next stage. Fig 7 the
SPST separate two parts and then latches the input
data of the MSP whenever they do not affect the
computation results.
Fig 9: detection logic unit
III. PROPOSED SPST
The bipartitioned SPST scheme, a detection
logic unit can be used to detect the effective input
ranges. The add/subtractor is divided into LSP and
MSP between eighth and ninth bits. Latches used to
control the input data of the MSP, by using simple
AND gates. Detection logic unit can decide whether
to turn off the MSP or not. The novel glitch-
diminishing technique by adding three 1-bit registers
to control the assertion of the close, sign, and carry-
ctrl signals to further decrease the transient signals
occured in the cascade circuits[15], [16] which are
usually adopted in VLSI architectures designed for
DSP applications.
Fig 10: data latch design
The SPST analysed by two conditions.
(i) When the detection-logic unit turns off the MSP:
The output of the MSP is directly compensated by the
SE unit.
(ii) When the detection-logic unit turns on the MSP:
the MSP circuits must wait for the notification of the
detection-logic unit to turn on the data latches to let
the data in. Hence, the delay caused by the detection-
logic unit will contribute to the delay of the whole
combinational circuitry.
Fig 11: SPST adder using Geometric Filter
IV. SIMULATION RESULTS
The test image eye shown in FIG. Is an 8-b
gray scale image with size of 85 *85 pixels Hence, in
the following, GVmax = 255 are used. The bilateral
filter was implemented in VHDL and simulated with
modelsim. The PDP was simulated using Xilinx. A
test image was filtered by Matlab implementations as
well as the Modelsim simulation, and the filtered
images were compared. The total delay of the output
pixels of our architecture with a kernel size of 5*5
(-61) 1111111111000011 (-196) 1111111100111100
(-205) 1111111100110011 (-52) 1111111111001100
(-266) 1111111011110110 (-248) 1111111100001000
Carr-ctrl
sign

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pixels applied to an image of 85*85 pixels is 7225
cycles.
Input image
Modelsim output image
In register matrix 5 *5 kernel size pixels are
being processed. Finally, the output of the register
matrix is sorted into 5 groups and center pixel value is
seperately obtained.
The output of the register matrix is given to
tha photometric filter. In photomtric filter Look Up
Table can be created and the photometric coefficients
are got. By multiplying the photometric coefficient
and group value we can get a weighted coefficients.
The output of photometric filter is given to
the geometric filter. In this filter, vertical part and
horizontal part process is done seperately. The vertical
part component carried out weighted coefficients and
horizontal component part carried out photometric
coefficients.
Mat lab output image
Input noisy image

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Each 5 *5 pixels to calculate the power,
area, delay, which compare normal binary adder and
SPST adder.
Table1: power consumption of proposed SPST
V. CONCLUSION:
In this paper, the SPST technique was
proposed to minimize area, power and delay. SPST
adder, which provides better performance
improvement with a slight accuracy loss. The bilateral
filter architecture assures a constant processing delay,
independent of the filter window size. The total
consumed power for this technique is 143 mW which
is 15.88% power reduction when compared to binary
adder technique.
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