This document presents the design and implementation of an area efficient AHB arbiter IP core in VHDL. The proposed arbiter can handle bus requests from 16 masters and grant access to the bus using a round-robin priority scheme. It was synthesized using Xilinx tools and achieved a maximum frequency of 319.519MHz while utilizing 1273 slices, representing a 5.5% improvement in area over previous designs. The arbiter supports features required by the AMBA specification such as split transactions and error handling. Simulation results confirmed the correct arbitration behavior and priority shifting between multiple concurrent requests.