2. In this lecture
• Pin layout and signal description
• Memory Addressing
• I/O Addressing
Zelalem Birhanu, AAiT 2
3. 8086 Features
40 pin CERDIP or plastic
package
5, 8 and 10MHz clock rate
Can operate in minimum or
maximum mode
o Minimum- single
processor mode
o Maximum-
multiprocessor mode
Zelalem Birhanu, AAiT 3
5. Signal Description
• Signals can be categorized based on their
function
Memory and I/O interfacing signals
Status signals
Interrupt signals
Other signals
Zelalem Birhanu, AAiT 5
6. Memory Interfacing Signals
8086
Memory
(up to 1MB)
20-bit Address
16-bit Data
8086 uses the same lines for address and data
These lines are time multiplexed (the same lines are
used as address lines and data lines at different times)
Zelalem Birhanu, AAiT 6
7. Memory Interfacing Signals…cntd
• A bus cycle includes applying physical address and
accessing (reading / writing) a byte of data from
memory location
• A bus cycle consists of four clock cycles (T1, T2,
T3, T4) and optional waiting clock cycles Tw
Zelalem Birhanu, AAiT 7
8. Memory Interfacing Signals…cntd
T1: The address is put on address bus
T2,T3, Tw, T4: Data is put on the data bus
AD15 – AD0: Time multiplexed address
and data lines
A19 – A16: Time multiplexed address
and status lines
Zelalem Birhanu, AAiT 8
10. • During T1 the address latch is enabled using the
signal ALE (ALE = 1)
• After T1 the data transceiver is enabled using the
signal DEN (DEN = 0)
• Since the data line is bidirectional, the signal
named DT/R is used to select direction of data
Memory Interfacing Signals…cntd
𝐷𝑇/ 𝑅 = 0 From memory to 8086
𝐷𝑇/ 𝑅 = 1 From 8086 to memory
Zelalem Birhanu, AAiT 10
12. • The 1MByte memory is organized as two
512KByte banks called upper (odd) bank and
lower (even) bank
Memory Interfacing Signals…cntd
Zelalem Birhanu, AAiT 12
13. • A memory bank to be accessed is selected using
the signals A0 (AD0) and 𝐵𝐻𝐸
Memory Interfacing Signals…cntd
𝐁𝐇𝐄 A0 Access Indications
0 0 Whole word (16-bits)
0 1 Upper byte from odd address
1 0 Lower byte from even address
1 1 None
Zelalem Birhanu, AAiT 13
16. S3 and S4
• Time multiplexed with A17 and A16
• Indicate which segment register is presently being used
for memory access
S5
• Time multiplexed with A18
• Shows the status of the interrupt enable flag bit and is
updated at the beginning of each clock cycle
Status Signals
S4 S3 Indications
0 0 ES
0 1 SS
1 0 CS or none
1 1 DS
Zelalem Birhanu, AAiT 16
17. Interrupt Signals
INTR (Interrupt request)
• This an interrupt request which is a high level triggered input
internally synchronized to the CPU
• It can be internally masked (disabled) by resetting the interrupt
enable flag
NMI (Non-Maskable Interrupt)
• Positive edge triggered interrupt
• Non maskable internally by software
Zelalem Birhanu, AAiT 17
18. Other Signals
CLK
• The clock input provides the basic timing for processor
operation and bus control activity. It’s an asymmetric square
wave with 33% duty cycle
𝑀𝑁/𝑀𝑋
• Indicates whether the processor is to operate in either minimum
(single processor) or maximum (multiprocessor) mode
READY
• This is the acknowledgement from the slow devices or memory
that they have completed the data transfer
Zelalem Birhanu, AAiT 18
20. I/O Addressing
• I/O devices contain registers to exchange data with the
CPU
• These registers are assigned addresses just like memory
locations
• 8086 can address up to a maximum of 64K I/O byte
registers
Zelalem Birhanu, AAiT 20
