Detail Description of instrcutions and addressing modes of 8085

1. Addressing Modes
and Instruction Set of
8085
1
SSP/EC-403/2021

2. Addressing Modes
• Addressing mode is the manner in which an operand
is given in an instruction.
• Operand: The value on which programmer want to
operate.
• Various formats for specifying operands are called
addressing modes.
• Types of addressing mode:
▫ Immediate Addressing
▫ Register Addressing
▫ Memory Direct Addressing
▫ Indirect Addressing
▫ Implicit or Implied Addressing
2
SSP/EC-403/2021

3. Immediate Addressing
• Data is given in the instruction.
• Transfers the operand given in the instruction.
• A byte or word – to the destination register or memory
location.
• Operand is part of the instruction.
• Operand is stored in the register mentioned in the
instruction.
• No memory reference to fetch data.
• Advantage:
▫ Executes faster
▫ Simple
• Disadvantage:
▫ Big instruction (Size)
• Eg: ADI 98H; MVI A 25H. LXI H 5000H Etc.
3
SSP/EC-403/2021

4. Immediate Addressing
SSP/EC-403/2021
4
Instruction
Opcode Operand
MVI A, 25
A 25H
25H

5. Register Addressing
• The data is given by a register.
• Transfers a copy of a byte or word from the source
register to the destination register.
• Operand is in the register named in the instruction.
• 1 byte instruction.
• The operand is within the processor, so the
execution is faster.
• Advantage:
▫ Faster
▫ Small size
• Disavantage:
▫ Very limited register space.
▫ Complex
• Eg: MOV A,B; ADD B etc,
5
SSP/EC-403/2021

6. Register Direct Addressing
SSP/EC-403/2021
6
Opcode Register Address Registers, in CPU
Operand
Instruction
MOV A,B
B
A
65H
65H

7. Memory Direct Addressing
• Moves a byte or word between memory
location and register.
• The memory address of the operand is given in
the instruction.
• Does not support memory to memory transfer.
• Advantage:
▫ Simple
• Disadvantage:
▫ Too large
▫ Rigid
• Eg: STA 9000H, LDA 9500H etc.
7
SSP/EC-403/2021

8. Memory Direct Addressing
SSP/EC-403/2021
8
Instruction
Opcode
Operand
Memory Address
Memory
STA 9000H
9000 A
45H
45H

9. Indirect Addressing
• Transfers a byte or word between a register and a
memory location.
• Address of a memory location is stored in a register
which is specified in the instruction.
• The effective address is calculated by the processor using
the content of the register specified in the instruction.
• Used to access series of locations.
• Advantage:
▫ Flexible
▫ Loops
• Disaadvantage:
▫ Complex
• Eg: MOV A,M; LDAX Rp; STAX Rp etc.
9
SSP/EC-403/2021

10. Indirect Addressing
SSP/EC-403/2021
10
Opcode Register Address
Memory
Operand
Instruction
Memory address
to operand
Register

11. Implicit or Implied Addressing
• We don’t give the data or address in the instruction.
• Instruction itself specifies the data to be operated
upon.
• Doesn’t required any operand.
• Used on particular operand.
• Advantage:
▫ Simple
▫ Small
• Disadvantage:
▫ Rigid
• Eg: CMA, XCHG,SPHL,XTHL etc.
CMA:
11
SSP/EC-403/2021
A 01H FFH

12. Quick Overview
• Immediate:
▫ Data in the instruction.
▫ MVI B, 40H B 40H
▫ LXIB, 4000H BC 4000H
• Register:
▫ Data is in the register.
▫ MOV A,B [A] [B]
▫ INR B [B] [B+1]
▫ INX B [BC] [BC+1]
• Direct:
▫ Address is in the instruction.
▫ LDA 8000H [A] [8000]
▫ STA 9000H [A] [9000]
• Indirect:
▫ Address is in the register.
▫ LDAX B [A] [BC]
▫ STAX B [A] [BC]
• Implied:
▫ Implied
▫ STC CY 1
▫ CMC CY CY
SSP/EC-403/2021
12

13. Instruction Set
 An instruction is a binary pattern designed inside a microprocessor to perform
a specific function.
 The assembly language mnemonics are the codes for these binary patterns so
that the user can easily understand the function performed by these
instructions.
 The entire group of instructions that a microprocessor supports is called
Instruction Set.
• Based on the design of the ALU and the decoding unit, the microprocessor
manufacturers generally list out the instruction set for the every
microprocessor manufactured.
• The purpose of an instruction set is to facilitate the development of efficient
programs by users.
• The instruction set is based on the architecture of the processor.
• Every µp has its own instruction set.
• Instruction set consist of both assembly language mnemonics and
corresponding machine code.
13
SSP/EC-403/2021

14. Instruction Set of 8085
• Intel 8085 processor has its own set of instructions listed
both in mnemonics and machine code, also called as
object code.
• As 8085 is an 8-bit processor.
• The machine codes for the instructions are also 8-bits
wide.
• It has 246 instructions.
 Each instruction is represented by an 8-bit binary value.
 These 8-bits of binary value is called Op-Code or
Instruction Byte
SSP/EC-403/2021
14

15. Classification of Instruction Set
Instruction set
Based on functionality Based on length
Data Transfer Instruction
Arithmetic Instructions
Logical Instructions
Branching Instructions
Stack/IO and Mc Control Instructions
One – byte
instruction
Two-byte
instruction
Three-byte
instruction
15
SSP/EC-403/2021

16. Classification of Instruction Set
• Based on length
▫ One- Byte Instructions
▫ Two- Byte Instructions
▫ Three- Byte Instructions
16
SSP/EC-403/2021

17. One- Byte Instructions
• Instructions require only one byte in machine
language.
• These instructions just have the machine code or
op-code to represent the operation to be
performed.
• Eg: MOV A,B ; ADD M; XRA A etc.
▫ MOV A,B Opcode One byte
17
SSP/EC-403/2021

18. Two- Byte Instructions
• Instructions that require two bytes in machine
code.
• The 1st byte : Op-code, which specifies the
operation to be performed.
• The 2nd byte : 8-bit operand, which is either an
8-bit number or an address.
• Eg: MVI A, 05H; ADI 0FH; IN 50H etc.
▫ MVI A 05H
18
SSP/EC-403/2021
Opcode 8-bit Operand
Two Byte

19. Three- Byte Instructions
• Instruction require three bytes in machine code.
• 1st byte: Op-code, which specifies the operation
to be performed.
• 2nd and 3rd byte: 16-bit operand, which is either
an 16-bit number or an address.
• Eg: LXI H 8500H; JMP 6900H, STA 7900H etc.
▫ STA 79 00H
19
SSP/EC-403/2021
Opcode Higher order
8-bit operand
Lower order
8-bit operand
Three Byte

20. Classification of Instruction Set
• Based on Functionality:
▫ Data Transfer Instruction
▫ Arithmetic Instructions
▫ Logical Instructions
▫ Branching Instructions
▫ Stack/IO and M/C Control Instructions
20
SSP/EC-403/2021

21. Data Transfer Instructions
• These instructions move data between registers,
or between memory and registers.
• These instructions copy data from source to
destination.
• Sometime data stored directly in designated
location.
• While copying, the contents of source are not
modified.
21
SSP/EC-403/2021

22. Data Transfer Instructions
• MOV B,C: Copy from source to destination.
• MVI C,05H: Load register C with the data 05H.
• LXI H,9000H: Load 9000H in HL register pair.
SSP/EC-403/2021
22
Source
Destination 88H
88H
[C] 05H
05H
[B] [C]
[H] [L] 90 00H
90 00

23. Data Transfer Instructions
• MVI M,25H: Put the data in memory location.
• MOV M,C: Copy the value of C to memory
location.
• MOV C,M:
SSP/EC-403/2021
23
[M] 25H 25H
[M]
C 80H
80H

24. Data Transfer Instructions
• LDA 8800H: Load the content of memory location 8800H in
the Accumulator.
• STA 2500H: The contents of accumulator are copied into the
memory location specified by the operand.
• STAX B: The contents of accumulator are copied into the
memory location specified by the contents of the register pair.
SSP/EC-403/2021
24
[8800] AF
[A] AF
[A]
[2500] 58
58
[B] [C]
85 89 [8589] [A] 6B
6B

25. Data Transfer Instructions
Op-code Operand Description
MOV Rd, Rs
M, Rs
Rd, M
Copy from source to destination.
MVI R,8 bit data Load register with 8 bit data.
LDA 16- bit
address
Load the content of memory location in
the Accumulator.
STA 16 bit
address
The contents of accumulator are copied
into the memory location specified by
the operand.
STAX Rp The contents of accumulator are copied
into the memory location specified by
the contents of the register pair.
LXI Rp,16 bit
data
Load the register pair immediate.
25
SSP/EC-403/2021

26. Arithmetic Instructions
• One of the data used in arithmetic operations is
stored in accumulator.
• Result is stored in accumulator.
• Arithmetic operations cannot be executed without
Acc.
• These instructions perform the operations like:
▫ Addition
▫ Subtraction
▫ Increment
▫ Decrement
26
SSP/EC-403/2021

27. Addition
• Any 8-bit number, or the contents of register, or the contents of
memory location can be added to the contents of accumulator.
• The result (sum) is stored in the accumulator.
• No two other 8-bit registers can be added directly.
Op-code Operand Description
ADD R
M
The contents of register or memory are added to
the contents of accumulator.
ADC R
M
Add with carry. The carry generated from the
previous operation is incorporated in this
addition.
ADI 05H The 8-bit data is added to the contents of
accumulator.
DAD B The 16-bit contents of the register pair are added
to the contents of H-L pair. The result is stored in
H-L pair. If the result is larger than 16 bits, then
CY is set.
DAA Decimal adjust after addition. It only used after
addition. This instruction doesn't have any
operand. It is only implied on Acc.
27
SSP/EC-403/2021

28. Subtraction
• Any 8-bit number, or the contents of register, or the
contents of memory location can be subtracted from
the contents of accumulator.
• The result is stored in the accumulator.
• Subtraction is performed in 2’s complement form.
• If the result is negative, it is stored in 2’s
complement form.
• No two other 8-bit registers can be subtracted
directly.
• Example: SUB B, SUB M, SUI data
28
SSP/EC-403/2021

29. Increment / Decrement
• The 8-bit contents of a register or a memory location can
be incremented or decremented by 1.
• The 16-bit contents of a register pair can be incremented
or decremented by 1.
• Increment or decrement can be performed on any
register or a memory location.
Op-code Operand Description
INR R
M
The contents of register or memory
location are incremented by 1..The
result is stored in the same place.
INX R The contents of register pair are
incremented by 1. The result is
stored in the same place.
29
SSP/EC-403/2021

30. Logical Instructions
• These instructions perform logical operations on
data stored in registers, memory and status flags
with the contents of accumulator.
• The result is stored in accumulator.
• The logical operations are:
▫ AND
▫ OR
▫ XOR
▫ Rotate
▫ Compare
▫ Complement
30
SSP/EC-403/2021

31. AND, OR, XOR
Op-code Operand Description
ANA R
M
The contents of the accumulator are logically
AND ed with the contents of register or memory.
The result is placed in the accumulator.
ANI 8-bit data The contents of the accumulator are logically
AND ed with the 8-bit data. The result is placed
in the accumulator.
ORA R
M
The contents of the accumulator are logically OR
ed with the contents of the register or memory.
The result is placed in the accumulator.
XRI 8-bit data The contents of the accumulator are XOR ed
with the 8-bit data. The result is placed in the
accumulator.
31
SSP/EC-403/2021

32. Rotate
• Each bit in the accumulator can be shifted either left or
right to the next position.
• RLC: Each binary bit of the accumulator is rotated left by
one position.
• RAL: Each binary bit of the accumulator is rotated left by
one position through the Carry flag.
SSP/EC-403/2021
32
7 6 5 4 3 2 1 0
C
Accumulator
7 6 5 4 3 2 1 0
C
Accumulator

33. Rotate Cont..
▫ RRC: Each binary bit of the accumulator is rotated
right by one position.
• RAR: Each binary bit of the accumulator is rotated right
by one position through the Carry flag.
SSP/EC-403/2021
33
7 6 5 4 3 2 1 0
Accumulator
7 6 5 4 3 2 1 0
Accumulator
C
C

34. Rotate
Op-code Operand Description
RLC None Each binary bit of the accumulator is rotated left
by one position. Bit D7 is placed in the position of
D0 as well as in the Carry flag. CY is modified
according to bit D7.
RAL None Each binary bit of the accumulator is rotated left
by one position through the Carry flag. Bit D7 is
placed in the Carry flag, and the Carry flag is
placed in the least significant position D0. CY is
modified according to bit D7.
RRC None Each binary bit of the accumulator is rotated right
by one position. Bit D0 is placed in the position of
D7 as well as in the Carry flag. CY is modified
according to bit D0.
RAR None Each binary bit of the accumulator is rotated right
by one position through the Carry flag. Bit D0 is
placed in the Carry flag, and the Carry flag is
placed in the most significant position D7. CY is
34

35. Compare
• Any 8-bit data, or the contents of register, or
memory location can be compares for:
▫ Equality
▫ Greater Than
▫ Less Than
with the contents of accumulator.
• The result is reflected in status flags.
35
SSP/EC-403/2021

36. Compare
Op-code Operand Description
CMP R
M
The contents of the operand (register or
memory) are compared with the contents
of the accumulator. Both contents are
preserved .
 The result of the comparison is shown by setting the flags
of the PSW as follows:
 if (A) < (reg/mem): carry flag is set
 if (A) = (reg/mem): zero flag is set
 if (A) > (reg/mem): carry and zero flags are reset.
36
SSP/EC-403/2021

37. Compare
Op-code Operand Description
CPI 8-bit data The 8-bit data is compared with the contents
of accumulator. The values being
compared remain unchanged.
 The result of the comparison is shown by setting the flags
of the PSW as follows:
 if (A) < data: carry flag is set
 if (A) = data: zero flag is set
 if (A) > data: carry and zero flags are reset
37
SSP/EC-403/2021

38. Complement
• The contents of accumulator can be complemented.
• Each 0 is replaced by 1 and each 1 is replaced by 0.
Op-code Operand Description
CMA None The contents of the accumulator are
complemented. No flags are affected.
CMC None The Carry flag is complemented. No
other flags are affected.
STC None The Carry flag is set to 1. No other flags
are affected.
38
SSP/EC-403/2021

39. Stack/IO and M/C Control
• Stack:
▫ PUSH
▫ POP
• I/O:
▫ IN
▫ OUT
• M/C Control:
▫ RIM
▫ SIM
▫ NOP
▫ HLT
▫ DI
▫ EI
SSP/EC-403/2021
39

40. I/O Operation
• Data will only able to transfer via Acc.
• Processor deals with one device at a time.
• Each and every I/O devices are signified by
address.
• The I/O address are known as port.
• It is 8-bit address.
• We can attach 28 ie. 256 devices with a
processor.
• IN 40H: A [40H]
• OUT 50H A [50H]
SSP/EC-403/2021
40

41. Control Instructions
• The control instructions control the operation of
microprocessor.
Opcode Description Status Flags
NOP None No operation is performed. The
instruction is fetched and decoded
but no operation is executed.
HLT None The CPU finishes executing the current
instruction and halts any further
execution. An interrupt or reset is
necessary to exit from the halt state.
DI None Disable interrupt. The interrupt enable
flip-flop is reset and all the interrupts
except the TRAP are disabled.
41
SSP/EC-403/2021

42. Branching Instructions
• The branching instruction alter the normal sequential
flow. Eg. JMP, CALL, RET,
• These instructions alter either unconditionally or
conditionally.
Op-code Operand Description
JMP 16-bit
address
Jump unconditionally. The program
sequence is transferred to the memory
location specified by the 16-bit address given
in the operand.
Jx 16-bit
address
Jump conditionally. The program sequence
is transferred to the memory location
specified by the 16-bit address given in the
operand based on the specified flag of the
PSW.
42
SSP/EC-403/2021

43. Jump Conditionally
Opcode Description Status Flags
JC Jump if Carry CY = 1
JNC Jump if No Carry CY = 0
JP Jump if Positive S = 0
JM Jump if Minus S = 1
JZ Jump if Zero Z = 1
JNZ Jump if No Zero Z = 0
JPE Jump if Parity
Even
P = 1
JPO Jump if Parity
Odd
P = 0
43
SSP/EC-403/2021

44. SSP/EC-403/2021
44