For the last five decades, electronic devices matured enough as the transistor size shrunk considerably. There by a new paradigm of ultra small scale device technology appeared and fuelled post CMOS device research. Consequently a classical manifestation of the quantization of electron charge evolved which is referred as Coulomb blocked in single Electronics Technology. This new technology ushered numerous figure of merit in nm scale electronics and soon single electronics was encoded to design logic circuits. But empirical studies revealed the limitations of room temperature based single electronics fabrication. Later on by amalgamating single electronics with conventional CMOS, addressed the limiting factors of single electronics fabrication. The new device principle is attributed as “Hybrid CMOS Single Electronics”. Since the last decade this hybrid topology is considered to design logic circuits similar to CMOS. Here the authors integrate classical CMOS with the uprising single electronics to model an expandable hardware and study its effectiveness to meet the current needs

1. Hybrid CMOS SET Based Expandable Hardware
Dr. JAYANTA GOPE
SANJAY BHADRA
SOUMYA GHATAK
PLABON SAHA
AALOK BHATTACHARYA
Authored by:-
Presented by
Soumya Ghatak
Dept. of Electrical Enginering
University of Engineering & Management, Kolkata

2. Work Outline
 INTRODUCTION
 Disadvantages of use of SET
 Why CMOS?
 OBJECTIVE
 HCS AND & HCS OR
 Circuit Diagram
 HYBRID CMOS SET ARCHITECTURE
 Circuit Diagram of Hybrid CMOS SET
 CONCLUSION
 References

3.  CMOS has been a necessary strategy to increase or improve the
performance of VLSI circuits.
Physically single electron transistors (SET) are devices comprising of
three-terminal switching technique.
It is composed of small conducting plates coupled to source and drain and
also coupled by capacitors to one or more gates.
It uses controlled electron tunneling to amplify current.
INTRODUCTION

4. Disadvantages of use of SET
 Small voltage gain
 High output impedance
 Sensitivity of background charges is also high

5. Why CMOS?
 High input impedance
 CMOS therefore, has a low out- put impedance
 CMOS works satisfactorily over wide temperature range.

6. By the combination of both CMOS and SET, hybrid SET-CMOS can be
made, and it is the only solution to the problems mentioned above. Authors
aim is to improve the performance of VLSI & ULSI circuits by using Hybrid
CMOS SET. In this paper, we are focusing to model an expandable hardware
and study its effectiveness to meet the current needs. For modeling/building up
an expandable hardware, we also concentrate to reduce the interconnects and
the unused space for making the circuit more compact.
OBJECTIVE

7.  HCS AND logic realization comprises of three n type MOSFET, six tunnel
junctions along with seven capacitors.
 Similarly HCS OR logic realization comprises the same.
HCS AND & HCS OR

8. Circuit Diagram of CMOS AND & OR GATE
CMOS SET Based AND Gate CMOS SET Based OR Gate

9.  Hybrid CMOS SET follows the same device principle of other low power
consuming nano devices.
The circuit comprises of forty-eight tunnel junction, fifty-six capacitor and
twenty-four n type MOSFET.
To make the circuit robust, non- vulnerable and to reduce the interconnects, the
interconnects are made lesser and also reduced the unused space in the proposed
Expandable Hardware model.
 JMS switching topology is used to construct the entire Hybrid CMOS SET
Expandable Hardware.
HYBRID CMOS SET ARCHITECTURE

10. HYBRID CMOS SET based Expandable hardware

11. CONCLUSION
 Hybrid CMOS SET adheres to the simple nm device principle without
compromising gain or other demerits of SET circuits. Being so Hybrid
CMOS SET is considered as more pragmatic substitute of CMOS. Hence the
authors advocate to include Hybrid CMOS SET in future VLSI circuits.
Besides the authors opted to design Hybrid CMOS SET Expandable
Hardware as because Expandable Hardware are largely envisaged as the
optimum solution of digital logic engineering. In other words it can be stated
that both the merits of CMOS and SET is combined and the shortcomings of
both the CMOS and SET is captivated

12. References
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CMOS logic circuits”, vol.3, pp 1671-1674, The 6th IEEE International Conference, September 1999.
 L. R. C. Fonseca, A. N. Korotkov and K. K. Likharev, “SENECA: a new program for the analysis of
single-electron devices”, VLSI Design, vol. 6, 1998, pp. 57-60.T.A. Fulton and G.J. Dolan, “Observation
of single-electron charging effects in small tunnel junctions”, Phys. Rev. Lett. 59, 109, July 1987.
 .S.Mahapatra, A.M. lonescu, K.Banejee, M.J.Declerq, “Modelling and analysis of power dissipation in
singleelectron logic”, Technical Digest of lEDM 2002.
 Dr. Jayanta Gope, Sanjay Bhadra, Md. Wasim Reja, Aquil Peyami, “Implementation of Low Power
Consuming Hybrid CMOS-SET Devices for Stair Case Lighting: A Case Study for Decision
MakingSubsystems”, International Journal of Scientific Engineering and Technology Research
(IJSETR), vol.04,Issue.10, April 2015, pp 1878-1881.
 Dr. J.Gope (MIEEE, CE), Sanjay Bhadra, S.Chowdhury (Kolay), M.Panda, N.Bhattacharya &
S.Bhadra, “JMS Hybrid Single Electron Model and its Simulation using MATLAB”, 2016 IEEE
7thAnnul Ubiquitous Computing ,Electronics and Mobile Computing(UEMCON).