2. Introduction.
Logic Styles.
Qualitative Logic Style Comparisons.
Power Estimations And Discussions .
Comparisons And Results.
Simulation Waveforms For Two-input Multiplexers.
Conclusion and Future Choice.
References.
3. Introduction
Because of the increased speed and density, power
consumption in CMOS VLSI Chips becomes increasingly
important.
Use of realistic circuit arrangements and comparisons
demonstrate CMOS to be superior to CPL in most cases
with respect to speed, area, power dissipation, and power
delay products.
This paper shows that complementary CMOS is the logic
style of choice for the simulation of arbitrary combinational
circuits.
4. The logic style used in logic gates basically influences the
speed, size, power dissipation, and the wiring complexity of a
circuit.
Important aspects influenced by the logic style are circuit
delay, power dissipation, robustness and compatibility.
Formula of logic style requirement for Low Power:
Pdyn= V²dd. fclk . Σ αn. cn + Σ Vdd . iscn
Switched Capacitance Reduction: Capacitive load, originating
from transistor capacitances and inter-connect wiring, is to
be minimized by having few transistors, circuit nodes and
minimized transistor sizes.
LOGIC STYLES
n n
5. Supply Voltage Reduction: It deals with logic style providing
fast logic gates to speed up critical signal paths which allows
a reduction of supply voltage in order to achieve a better
throughput.
Short-Circuit Current Reduction: It may vary by a
considerable amount between logic styles and depends on
input signal slopes and thus on transistor sizing.
Complementary CMOS logic style: Advantages of CMOS logic
style are its robustness against voltage scaling and transistor
sizing and reliable operation at low voltages and arbitrary
transistor sizes. Disadvantage of C²MOS is substantial
number of PMOS transistor resulting in high input load.
Cont…
6. Cont…
MUX2 (CMOS)
MUX (CPL)
MUX2(DPL)
CPL: The CPL logic has small input loads,
the efficient XOR and multiplexer gate im-
plementations, the good output driving ca-
pability due to output inverters.
DPL: It provides full swing on the output
sigals, and circuit robustness is high. The
combination of large PMOS transistors and
dual rail logic makes it incompetitive.
Other PT styles: SRPL is derived from CPL.
DPTL is generalised dual rail logic and
PPL is a CPL gate without output
s s
4.6
s
A
A
S
9
9
9
9
B
S
B
S
9
9
9
9
O
8,12
A
B
A
B
S
S
S
S
6
6
6
6
4
4
O
O
10,12
10,12
A
B
S
S
6
4
6
4
6
4
6
4
O
8,12
8,12
7. Power Estimations And Discussions
QUALITATIVE LOGIC STYLE COMPARISONS.
Logic
style+
#MOS
network
Output
driving
I/O
Decoup.
Swing
restor
#
rails
Robust
ness
CMOS n+p Med-good yes no Single high
CPL 2n good yes yes Dual medium
SRPL 2n poor no yes Dual low
DPL 2n+2p good yes no Dual high
EEPL 2n good yes yes Dual medium
PPL n+p poor no yes Dual low
Fig. circuit arrangement for
simulation of full adders
Some basic logic style characteristics which influence performance and
power dissipation are discussed in Table above.
The simple circuit setup allows application of arbitrary signal transition
combinations to the full-adder inputs, as well as consideration of output-
driving and fan-out characteristics.
n,p
n,p
n,p
A
B
C1
Logic
network
20fF
20fF
20fF
n,p
n,p
S
CO
8. Cont…
If we add logic power , clock power and total
wire power, we will find that logic depth
strongly influences power consumption.
When logic depth is larger than a certain value,
dynamic logic consumes more than static logic.
This is because relative number of clock driven
transistors is decreased in static logic when
increasing logic depth.
Fig. Power consumption of gates,
clock, and interconnections
versus logic depth.
Comparisons And Results:
Fig. simulated gates in CMOS (FA) and CPL logic styles
A
C
C
A
9
9
6
6
B
B
9
6
A
B
B
A
9
9
6
6
A
A
9
9
6
6
B
B
9
6
C
C
9
6
A
B
C
C
B
A
9
9
9
6
6
6
S
CO
8,12
8,12
B
B
A
A
A
A
A
A
B
A
A
CL
CL
CL
CL
S
CO
4
4
4
4
10,12
10,12
10,12
10,12
9. The multiplexer in complementary CMOS out performs all other
implementations wrt circuit delay, power, PT product and layout size.
Fig. below, confirms the well-known fact that gates without input-output
decoupling cannot be connected in series to form arbitrary circuits
without inserting buffers every few gates.
Fig. Simulation waveforms for 2-input multiplexers in CMOS, CPL, SRPL logic styles
10. CONCLUSION AND FUTURE CHOICE
CPL was found to be the most efficient pass-transistor logic
style.
C²MOS is however superior to CPL in all respect except for
few exceptions.
Except FA, static C²MOS performs much better than CPL
and other PT logic styles, if low power is of concern.
CMOS compares favourably with regard to circuit speed and
efficiency.
Its single-rail property is crucial for saving routing resources,
which is an important issue in submicron VLSI.
11. High end designs will have more severe problems in future
and the only way to handle this problem is to reduce supply
voltage.
For logic depths above six, static logic uses less power than
dynamic logic.
Therefore, when using domino logic, a larger share of the
total logic power must be supplied through the clock generator
which makes complementary CMOS the logic style of choice for
low power.
So, CMOS should be used for low voltage implementation of
arbitrary combinational circuits and for design automation,
also and particular in future.
12. REFERENCES
Low Power Logic Styles: Reto Zimmermann and Wolfgang
Fitchner, Fellow, IEEE journal, 1997.
Power Consumption Estimation in CMOS VLSI Chips: Dake
Liu and Christer Stevensson, IEEE journal of Solid State
Circuits, June 1994.
R. Zimmermann and R. Gupta, “Low Power Logic Styles:
CMOS versus CPL”, in Proc. 22nd
European Solid-State
circuits , vol. 31, pp. 841-846, June 1996.
R. Powell and P.M. Chan, “A model for estimating power
dissipaton in a class of VLSI Chips”, /EEE trans, circuits and
systems, vol. 38, no.6, June 1991.
